[{"id":1770074,"web_url":"http://patchwork.ozlabs.org/comment/1770074/","msgid":"<20170918105520.GA2837@kroah.com>","list_archive_url":null,"date":"2017-09-18T10:55:20","subject":"Re: [RFC RESEND 0/3] Add support for Hisilicon Hi3521A SoC","submitter":{"id":11800,"url":"http://patchwork.ozlabs.org/api/people/11800/","name":"Greg Kroah-Hartman","email":"gregkh@linuxfoundation.org"},"content":"On Sun, Sep 17, 2017 at 03:23:24AM -0500, Marty E. Plummer wrote:\n> Greetings,\n> \n> I'd like the community's feedback on the following patchset. I've attempted to\n> split my changes up in what I believe to be a sensible setup.\n> \n> The device I'm working against is the 'SamsungSV SDR-B74301' HD CCTV surveillance\n> system, which uses a Hisilicon Hi3521A arm SoC as its basis.\n> \n> Resending due to a typo, s/primcell/primecell/\n> \n> Marty E. Plummer (3):\n> clk: hisilicon: add CRG driver Hi3521A SoC\n> arm: hisi: enable Hi3521A SoC\n> arm: dts: add Hi3521A dts\n\nSeems reasonable to me, but I'll let the clk maintainers/developers give\nyou a better review...\n\nthanks,\n\ngreg k-h\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwjZn0llHz9s3T\n\tfor ;\n\tMon, 18 Sep 2017 20:55:12 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751878AbdIRKzK (ORCPT\n\t);\n\tMon, 18 Sep 2017 06:55:10 -0400","from mail.linuxfoundation.org ([140.211.169.12]:49024 \"EHLO\n\tmail.linuxfoundation.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751751AbdIRKzK (ORCPT\n\t); Mon, 18 Sep 2017 06:55:10 -0400","from localhost (LFbn-1-12253-150.w90-92.abo.wanadoo.fr\n\t[90.92.67.150])\n\tby mail.linuxfoundation.org (Postfix) with ESMTPSA id 2AF709F8;\n\tMon, 18 Sep 2017 10:55:09 +0000 (UTC)"],"Date":"Mon, 18 Sep 2017 12:55:20 +0200","From":"Greg KH ","To":"\"Marty E. Plummer\" ","Cc":"linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,\n\txuejiancheng@hisilicon.com, leo.yan@linaro.org,\n\tlinux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tmark.rutland@arm.com, mturquette@baylibre.com,\n\twenpan@hisilicon.com, robh+dt@kernel.org, linux@armlinux.org.uk,\n\tsboyd@codeaurora.org, xuwei5@hisilicon.com,\n\tzhangfei.gao@linaro.org, arnd@arndb.de","Subject":"Re: [RFC RESEND 0/3] Add support for Hisilicon Hi3521A SoC","Message-ID":"<20170918105520.GA2837@kroah.com>","References":"<20170917082327.10058-1-hanetzer@startmail.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170917082327.10058-1-hanetzer@startmail.com>","User-Agent":"Mutt/1.9.0 (2017-09-02)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1772215,"web_url":"http://patchwork.ozlabs.org/comment/1772215/","msgid":"<20170920205303.lcycfuai75a7namk@rob-hp-laptop>","list_archive_url":null,"date":"2017-09-20T20:53:03","subject":"Re: [RFC RESEND 3/3] arm: dts: add Hi3521A dts","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Sun, Sep 17, 2017 at 03:23:27AM -0500, Marty E. Plummer wrote:\n> Add hi3521a.dtsi and hi3521a-rs-dm290e.dts for RaySharp CCTV systems,\n> marketed under the name Samsung SDR-B74301N\n> \n> Signed-off-by: Marty E. Plummer \n> ---\n> arch/arm/boot/dts/Makefile | 2 +\n> arch/arm/boot/dts/hi3521a-rs-dm290e.dts | 52 ++++++\n> arch/arm/boot/dts/hi3521a.dtsi | 310 ++++++++++++++++++++++++++++++++\n> 3 files changed, 364 insertions(+)\n> create mode 100644 arch/arm/boot/dts/hi3521a-rs-dm290e.dts\n> create mode 100644 arch/arm/boot/dts/hi3521a.dtsi\n> \n> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile\n> index faf46abaa4a2..e7b9b5dde20f 100644\n> --- a/arch/arm/boot/dts/Makefile\n> +++ b/arch/arm/boot/dts/Makefile\n> @@ -189,6 +189,8 @@ dtb-$(CONFIG_ARCH_GEMINI) += \\\n> \tgemini-sq201.dtb \\\n> \tgemini-wbd111.dtb \\\n> \tgemini-wbd222.dtb\n> +dtb-$(CONFIG_ARCH_HI3521A) += \\\n> +\thi3521a-rs-dm290e.dtb\n> dtb-$(CONFIG_ARCH_HI3xxx) += \\\n> \thi3620-hi4511.dtb\n> dtb-$(CONFIG_ARCH_HIGHBANK) += \\\n> diff --git a/arch/arm/boot/dts/hi3521a-rs-dm290e.dts b/arch/arm/boot/dts/hi3521a-rs-dm290e.dts\n> new file mode 100644\n> index 000000000000..b32c8392c93f\n> --- /dev/null\n> +++ b/arch/arm/boot/dts/hi3521a-rs-dm290e.dts\n> @@ -0,0 +1,52 @@\n> +/*\n> + * Copyright (C) 2017 Marty Plummer \n> + *\n> + * This program is free software: you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License as published by\n> + * the Free Software Foundation, either version 3 of the License, or\n> + * (at your option) any later version.\n\nShould be version 2 or later? Doesn't really matter to me from a DT \nperspective, but it is in the kernel tree.\n\nYou can use SPDX tags if you want.\n\n> + *\n> + * This program is distributed in the hope that it will be useful,\n> + * but WITHOUT ANY WARRANTY; without even the implied warranty of\n> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n> + * GNU General Public License for more details.\n> + *\n> + * You should have received a copy of the GNU General Public License\n> + * along with this program. If not, see .\n> + */\n> +\n> +/dts-v1/;\n> +#include \"hi3521a.dtsi\"\n> +\n> +/ {\n> +\tmodel = \"RaySharp RS-DM-290E DVR Board\";\n> +\tcompatible = \"hisilicon,hi3521a\";\n\nNeeds a board compatible too.\n\n> +\n> +\taliases {\n> +\t\tserial0 = &uart0;\n> +\t\tserial1 = &uart1;\n> +\t\tserial2 = &uart2;\n> +\t};\n> +\n> +\tmemory {\n\nNeeds a unit-address.\n\n> +\t\tdevice_type = \"memory\";\n> +\t\treg = <0x80000000 0xf00000>;\n> +\t};\n> +};\n> +\n> +&hi_sfc {\n> +\tstatus = \"okay\";\n> +\tspi-nor@0 {\n> +\t\tcompatible = \"jedec,spi-nor\";\n\nI don't remember offhand, but I think this should have a device specific \ncompatible too.\n\n> +\t\treg = <0>;\n> +\t\tspi-max-frequency = <104000000>;\n> +\t};\n> +};\n> +\n> +&uart0 {\n> +\tstatus = \"okay\";\n> +};\n> +\n> +&dual_timer0 {\n> +\tstatus = \"okay\";\n> +};\n> diff --git a/arch/arm/boot/dts/hi3521a.dtsi b/arch/arm/boot/dts/hi3521a.dtsi\n> new file mode 100644\n> index 000000000000..2af746fdec46\n> --- /dev/null\n> +++ b/arch/arm/boot/dts/hi3521a.dtsi\n> @@ -0,0 +1,310 @@\n> +/*\n> + * Copyright (C) 2017 Marty Plummer \n> + *\n> + * This program is free software: you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License as published by\n> + * the Free Software Foundation, either version 3 of the License, or\n> + * (at your option) any later version.\n> + *\n> + * This program is distributed in the hope that it will be useful,\n> + * but WITHOUT ANY WARRANTY; without even the implied warranty of\n> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n> + * GNU General Public License for more details.\n> + *\n> + * You should have received a copy of the GNU General Public License\n> + * along with this program. If not, see .\n> + */\n> +\n> +#include \n> +#include \n> +/ {\n> +\t#address-cells = <1>;\n> +\t#size-cells = <1>;\n> +\tchosen { };\n> +\n> +\tcpus {\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\n> +\t\tcpu0: cpu@0 {\n> +\t\t\tdevice_type = \"cpu\";\n> +\t\t\tcompatible = \"arm,cortex-a7\";\n> +\t\t\treg = <0>;\n> +\t\t};\n> +\t};\n> +\n> +\thi_sfc: spi-nor-controller@10000000 {\n> +\t\tcompatible = \"hisilicon,hi3521a-spi-nor\", \"hisilicon,fmc-spi-nor\";\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\t\treg = <0x10000000 0x10000>, <0x14000000 0x1000000>;\n> +\t\treg-names = \"control\", \"memory\";\n> +\t\tclocks = <&crg HI3521A_FMC_CLK>;\n> +\t\tstatus = \"disabled\";\n> +\t};\n> +\n> +\tgic: interrupt-controller@10300000 {\n> +\t\tcompatible = \"arm,pl390\";\n> +\t\t#interrupt-cells = <3>;\n> +\t\tinterrupt-controller;\n> +\t\treg = <0x10301000 0x1000>, <0x10302000 0x1000>;\n> +\t};\n> +\n> +\tclk_3m: clk_3m {\n> +\t\tcompatible = \"fixed-clock\";\n> +\t\t#clock-cells = <0>;\n> +\t\tclock-frequency = <3000000>;\n> +\t};\n> +\n> +\tcrg: clock-reset-controller@12040000 {\n> +\t\tcompatible = \"hisilicon,hi3521a-crg\";\n> +\t\t#clock-cells = <1>;\n> +\t\t#reset-cells = <2>;\n> +\t\treg = <0x12040000 0x10000>;\n> +\t};\n\nThese memory mapped peripherals should be under a bus node.\n\n> +\n> +\tsoc {\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <1>;\n> +\t\tcompatible = \"simple-bus\";\n> +\t\tinterrupt-parent = <&gic>;\n> +\t\tranges;\n\nIt is preferred to have a value here and limit the range of the bus \naddresses.\n\n> +\n> +\t\tdmac: dma@10060000 {\n\ndma-controller@...\n\n> +\t\t\tcompatible = \"arm,pl080\", \"arm,primecell\";\n> +\t\t\treg = <0x10060000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tstatus = \"disabled\";\n\nI wouldn't think enabling dma would be a per board decision.\n\n> +\t\t};\n> +\n> +\t\tdual_timer0: timer@12000000 {\n> +\t\t\tcompatible = \"arm,sp804\", \"arm,primecell\";\n> +\t\t\tinterrupts = ,\n> +\t\t\t\t ;\n> +\t\t\treg = <0x12000000 0x1000>;\n> +\t\t\tclocks = <&clk_3m>;\n> +\t\t\tclock-names = \"apb_pclk\";\n\nIIRC, it is deprecated to have a single clock here. The h/w has 2 clock \ninputs.\n\nWhere's the ARM architected timer?\n\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tdual_timer1: timer@12010000 {\n> +\t\t\tcompatible = \"arm,sp804\", \"arm,primecell\";\n> +\t\t\tinterrupts = ,\n> +\t\t\t\t ;\n> +\t\t\treg = <0x12010000 0x1000>;\n> +\t\t\tclocks = <&clk_3m>;\n> +\t\t\tclock-name = \"apb_pclk\";\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tdual_timer2: timer@12020000 {\n> +\t\t\tcompatible = \"arm,sp804\", \"arm,primecell\";\n> +\t\t\tinterrupts = ,\n> +\t\t\t\t ;\n> +\t\t\treg = <0x12020000 0x1000>;\n> +\t\t\tclocks = <&clk_3m>;\n> +\t\t\tclock-name = \"apb_pclk\";\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tdual_timer3: timer@12030000 {\n> +\t\t\tcompatible = \"arm,sp804\", \"arm,primecell\";\n> +\t\t\tinterrupts = ,\n> +\t\t\t\t ;\n> +\t\t\treg = <0x12030000 0x1000>;\n> +\t\t\tclocks = <&clk_3m>;\n> +\t\t\tclock-name = \"apb_pclk\";\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\twdt0: watchdog@12070000 {\n> +\t\t\tcompatible = \"arm,sp805\", \"arm,primecell\";\n> +\t\t\tarm,primecell-periphid = <0x00141805>;\n> +\t\t\treg = <0x12070000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tclocks = <&clk_3m>;\n> +\t\t\tclock-names = \"apb_pclk\";\n> +\t\t};\n> +\n> +\t\tuart0: serial@12080000 {\n> +\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n> +\t\t\treg = <0x12080000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tclocks = <&crg HI3521A_UART0_CLK>;\n> +\t\t\tclock-names = \"apb_pclk\";\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tuart1: serial@12090000 {\n> +\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n> +\t\t\treg = <0x12090000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tclocks = <&crg HI3521A_UART1_CLK>;\n> +\t\t\tclock-names = \"apb_pclk\";\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tuart2: serial@120a0000 {\n> +\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n> +\t\t\treg = <0x120a0000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tclocks = <&crg HI3521A_UART2_CLK>;\n> +\t\t\tclock-names = \"apb_pclk\";\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tgpio0: gpio@12150000 {\n> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n> +\t\t\treg = <0x12150000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tgpio-controller;\n> +\t\t\t#gpio-cells = <2>;\n> +\t\t\tinterrupt-controller;\n> +\t\t\t#interrupt-cells = <2>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tgpio1: gpio@12160000 {\n> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n> +\t\t\treg = <0x12160000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tgpio-controller;\n> +\t\t\t#gpio-cells = <2>;\n> +\t\t\tinterrupt-controller;\n> +\t\t\t#interrupt-cells = <2>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tgpio2: gpio@12170000 {\n> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n> +\t\t\treg = <0x12170000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tgpio-controller;\n> +\t\t\t#gpio-cells = <2>;\n> +\t\t\tinterrupt-controller;\n> +\t\t\t#interrupt-cells = <2>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tgpio3: gpio@12180000 {\n> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n> +\t\t\treg = <0x12180000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tgpio-controller;\n> +\t\t\t#gpio-cells = <2>;\n> +\t\t\tinterrupt-controller;\n> +\t\t\t#interrupt-cells = <2>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tgpio4: gpio@12190000 {\n> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n> +\t\t\treg = <0x12190000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tgpio-controller;\n> +\t\t\t#gpio-cells = <2>;\n> +\t\t\tinterrupt-controller;\n> +\t\t\t#interrupt-cells = <2>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tgpio5: gpio@121a0000 {\n> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n> +\t\t\treg = <0x121a0000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tgpio-controller;\n> +\t\t\t#gpio-cells = <2>;\n> +\t\t\tinterrupt-controller;\n> +\t\t\t#interrupt-cells = <2>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tgpio6: gpio@121b0000 {\n> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n> +\t\t\treg = <0x121b0000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tgpio-controller;\n> +\t\t\t#gpio-cells = <2>;\n> +\t\t\tinterrupt-controller;\n> +\t\t\t#interrupt-cells = <2>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tgpio7: gpio@121c0000 {\n> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n> +\t\t\treg = <0x121c0000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tgpio-controller;\n> +\t\t\t#gpio-cells = <2>;\n> +\t\t\tinterrupt-controller;\n> +\t\t\t#interrupt-cells = <2>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tgpio8: gpio@121d0000 {\n> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n> +\t\t\treg = <0x121d0000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tgpio-controller;\n> +\t\t\t#gpio-cells = <2>;\n> +\t\t\tinterrupt-controller;\n> +\t\t\t#interrupt-cells = <2>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tgpio9: gpio@121e0000 {\n> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n> +\t\t\treg = <0x121e0000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tgpio-controller;\n> +\t\t\t#gpio-cells = <2>;\n> +\t\t\tinterrupt-controller;\n> +\t\t\t#interrupt-cells = <2>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tgpio10: gpio@121f0000 {\n> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n> +\t\t\treg = <0x121f0000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tgpio-controller;\n> +\t\t\t#gpio-cells = <2>;\n> +\t\t\tinterrupt-controller;\n> +\t\t\t#interrupt-cells = <2>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tgpio11: gpio@12200000 {\n> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n> +\t\t\treg = <0x12200000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tgpio-controller;\n> +\t\t\t#gpio-cells = <2>;\n> +\t\t\tinterrupt-controller;\n> +\t\t\t#interrupt-cells = <2>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tgpio12: gpio@12210000 {\n> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n> +\t\t\treg = <0x12210000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tgpio-controller;\n> +\t\t\t#gpio-cells = <2>;\n> +\t\t\tinterrupt-controller;\n> +\t\t\t#interrupt-cells = <2>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tgpio13: gpio@12220000 {\n> +\t\t\tcompatible = \"arm,pl061\", \"arm,primecell\";\n> +\t\t\treg = <0x12220000 0x1000>;\n> +\t\t\tinterrupts = ;\n> +\t\t\tgpio-controller;\n> +\t\t\t#gpio-cells = <2>;\n> +\t\t\tinterrupt-controller;\n> +\t\t\t#interrupt-cells = <2>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\t};\n> +};\n> -- \n> 2.14.1\n> \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at 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s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=haQhH2kKIgte1MVM9xbm9J2sKZpJGfQqofypYe2YN00=;\n\tb=aPGtqVUHvqcYlBEbDdHIt6zt7bwSkMaLAbaaczPg1GGIMi9mxljmzPnAffJYJjudIR\n\tVcuV5RkBujlse3JqcTN9eQPQDyrygwZ/Fb380DSwWsQFOVuQXXtT27opW0UB70CH0ilB\n\ts31b9FTmowh8I98lypIJhklgNLb3RlcYHQjhzVF5XCSp2S/73zsePpAFeNt3zl5c0DeD\n\tkS0ziO3meqng9qOEOGmP85WDJsrRH4VTGs6fiH1BoGmwrQssJzs0TnoOAL8bMgB+Z6Ss\n\tfNr1LqoEiJEN6IC/G/HQNUnlzu75Mf7yeCcUREqQimYF4LGPC6sf9/7hbdsrfdwEudVa\n\t/J4w==","X-Gm-Message-State":"AHPjjUgm1Ylo0QvfICPafAqI0JxEw0DppfGDyK6NxOSI19C1EnbOnv6m\n\tR2uaCwVISKMscQMqAtG45g==","X-Google-Smtp-Source":"AOwi7QBL0a9XL0pB4dxFxcXRmQ1jXhfmb+jEERxvFR3tEnOxHcMfAWYy23gdmSm5owWxEw3qZZyrgg==","X-Received":"by 10.98.58.221 with SMTP id v90mr3438790pfj.338.1505940784602; \n\tWed, 20 Sep 2017 13:53:04 -0700 (PDT)","Date":"Wed, 20 Sep 2017 15:53:03 -0500","From":"Rob Herring ","To":"\"Marty E. Plummer\" ","Cc":"linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,\n\txuejiancheng@hisilicon.com, leo.yan@linaro.org,\n\tlinux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tmark.rutland@arm.com, mturquette@baylibre.com,\n\twenpan@hisilicon.com, linux@armlinux.org.uk, sboyd@codeaurora.org,\n\txuwei5@hisilicon.com, zhangfei.gao@linaro.org,\n\tgregkh@linuxfoundation.org, arnd@arndb.de","Subject":"Re: [RFC RESEND 3/3] arm: dts: add Hi3521A dts","Message-ID":"<20170920205303.lcycfuai75a7namk@rob-hp-laptop>","References":"<20170917082327.10058-1-hanetzer@startmail.com>\n\t<20170917082327.10058-4-hanetzer@startmail.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170917082327.10058-4-hanetzer@startmail.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1772304,"web_url":"http://patchwork.ozlabs.org/comment/1772304/","msgid":"<20170920230405.tz3vzoys2vn72rgv@proprietary-killer.fossland>","list_archive_url":null,"date":"2017-09-20T23:04:12","subject":"Re: [RFC RESEND 3/3] arm: dts: add Hi3521A dts","submitter":{"id":72369,"url":"http://patchwork.ozlabs.org/api/people/72369/","name":"Marty E. Plummer","email":"hanetzer@startmail.com"},"content":"On Wed, Sep 20, 2017 at 08:53:03PM +0000, Rob Herring wrote:\n> On Sun, Sep 17, 2017 at 03:23:27AM -0500, Marty E. Plummer wrote:\n> > Add hi3521a.dtsi and hi3521a-rs-dm290e.dts for RaySharp CCTV systems,\n> > marketed under the name Samsung SDR-B74301N\n> > \n> > Signed-off-by: Marty E. Plummer \n> > ---\n> > arch/arm/boot/dts/Makefile | 2 +\n> > arch/arm/boot/dts/hi3521a-rs-dm290e.dts | 52 ++++++\n> > arch/arm/boot/dts/hi3521a.dtsi | 310 ++++++++++++++++++++++++++++++++\n> > 3 files changed, 364 insertions(+)\n> > create mode 100644 arch/arm/boot/dts/hi3521a-rs-dm290e.dts\n> > create mode 100644 arch/arm/boot/dts/hi3521a.dtsi\n> > \n> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile\n> > index faf46abaa4a2..e7b9b5dde20f 100644\n> > --- a/arch/arm/boot/dts/Makefile\n> > +++ b/arch/arm/boot/dts/Makefile\n> > @@ -189,6 +189,8 @@ dtb-$(CONFIG_ARCH_GEMINI) += \\\n> > \tgemini-sq201.dtb \\\n> > \tgemini-wbd111.dtb \\\n> > \tgemini-wbd222.dtb\n> > +dtb-$(CONFIG_ARCH_HI3521A) += \\\n> > +\thi3521a-rs-dm290e.dtb\n> > dtb-$(CONFIG_ARCH_HI3xxx) += \\\n> > \thi3620-hi4511.dtb\n> > dtb-$(CONFIG_ARCH_HIGHBANK) += \\\n> > diff --git a/arch/arm/boot/dts/hi3521a-rs-dm290e.dts b/arch/arm/boot/dts/hi3521a-rs-dm290e.dts\n> > new file mode 100644\n> > index 000000000000..b32c8392c93f\n> > --- /dev/null\n> > +++ b/arch/arm/boot/dts/hi3521a-rs-dm290e.dts\n> > @@ -0,0 +1,52 @@\n> > +/*\n> > + * Copyright (C) 2017 Marty Plummer \n> > + *\n> > + * This program is free software: you can redistribute it and/or modify\n> > + * it under the terms of the GNU General Public License as published by\n> > + * the Free Software Foundation, either version 3 of the License, or\n> > + * (at your option) any later version.\n> \n> Should be version 2 or later? Doesn't really matter to me from a DT \n> perspective, but it is in the kernel tree.\n> \n> You can use SPDX tags if you want.\n>\nOh, that's a good idea. I hadn't seen any SPDX tags in the tree that I\nnoticed before. I ended up just using the :Gpl command from neovim. \n> > + *\n> > + * This program is distributed in the hope that it will be useful,\n> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of\n> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n> > + * GNU General Public License for more details.\n> > + *\n> > + * You should have received a copy of the GNU General Public License\n> > + * along with this program. If not, see .\n> > + */\n> > +\n> > +/dts-v1/;\n> > +#include \"hi3521a.dtsi\"\n> > +\n> > +/ {\n> > +\tmodel = \"RaySharp RS-DM-290E DVR Board\";\n> > +\tcompatible = \"hisilicon,hi3521a\";\n> \n> Needs a board compatible too.\n>\nSomething like `compatible = \"hisilicon,hi3521a\", \"raysharp,rs-dm-290e\";` ? \n> > +\n> > +\taliases {\n> > +\t\tserial0 = &uart0;\n> > +\t\tserial1 = &uart1;\n> > +\t\tserial2 = &uart2;\n> > +\t};\n> > +\n> > +\tmemory {\n> \n> Needs a unit-address.\n>\nCould you explain what you mean here? As in, memory@someaddr? What would\nI use here? \n> > +\t\tdevice_type = \"memory\";\n> > +\t\treg = <0x80000000 0xf00000>;\n> > +\t};\n> > +};\n> > +\n> > +&hi_sfc {\n> > +\tstatus = \"okay\";\n> > +\tspi-nor@0 {\n> > +\t\tcompatible = \"jedec,spi-nor\";\n> \n> I don't remember offhand, but I think this should have a device specific \n> compatible too.\n>\nInstead of \"jedec,spi-nor\" ? Specific to the SPI chip? \n> > +\t\treg = <0>;\n> > +\t\tspi-max-frequency = <104000000>;\n> > +\t};\n> > +};\n> > +\n> > +&uart0 {\n> > +\tstatus = \"okay\";\n> > +};\n> > +\n> > +&dual_timer0 {\n> > +\tstatus = \"okay\";\n> > +};\n> > diff --git a/arch/arm/boot/dts/hi3521a.dtsi b/arch/arm/boot/dts/hi3521a.dtsi\n> > new file mode 100644\n> > index 000000000000..2af746fdec46\n> > --- /dev/null\n> > +++ b/arch/arm/boot/dts/hi3521a.dtsi\n> > @@ -0,0 +1,310 @@\n> > +/*\n> > + * Copyright (C) 2017 Marty Plummer \n> > + *\n> > + * This program is free software: you can redistribute it and/or modify\n> > + * it under the terms of the GNU General Public License as published by\n> > + * the Free Software Foundation, either version 3 of the License, or\n> > + * (at your option) any later version.\n> > + *\n> > + * This program is distributed in the hope that it will be useful,\n> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of\n> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n> > + * GNU General Public License for more details.\n> > + *\n> > + * You should have received a copy of the GNU General Public License\n> > + * along with this program. If not, see .\n> > + */\n> > +\n> > +#include \n> > +#include \n> > +/ {\n> > +\t#address-cells = <1>;\n> > +\t#size-cells = <1>;\n> > +\tchosen { };\n> > +\n> > +\tcpus {\n> > +\t\t#address-cells = <1>;\n> > +\t\t#size-cells = <0>;\n> > +\n> > +\t\tcpu0: cpu@0 {\n> > +\t\t\tdevice_type = \"cpu\";\n> > +\t\t\tcompatible = \"arm,cortex-a7\";\n> > +\t\t\treg = <0>;\n> > +\t\t};\n> > +\t};\n> > +\n> > +\thi_sfc: spi-nor-controller@10000000 {\n> > +\t\tcompatible = \"hisilicon,hi3521a-spi-nor\", \"hisilicon,fmc-spi-nor\";\n> > +\t\t#address-cells = <1>;\n> > +\t\t#size-cells = <0>;\n> > +\t\treg = <0x10000000 0x10000>, <0x14000000 0x1000000>;\n> > +\t\treg-names = \"control\", \"memory\";\n> > +\t\tclocks = <&crg HI3521A_FMC_CLK>;\n> > +\t\tstatus = \"disabled\";\n> > +\t};\n> > +\n> > +\tgic: interrupt-controller@10300000 {\n> > +\t\tcompatible = \"arm,pl390\";\n> > +\t\t#interrupt-cells = <3>;\n> > +\t\tinterrupt-controller;\n> > +\t\treg = <0x10301000 0x1000>, <0x10302000 0x1000>;\n> > +\t};\n> > +\n> > +\tclk_3m: clk_3m {\n> > +\t\tcompatible = \"fixed-clock\";\n> > +\t\t#clock-cells = <0>;\n> > +\t\tclock-frequency = <3000000>;\n> > +\t};\n> > +\n> > +\tcrg: clock-reset-controller@12040000 {\n> > +\t\tcompatible = \"hisilicon,hi3521a-crg\";\n> > +\t\t#clock-cells = <1>;\n> > +\t\t#reset-cells = <2>;\n> > +\t\treg = <0x12040000 0x10000>;\n> > +\t};\n> \n> These memory mapped peripherals should be under a bus node.\n>\nCrap, will fix. \n> > +\n> > +\tsoc {\n> > +\t\t#address-cells = <1>;\n> > +\t\t#size-cells = <1>;\n> > +\t\tcompatible = \"simple-bus\";\n> > +\t\tinterrupt-parent = <&gic>;\n> > +\t\tranges;\n> \n> It is preferred to have a value here and limit the range of the bus \n> addresses.\n> \nYeah, I think I've seen that before, I don't quite grok how that works.\n> > +\n> > +\t\tdmac: dma@10060000 {\n> \n> dma-controller@...\n> \nWill fix.\n> > +\t\t\tcompatible = \"arm,pl080\", \"arm,primecell\";\n> > +\t\t\treg = <0x10060000 0x1000>;\n> > +\t\t\tinterrupts = ;\n> > +\t\t\tstatus = \"disabled\";\n> \n> I wouldn't think enabling dma would be a per board decision.\n> \nI've just noticed that in general dtsi files just lay it all out and are\nmostly \"disabled\", though if you think this should be explicitly enabled\nthats fine by me.\n> > +\t\t};\n> > +\n> > +\t\tdual_timer0: timer@12000000 {\n> > +\t\t\tcompatible = \"arm,sp804\", \"arm,primecell\";\n> > +\t\t\tinterrupts = ,\n> > +\t\t\t\t ;\n> > +\t\t\treg = <0x12000000 0x1000>;\n> > +\t\t\tclocks = <&clk_3m>;\n> > +\t\t\tclock-names = \"apb_pclk\";\n> \n> IIRC, it is deprecated to have a single clock here. The h/w has 2 clock \n> inputs.\n>\nAre you meaning for the 0x0 index and 0x20 index clocks?\n> Where's the ARM architected timer?\n> \nUnsure tbqf, just doing my best to translate a datasheet into code. Do\nall ARM soc's have one?\n> > -- \n> > 2.14.1\n> > \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=startmail.com header.i=@startmail.com\n\theader.b=\"HnuWkCNx\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyFjt0w99z9sPk\n\tfor ;\n\tThu, 21 Sep 2017 09:06:42 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751821AbdITXGk (ORCPT\n\t);\n\tWed, 20 Sep 2017 19:06:40 -0400","from smx-7fb.smtp.startmail.com ([37.153.204.247]:43851 \"EHLO\n\tsmx-7fb.smtp.startmail.com\" rhost-flags-OK-OK-OK-OK)\n\tby vger.kernel.org with ESMTP id S1751584AbdITXGj (ORCPT\n\t); Wed, 20 Sep 2017 19:06:39 -0400","from smx-6f5.int1.startmail.com (smx-6f5.int1.startmail.com\n\t[10.116.2.63])\n\tby smx-7fb.smtp.startmail.com (Postfix) with ESMTPS id 942DFB7CD6;\n\tThu, 21 Sep 2017 01:06:36 +0200 (CEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=startmail.com;\n\ts=dkim; t=1505948796;\n\tbh=wH/jn8vnVRbnD81bzXnYz+gnwzP1g+99B2mPOAsvfzg=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=HnuWkCNxggf753F8gab2FcMRhYeBcUOrYmcSb2lu3q+/YYVLB9oCO7TwTNGoXUZEt\n\tXP8fKnzg1sv+wa7iEN49rKIoVatctNDIqn1NdqQWmnOFLzKRysxL8csmmbIkHxNm98\n\tNaRDOmWtGlTrkeYmdNmNoW20UMTdpKpMXWlhf96MFu2wpfqsjkZfZzUDs7nNTJK5iN\n\tvjUvyf3Sj0RbAswaytnJ1nykKf+MS/y7ex4ySo+9ANpO4YJWEfekKSWCkhIQUTScaX\n\tuQ7+tv4g5db0tg3pRlBWALjYdoYCc/lJoJTfIz06CprnSGnRgS1HZlTsFU5RZQ+9qh\n\td9Ni7vqZXbLAQ==","Date":"Wed, 20 Sep 2017 18:04:12 -0500","From":"\"Marty E. Plummer\" ","To":"Rob Herring ","Cc":"linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,\n\txuejiancheng@hisilicon.com, leo.yan@linaro.org,\n\tlinux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tmark.rutland@arm.com, mturquette@baylibre.com,\n\twenpan@hisilicon.com, linux@armlinux.org.uk, sboyd@codeaurora.org,\n\txuwei5@hisilicon.com, zhangfei.gao@linaro.org,\n\tgregkh@linuxfoundation.org, arnd@arndb.de","Subject":"Re: [RFC RESEND 3/3] arm: dts: add Hi3521A dts","Message-ID":"<20170920230405.tz3vzoys2vn72rgv@proprietary-killer.fossland>","References":"<20170917082327.10058-1-hanetzer@startmail.com>\n\t<20170917082327.10058-4-hanetzer@startmail.com>\n\t<20170920205303.lcycfuai75a7namk@rob-hp-laptop>","Mime-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170920205303.lcycfuai75a7namk@rob-hp-laptop>","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1772347,"web_url":"http://patchwork.ozlabs.org/comment/1772347/","msgid":"","list_archive_url":null,"date":"2017-09-21T01:08:39","subject":"Re: [RFC RESEND 3/3] arm: dts: add Hi3521A dts","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Wed, Sep 20, 2017 at 6:04 PM, Marty E. Plummer\n wrote:\n> On Wed, Sep 20, 2017 at 08:53:03PM +0000, Rob Herring wrote:\n>> On Sun, Sep 17, 2017 at 03:23:27AM -0500, Marty E. Plummer wrote:\n>> > Add hi3521a.dtsi and hi3521a-rs-dm290e.dts for RaySharp CCTV systems,\n>> > marketed under the name Samsung SDR-B74301N\n>> >\n>> > Signed-off-by: Marty E. Plummer \n>> > ---\n>> > arch/arm/boot/dts/Makefile | 2 +\n>> > arch/arm/boot/dts/hi3521a-rs-dm290e.dts | 52 ++++++\n>> > arch/arm/boot/dts/hi3521a.dtsi | 310 ++++++++++++++++++++++++++++++++\n>> > 3 files changed, 364 insertions(+)\n>> > create mode 100644 arch/arm/boot/dts/hi3521a-rs-dm290e.dts\n>> > create mode 100644 arch/arm/boot/dts/hi3521a.dtsi\n>> >\n>> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile\n>> > index faf46abaa4a2..e7b9b5dde20f 100644\n>> > --- a/arch/arm/boot/dts/Makefile\n>> > +++ b/arch/arm/boot/dts/Makefile\n>> > @@ -189,6 +189,8 @@ dtb-$(CONFIG_ARCH_GEMINI) += \\\n>> > gemini-sq201.dtb \\\n>> > gemini-wbd111.dtb \\\n>> > gemini-wbd222.dtb\n>> > +dtb-$(CONFIG_ARCH_HI3521A) += \\\n>> > + hi3521a-rs-dm290e.dtb\n>> > dtb-$(CONFIG_ARCH_HI3xxx) += \\\n>> > hi3620-hi4511.dtb\n>> > dtb-$(CONFIG_ARCH_HIGHBANK) += \\\n>> > diff --git a/arch/arm/boot/dts/hi3521a-rs-dm290e.dts b/arch/arm/boot/dts/hi3521a-rs-dm290e.dts\n>> > new file mode 100644\n>> > index 000000000000..b32c8392c93f\n>> > --- /dev/null\n>> > +++ b/arch/arm/boot/dts/hi3521a-rs-dm290e.dts\n>> > @@ -0,0 +1,52 @@\n>> > +/*\n>> > + * Copyright (C) 2017 Marty Plummer \n>> > + *\n>> > + * This program is free software: you can redistribute it and/or modify\n>> > + * it under the terms of the GNU General Public License as published by\n>> > + * the Free Software Foundation, either version 3 of the License, or\n>> > + * (at your option) any later version.\n>>\n>> Should be version 2 or later? Doesn't really matter to me from a DT\n>> perspective, but it is in the kernel tree.\n>>\n>> You can use SPDX tags if you want.\n>>\n> Oh, that's a good idea. I hadn't seen any SPDX tags in the tree that I\n> noticed before. I ended up just using the :Gpl command from neovim.\n>> > + *\n>> > + * This program is distributed in the hope that it will be useful,\n>> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of\n>> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n>> > + * GNU General Public License for more details.\n>> > + *\n>> > + * You should have received a copy of the GNU General Public License\n>> > + * along with this program. If not, see .\n>> > + */\n>> > +\n>> > +/dts-v1/;\n>> > +#include \"hi3521a.dtsi\"\n>> > +\n>> > +/ {\n>> > + model = \"RaySharp RS-DM-290E DVR Board\";\n>> > + compatible = \"hisilicon,hi3521a\";\n>>\n>> Needs a board compatible too.\n>>\n> Something like `compatible = \"hisilicon,hi3521a\", \"raysharp,rs-dm-290e\";` ?\n\nYes, but flip the order. Most specific compatible first.\n\n>> > +\n>> > + aliases {\n>> > + serial0 = &uart0;\n>> > + serial1 = &uart1;\n>> > + serial2 = &uart2;\n>> > + };\n>> > +\n>> > + memory {\n>>\n>> Needs a unit-address.\n>>\n> Could you explain what you mean here? As in, memory@someaddr? What would\n> I use here?\n\n\"memory@80000000\". Building with W=2 will tell you.\n\n>> > + device_type = \"memory\";\n>> > + reg = <0x80000000 0xf00000>;\n>> > + };\n>> > +};\n>> > +\n>> > +&hi_sfc {\n>> > + status = \"okay\";\n>> > + spi-nor@0 {\n>> > + compatible = \"jedec,spi-nor\";\n>>\n>> I don't remember offhand, but I think this should have a device specific\n>> compatible too.\n>>\n> Instead of \"jedec,spi-nor\" ? Specific to the SPI chip?\n\nNo, both with jedec,spi-nor 2nd.\n\n>> > + reg = <0>;\n>> > + spi-max-frequency = <104000000>;\n>> > + };\n>> > +};\n>> > +\n>> > +&uart0 {\n>> > + status = \"okay\";\n>> > +};\n>> > +\n>> > +&dual_timer0 {\n>> > + status = \"okay\";\n>> > +};\n>> > diff --git a/arch/arm/boot/dts/hi3521a.dtsi b/arch/arm/boot/dts/hi3521a.dtsi\n>> > new file mode 100644\n>> > index 000000000000..2af746fdec46\n>> > --- /dev/null\n>> > +++ b/arch/arm/boot/dts/hi3521a.dtsi\n>> > @@ -0,0 +1,310 @@\n>> > +/*\n>> > + * Copyright (C) 2017 Marty Plummer \n>> > + *\n>> > + * This program is free software: you can redistribute it and/or modify\n>> > + * it under the terms of the GNU General Public License as published by\n>> > + * the Free Software Foundation, either version 3 of the License, or\n>> > + * (at your option) any later version.\n>> > + *\n>> > + * This program is distributed in the hope that it will be useful,\n>> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of\n>> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n>> > + * GNU General Public License for more details.\n>> > + *\n>> > + * You should have received a copy of the GNU General Public License\n>> > + * along with this program. If not, see .\n>> > + */\n>> > +\n>> > +#include \n>> > +#include \n>> > +/ {\n>> > + #address-cells = <1>;\n>> > + #size-cells = <1>;\n>> > + chosen { };\n>> > +\n>> > + cpus {\n>> > + #address-cells = <1>;\n>> > + #size-cells = <0>;\n>> > +\n>> > + cpu0: cpu@0 {\n>> > + device_type = \"cpu\";\n>> > + compatible = \"arm,cortex-a7\";\n>> > + reg = <0>;\n>> > + };\n>> > + };\n>> > +\n>> > + hi_sfc: spi-nor-controller@10000000 {\n>> > + compatible = \"hisilicon,hi3521a-spi-nor\", \"hisilicon,fmc-spi-nor\";\n>> > + #address-cells = <1>;\n>> > + #size-cells = <0>;\n>> > + reg = <0x10000000 0x10000>, <0x14000000 0x1000000>;\n>> > + reg-names = \"control\", \"memory\";\n>> > + clocks = <&crg HI3521A_FMC_CLK>;\n>> > + status = \"disabled\";\n>> > + };\n>> > +\n>> > + gic: interrupt-controller@10300000 {\n>> > + compatible = \"arm,pl390\";\n>> > + #interrupt-cells = <3>;\n>> > + interrupt-controller;\n>> > + reg = <0x10301000 0x1000>, <0x10302000 0x1000>;\n>> > + };\n>> > +\n>> > + clk_3m: clk_3m {\n>> > + compatible = \"fixed-clock\";\n>> > + #clock-cells = <0>;\n>> > + clock-frequency = <3000000>;\n>> > + };\n>> > +\n>> > + crg: clock-reset-controller@12040000 {\n>> > + compatible = \"hisilicon,hi3521a-crg\";\n>> > + #clock-cells = <1>;\n>> > + #reset-cells = <2>;\n>> > + reg = <0x12040000 0x10000>;\n>> > + };\n>>\n>> These memory mapped peripherals should be under a bus node.\n>>\n> Crap, will fix.\n>> > +\n>> > + soc {\n>> > + #address-cells = <1>;\n>> > + #size-cells = <1>;\n>> > + compatible = \"simple-bus\";\n>> > + interrupt-parent = <&gic>;\n>> > + ranges;\n>>\n>> It is preferred to have a value here and limit the range of the bus\n>> addresses.\n>>\n> Yeah, I think I've seen that before, I don't quite grok how that works.\n>> > +\n>> > + dmac: dma@10060000 {\n>>\n>> dma-controller@...\n>>\n> Will fix.\n>> > + compatible = \"arm,pl080\", \"arm,primecell\";\n>> > + reg = <0x10060000 0x1000>;\n>> > + interrupts = ;\n>> > + status = \"disabled\";\n>>\n>> I wouldn't think enabling dma would be a per board decision.\n>>\n> I've just noticed that in general dtsi files just lay it all out and are\n> mostly \"disabled\", though if you think this should be explicitly enabled\n> thats fine by me.\n>> > + };\n>> > +\n>> > + dual_timer0: timer@12000000 {\n>> > + compatible = \"arm,sp804\", \"arm,primecell\";\n>> > + interrupts = ,\n>> > + ;\n>> > + reg = <0x12000000 0x1000>;\n>> > + clocks = <&clk_3m>;\n>> > + clock-names = \"apb_pclk\";\n>>\n>> IIRC, it is deprecated to have a single clock here. The h/w has 2 clock\n>> inputs.\n>>\n> Are you meaning for the 0x0 index and 0x20 index clocks?\n\nYes. Maybe it's 3 clocks. Anyway, should all be in the sp804 binding doc.\n\n>> Where's the ARM architected timer?\n>>\n> Unsure tbqf, just doing my best to translate a datasheet into code. Do\n> all ARM soc's have one?\n\nAll A7's should I think.\n\nRob\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=robh@kernel.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyJR439Dmz9s0g\n\tfor ;\n\tThu, 21 Sep 2017 11:09:04 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751842AbdIUBJC (ORCPT\n\t);\n\tWed, 20 Sep 2017 21:09:02 -0400","from mail.kernel.org ([198.145.29.99]:40812 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751681AbdIUBJC (ORCPT );\n\tWed, 20 Sep 2017 21:09:02 -0400","from mail-qk0-f169.google.com (mail-qk0-f169.google.com\n\t[209.85.220.169])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 55EAB217C2;\n\tThu, 21 Sep 2017 01:09:01 +0000 (UTC)","by mail-qk0-f169.google.com with SMTP id b23so4445769qkg.1;\n\tWed, 20 Sep 2017 18:09:01 -0700 (PDT)","by 10.12.209.75 with HTTP; Wed, 20 Sep 2017 18:08:39 -0700 (PDT)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org 55EAB217C2","X-Gm-Message-State":"AHPjjUghv8JWIat0N/Eze2eHynuitPaM+DuNhLBY2FuPzrSsoGoWgOCM\n\tZbv2EyC66kl/STvOalhIDgJsaK5ZWeUTFwoxUA==","X-Google-Smtp-Source":"AOwi7QBa48dZga+8EJP4NPfzWC8OQUh6rmDn1yFI4066BdNKKSUCwA+JO6DbBaAdsdNTmo/y6w51mrbvfWi7AMOw7xw=","X-Received":"by 10.55.78.144 with SMTP id c138mr816533qkb.67.1505956140421;\n\tWed, 20 Sep 2017 18:09:00 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170920230405.tz3vzoys2vn72rgv@proprietary-killer.fossland>","References":"<20170917082327.10058-1-hanetzer@startmail.com>\n\t<20170917082327.10058-4-hanetzer@startmail.com>\n\t<20170920205303.lcycfuai75a7namk@rob-hp-laptop>\n\t<20170920230405.tz3vzoys2vn72rgv@proprietary-killer.fossland>","From":"Rob Herring ","Date":"Wed, 20 Sep 2017 20:08:39 -0500","X-Gmail-Original-Message-ID":"","Message-ID":"","Subject":"Re: [RFC RESEND 3/3] arm: dts: add Hi3521A dts","To":"\"Marty E. Plummer\" ","Cc":"\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"devicetree@vger.kernel.org\" ,\n\tJiancheng Xue ,\n\tLeo Yan , linux-clk ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\tMark Rutland ,\n\tMichael Turquette ,\n\tPan Wen , Russell King , \n\tStephen Boyd , Wei Xu ,\n\tZhangfei Gao ,\n\tGreg Kroah-Hartman ,\n\tArnd Bergmann ","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1772370,"web_url":"http://patchwork.ozlabs.org/comment/1772370/","msgid":"<20170921021511.q6cbew5d5ec5cxxd@proprietary-killer.fossland>","list_archive_url":null,"date":"2017-09-21T02:15:16","subject":"Re: [RFC RESEND 3/3] arm: dts: add Hi3521A dts","submitter":{"id":72369,"url":"http://patchwork.ozlabs.org/api/people/72369/","name":"Marty E. Plummer","email":"hanetzer@startmail.com"},"content":"On Thu, Sep 21, 2017 at 01:08:39AM +0000, Rob Herring wrote:\n> On Wed, Sep 20, 2017 at 6:04 PM, Marty E. Plummer\n> wrote:\n> > On Wed, Sep 20, 2017 at 08:53:03PM +0000, Rob Herring wrote:\n> >> On Sun, Sep 17, 2017 at 03:23:27AM -0500, Marty E. Plummer wrote:\n> >> > Add hi3521a.dtsi and hi3521a-rs-dm290e.dts for RaySharp CCTV systems,\n> >> > marketed under the name Samsung SDR-B74301N\n> >> >\n> >> > Signed-off-by: Marty E. Plummer \n> >> > ---\n> >> > arch/arm/boot/dts/Makefile | 2 +\n> >> > arch/arm/boot/dts/hi3521a-rs-dm290e.dts | 52 ++++++\n> >> > arch/arm/boot/dts/hi3521a.dtsi | 310 ++++++++++++++++++++++++++++++++\n> >> > 3 files changed, 364 insertions(+)\n> >> > create mode 100644 arch/arm/boot/dts/hi3521a-rs-dm290e.dts\n> >> > create mode 100644 arch/arm/boot/dts/hi3521a.dtsi\n> >> >\n> >> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile\n> >> > index faf46abaa4a2..e7b9b5dde20f 100644\n> >> > --- a/arch/arm/boot/dts/Makefile\n> >> > +++ b/arch/arm/boot/dts/Makefile\n> >> > @@ -189,6 +189,8 @@ dtb-$(CONFIG_ARCH_GEMINI) += \\\n> >> > gemini-sq201.dtb \\\n> >> > gemini-wbd111.dtb \\\n> >> > gemini-wbd222.dtb\n> >> > +dtb-$(CONFIG_ARCH_HI3521A) += \\\n> >> > + hi3521a-rs-dm290e.dtb\n> >> > dtb-$(CONFIG_ARCH_HI3xxx) += \\\n> >> > hi3620-hi4511.dtb\n> >> > dtb-$(CONFIG_ARCH_HIGHBANK) += \\\n> >> > diff --git a/arch/arm/boot/dts/hi3521a-rs-dm290e.dts b/arch/arm/boot/dts/hi3521a-rs-dm290e.dts\n> >> > new file mode 100644\n> >> > index 000000000000..b32c8392c93f\n> >> > --- /dev/null\n> >> > +++ b/arch/arm/boot/dts/hi3521a-rs-dm290e.dts\n> >> > @@ -0,0 +1,52 @@\n> >> > +/*\n> >> > + * Copyright (C) 2017 Marty Plummer \n> >> > + *\n> >> > + * This program is free software: you can redistribute it and/or modify\n> >> > + * it under the terms of the GNU General Public License as published by\n> >> > + * the Free Software Foundation, either version 3 of the License, or\n> >> > + * (at your option) any later version.\n> >>\n> >> Should be version 2 or later? Doesn't really matter to me from a DT\n> >> perspective, but it is in the kernel tree.\n> >>\n> >> You can use SPDX tags if you want.\n> >>\n> > Oh, that's a good idea. I hadn't seen any SPDX tags in the tree that I\n> > noticed before. I ended up just using the :Gpl command from neovim.\n> >> > + *\n> >> > + * This program is distributed in the hope that it will be useful,\n> >> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of\n> >> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n> >> > + * GNU General Public License for more details.\n> >> > + *\n> >> > + * You should have received a copy of the GNU General Public License\n> >> > + * along with this program. If not, see .\n> >> > + */\n> >> > +\n> >> > +/dts-v1/;\n> >> > +#include \"hi3521a.dtsi\"\n> >> > +\n> >> > +/ {\n> >> > + model = \"RaySharp RS-DM-290E DVR Board\";\n> >> > + compatible = \"hisilicon,hi3521a\";\n> >>\n> >> Needs a board compatible too.\n> >>\n> > Something like `compatible = \"hisilicon,hi3521a\", \"raysharp,rs-dm-290e\";` ?\n> \n> Yes, but flip the order. Most specific compatible first.\n> \n> >> > +\n> >> > + aliases {\n> >> > + serial0 = &uart0;\n> >> > + serial1 = &uart1;\n> >> > + serial2 = &uart2;\n> >> > + };\n> >> > +\n> >> > + memory {\n> >>\n> >> Needs a unit-address.\n> >>\n> > Could you explain what you mean here? As in, memory@someaddr? What would\n> > I use here?\n> \n> \"memory@80000000\". Building with W=2 will tell you.\n> \nAh, nice trick. Suppose that makes sense, as every other thing was the\nsame on that sort of thing. Not sure if I've ever seen memory@addr\nbefore.\n> >> > + device_type = \"memory\";\n> >> > + reg = <0x80000000 0xf00000>;\n> >> > + };\n> >> > +};\n> >> > +\n> >> > +&hi_sfc {\n> >> > + status = \"okay\";\n> >> > + spi-nor@0 {\n> >> > + compatible = \"jedec,spi-nor\";\n> >>\n> >> I don't remember offhand, but I think this should have a device specific\n> >> compatible too.\n> >>\n> > Instead of \"jedec,spi-nor\" ? Specific to the SPI chip?\n> \n> No, both with jedec,spi-nor 2nd.\n> \nGotcha, will fix it up.\n> >> > + reg = <0>;\n> >> > + spi-max-frequency = <104000000>;\n> >> > + };\n> >> > +};\n> >> > +\n> >> > +&uart0 {\n> >> > + status = \"okay\";\n> >> > +};\n> >> > +\n> >> > +&dual_timer0 {\n> >> > + status = \"okay\";\n> >> > +};\n> >> > diff --git a/arch/arm/boot/dts/hi3521a.dtsi b/arch/arm/boot/dts/hi3521a.dtsi\n> >> > new file mode 100644\n> >> > index 000000000000..2af746fdec46\n> >> > --- /dev/null\n> >> > +++ b/arch/arm/boot/dts/hi3521a.dtsi\n> >> > @@ -0,0 +1,310 @@\n> >> > +/*\n> >> > + * Copyright (C) 2017 Marty Plummer \n> >> > + *\n> >> > + * This program is free software: you can redistribute it and/or modify\n> >> > + * it under the terms of the GNU General Public License as published by\n> >> > + * the Free Software Foundation, either version 3 of the License, or\n> >> > + * (at your option) any later version.\n> >> > + *\n> >> > + * This program is distributed in the hope that it will be useful,\n> >> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of\n> >> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n> >> > + * GNU General Public License for more details.\n> >> > + *\n> >> > + * You should have received a copy of the GNU General Public License\n> >> > + * along with this program. If not, see .\n> >> > + */\n> >> > +\n> >> > +#include \n> >> > +#include \n> >> > +/ {\n> >> > + #address-cells = <1>;\n> >> > + #size-cells = <1>;\n> >> > + chosen { };\n> >> > +\n> >> > + cpus {\n> >> > + #address-cells = <1>;\n> >> > + #size-cells = <0>;\n> >> > +\n> >> > + cpu0: cpu@0 {\n> >> > + device_type = \"cpu\";\n> >> > + compatible = \"arm,cortex-a7\";\n> >> > + reg = <0>;\n> >> > + };\n> >> > + };\n> >> > +\n> >> > + hi_sfc: spi-nor-controller@10000000 {\n> >> > + compatible = \"hisilicon,hi3521a-spi-nor\", \"hisilicon,fmc-spi-nor\";\n> >> > + #address-cells = <1>;\n> >> > + #size-cells = <0>;\n> >> > + reg = <0x10000000 0x10000>, <0x14000000 0x1000000>;\n> >> > + reg-names = \"control\", \"memory\";\n> >> > + clocks = <&crg HI3521A_FMC_CLK>;\n> >> > + status = \"disabled\";\n> >> > + };\n> >> > +\n> >> > + gic: interrupt-controller@10300000 {\n> >> > + compatible = \"arm,pl390\";\n> >> > + #interrupt-cells = <3>;\n> >> > + interrupt-controller;\n> >> > + reg = <0x10301000 0x1000>, <0x10302000 0x1000>;\n> >> > + };\n> >> > +\n> >> > + clk_3m: clk_3m {\n> >> > + compatible = \"fixed-clock\";\n> >> > + #clock-cells = <0>;\n> >> > + clock-frequency = <3000000>;\n> >> > + };\n> >> > +\n> >> > + crg: clock-reset-controller@12040000 {\n> >> > + compatible = \"hisilicon,hi3521a-crg\";\n> >> > + #clock-cells = <1>;\n> >> > + #reset-cells = <2>;\n> >> > + reg = <0x12040000 0x10000>;\n> >> > + };\n> >>\n> >> These memory mapped peripherals should be under a bus node.\n> >>\n> > Crap, will fix.\n> >> > +\n> >> > + soc {\n> >> > + #address-cells = <1>;\n> >> > + #size-cells = <1>;\n> >> > + compatible = \"simple-bus\";\n> >> > + interrupt-parent = <&gic>;\n> >> > + ranges;\n> >>\n> >> It is preferred to have a value here and limit the range of the bus\n> >> addresses.\n> >>\n> > Yeah, I think I've seen that before, I don't quite grok how that works.\n> >> > +\n> >> > + dmac: dma@10060000 {\n> >>\n> >> dma-controller@...\n> >>\n> > Will fix.\n> >> > + compatible = \"arm,pl080\", \"arm,primecell\";\n> >> > + reg = <0x10060000 0x1000>;\n> >> > + interrupts = ;\n> >> > + status = \"disabled\";\n> >>\n> >> I wouldn't think enabling dma would be a per board decision.\n> >>\n> > I've just noticed that in general dtsi files just lay it all out and are\n> > mostly \"disabled\", though if you think this should be explicitly enabled\n> > thats fine by me.\n> >> > + };\n> >> > +\n> >> > + dual_timer0: timer@12000000 {\n> >> > + compatible = \"arm,sp804\", \"arm,primecell\";\n> >> > + interrupts = ,\n> >> > + ;\n> >> > + reg = <0x12000000 0x1000>;\n> >> > + clocks = <&clk_3m>;\n> >> > + clock-names = \"apb_pclk\";\n> >>\n> >> IIRC, it is deprecated to have a single clock here. The h/w has 2 clock\n> >> inputs.\n> >>\n> > Are you meaning for the 0x0 index and 0x20 index clocks?\n> \n> Yes. Maybe it's 3 clocks. Anyway, should all be in the sp804 binding doc.\n> \n> >> Where's the ARM architected timer?\n> >>\n> > Unsure tbqf, just doing my best to translate a datasheet into code. Do\n> > all ARM soc's have one?\n> \n> All A7's should I think.\n> \nGotcha.\n> Rob\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=startmail.com header.i=@startmail.com\n\theader.b=\"iO9xgrBO\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyKyN2Hvgz9sPm\n\tfor ;\n\tThu, 21 Sep 2017 12:17:48 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751621AbdIUCRp (ORCPT\n\t);\n\tWed, 20 Sep 2017 22:17:45 -0400","from smx-7fb.smtp.startmail.com ([37.153.204.247]:58528 \"EHLO\n\tsmx-7fb.smtp.startmail.com\" rhost-flags-OK-OK-OK-OK)\n\tby vger.kernel.org with ESMTP id S1751095AbdIUCRo (ORCPT\n\t); Wed, 20 Sep 2017 22:17:44 -0400","from smx-6f5.int1.startmail.com (smx-6f5.int1.startmail.com\n\t[10.116.2.63])\n\tby smx-7fb.smtp.startmail.com (Postfix) with ESMTPS id 53F5AB7B1B;\n\tThu, 21 Sep 2017 04:17:42 +0200 (CEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=startmail.com;\n\ts=dkim; t=1505960262;\n\tbh=/HUCnSzFQbVK55ypapOTMIfyXbrFf5ZGraZLHe3DuLU=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=iO9xgrBOOsVAKtMVYWBSrXIEzd0KFPSRXSOxiSDXA7WdiGLPjC0YbI3bKeWZ7p3/J\n\tJHIFnIoDhPi9/clmV58HtU1Jo87B9KkdCxZIXNoQ8fHy8IUItF/Mtfy46/oohHGir5\n\t0sLO9NtbPoZOq9Zs4UfYWokXiqwDAqtUNkV4v5RCt9nILOhOjtPrrRfOcvzm1QCcy+\n\tO9teVuegeanXoLkWstwgaxpdz5KfHMXBfOZfzISqtJJW8szP+k7+n7hyILOOTFVHW9\n\tSdLEc2udWe4ZgLh0JjYfqpc22YRHJ9hONks7U2gTd+EGWnUNePllUiRlMQKLDel+S9\n\ty5KaHebd107pA==","Date":"Wed, 20 Sep 2017 21:15:16 -0500","From":"\"Marty E. Plummer\" ","To":"Rob Herring ","Cc":"linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,\n\txuejiancheng@hisilicon.com, leo.yan@linaro.org,\n\tlinux-clk@vger.kernel.org, \n\t\"linux-kernel@vger.kernel.org\" ,\n\tmark.rutland@arm.com, mturquette@baylibre.com,\n\twenpan@hisilicon.com, linux@armlinux.org.uk, sboyd@codeaurora.org,\n\txuwei5@hisilicon.com, zhangfei.gao@linaro.org,\n\tgregkh@linuxfoundation.org, arnd@arndb.de","Subject":"Re: [RFC RESEND 3/3] arm: dts: add Hi3521A dts","Message-ID":"<20170921021511.q6cbew5d5ec5cxxd@proprietary-killer.fossland>","References":"<20170917082327.10058-1-hanetzer@startmail.com>\n\t<20170917082327.10058-4-hanetzer@startmail.com>\n\t<20170920205303.lcycfuai75a7namk@rob-hp-laptop>\n\t<20170920230405.tz3vzoys2vn72rgv@proprietary-killer.fossland>\n\t","Mime-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]