[{"id":1771194,"web_url":"http://patchwork.ozlabs.org/comment/1771194/","msgid":"<6028407.VKu5LCmQv0@sbruens-linux>","list_archive_url":null,"date":"2017-09-19T16:17:59","subject":"Re: [PATCH v2 07/10] dmaengine: sun6i: Retrieve channel count/max\n\trequest from devicetree","submitter":{"id":67055,"url":"http://patchwork.ozlabs.org/api/people/67055/","name":"Stefan Brüns","email":"stefan.bruens@rwth-aachen.de"},"content":"On Dienstag, 19. September 2017 16:25:08 CEST Maxime Ripard wrote:\n> On Mon, Sep 18, 2017 at 02:09:43PM +0000, Brüns, Stefan wrote:\n> > On Montag, 18. September 2017 10:18:24 CEST you wrote:\n> > > Hi,\n> > > \n> > > On Sun, Sep 17, 2017 at 05:19:53AM +0200, Stefan Brüns wrote:\n> > > > +\tret = of_property_read_u32(np, \"dma-channels\", &sdc->num_pchans);\n> > > > +\tif (ret && !sdc->num_pchans) {\n> > > > +\t\tdev_err(&pdev->dev, \"Can't get dma-channels.\\n\");\n> > > > +\t\treturn ret;\n> > > > +\t}\n> > > > +\n> > > > +\tif (sdc->num_pchans > DMA_MAX_CHANNELS) {\n> > > > +\t\tdev_err(&pdev->dev, \"Number of dma-channels out of range.\\n\");\n> > > > +\t\treturn -EINVAL;\n> > > > +\t}\n> > > > +\n> > > > +\tret = of_property_read_u32(np, \"dma-requests\", &sdc->max_request);\n> > > > +\tif (ret && !sdc->max_request) {\n> > > > +\t\tdev_info(&pdev->dev, \"Missing dma-requests, using %u.\\n\",\n> > > > +\t\t\t DMA_CHAN_MAX_DRQ);\n> > > > +\t\tsdc->max_request = DMA_CHAN_MAX_DRQ;\n> > > > +\t}\n> > > > +\n> > > > +\tif (sdc->max_request > DMA_CHAN_MAX_DRQ) {\n> > > > +\t\tdev_err(&pdev->dev, \"Value of dma-requests out of range.\\n\");\n> > > > +\t\treturn -EINVAL;\n> > > > +\t}\n> > > \n> > > I'm not really convinced about these two checks. They don't catch all\n> > > errors (the range between the actual number of channels / DRQ and the\n> > > maximum allowed per the registers), they might increase in the future\n> > > too, and if we want to make that check actually working, we would have\n> > > to duplicate the number of requests and channels into the driver.\n> > \n> > 1. If these values increase, we have a new register layout and and\n> > need a new compatible anyway.\n> \n> And you want to store a new maximum attached to the compatible? Isn't\n> that exactly the situation you're trying to get away from?\n\nYes, and no. H3, H5, A64 and R40 have the exact same register layout, but \ndifferent number of channels and ports. They could share a compatible (if DMA \nchannels were generalized), and we already have several register offsets/\nwidths (implicitly via the callbacks) attached to the compatible (so these \ndon't need generalization via DT).\n\nNow, we could also move everything that is currently attached to the \ncompatible, i.e. clock gate register offset, burst widths/lengths etc. into \nthe devicetree binding, but that would just be too much.\n\nThe idea is to find a middle ground here, using common patterns in the \nexisting SoCs. The register layout has hardly changed, while the number of DMA \nchannels and ports changes all the time. Moving the number of DMA channels and \nports to the DT is trivial, and a pattern also found in other DMA controller \ndrivers. *If* the number of dma channels and ports is ever increased, \nexceeding the current maximum, this would amount to major changes in the \ndriver and maybe even warrant a completely new driver.\n\n> > 2. As long as the the limits are adhered to, no other registers/register\n> > fields are overwritten. As the channel number and port are used to\n> > calculate memory offsets bounds checking is IMHO a good idea.\n> \n> And this is true for many other resources, starting with the one\n> defined in reg. We don't error check every register range, clock\n> index, reset line, interrupt, DMA channel, the memory size, etc. yet\n> you could make the same argument.\n> \n> The DT has to be right, and we have to trust it. Otherwise we can just\n> throw it away.\n\nSo your argument here basically is - don't do any checks on DT provided \nvalues, these are always correct. So, following this argument, not only the \nrange check, but also the of_property_read return values should be ignored, as \nthe DT is correct, thus of_property_read will never return an error.\n\nThat clearly does not match the implementation of drivers throughout the \nvarious subsystems for DT properties, which is in general - do all the checks \nthat can be done, trust everything you can not verify.\n\nKind regards,\n\nStefan","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"UB2rdL3E\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxSjP3m2Cz9ryT\n\tfor ;\n\tWed, 20 Sep 2017 02:18:33 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1duLEE-0007dz-6T; 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bh=BVsalSnmfxZsKNOqEfjZkU/xULWELfQ3AD0tBNPXhDY=;\n\tb=UB2rdL3EscAq8Z\n\t+7c7HQN5/G5zCH4vfH5wUFKUkYomR+eYb4GOLNI54446TzAZZpZLxJEBdTi+up61Wi1BkysXDj1rj\n\tW876sZzAOoc3uqmhWse8HBS2oIUWlK88KcHqsnvVlRA48GNYam7wQSuMD6n/GXYiRAm7I2LyInTi1\n\tCpVJOsQ/AjGoTILtWo3MjroUFQC6/RydtmdE5vbcU01ub05mRI9YXhFHd9bjrAxT8dysswhkppHhN\n\tRkdwg7uMtQjpTSEKI6bKObzId1s2jqfJUefu9KT8EXNadXensfniY7Bms08h0ZTuDivymRvoFlHRR\n\tZH2fZy+FzvgA0N9QEddA==;","X-IronPort-AV":"E=Sophos;i=\"5.42,418,1500933600\"; d=\"scan'208\";a=\"14129079\"","From":"=?iso-8859-1?q?Br=FCns=2C_Stefan?= ","To":"Maxime Ripard ","Subject":"Re: [PATCH v2 07/10] dmaengine: sun6i: Retrieve channel count/max\n\trequest from devicetree","Thread-Topic":"[PATCH v2 07/10] dmaengine: sun6i: Retrieve channel count/max\n\trequest from devicetree","Thread-Index":"AQHTMFlrb6IcqOdVukugQ6LTh2jDNqK8Q3uA","Date":"Tue, 19 Sep 2017 16:17:59 +0000","Message-ID":"<6028407.VKu5LCmQv0@sbruens-linux>","References":"<20170917031956.28010-1-stefan.bruens@rwth-aachen.de>\n\t<2791817.czGZyN6WKS@sbruens-linux>\n\t<20170919142508.woslovwjtecgygpo@flea.lan>","In-Reply-To":"<20170919142508.woslovwjtecgygpo@flea.lan>","Accept-Language":"en-US, de-DE","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[78.35.13.203]","Content-ID":"<60C30A0C0F582C4E9A9378499AFB4D7D@rwth-ad.de>","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170919_091826_601764_4F8FCA0B ","X-CRM114-Status":"GOOD ( 18.08 )","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [134.130.5.46 listed in list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"devicetree@vger.kernel.org\" ,\n\tVinod Koul ,\n\tAndre Przywara , \n\t\"linux-kernel@vger.kernel.org\" ,\n\tCode Kipper ,\n\t\"linux-sunxi@googlegroups.com\" ,\n\tRob Herring ,\n\t\"dmaengine@vger.kernel.org\" ,\n\tChen-Yu Tsai , \"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Type":"text/plain; charset=\"iso-8859-1\"","Content-Transfer-Encoding":"quoted-printable","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1773897,"web_url":"http://patchwork.ozlabs.org/comment/1773897/","msgid":"<20170922213027.xpnaut3an5or6edl@flea.home>","list_archive_url":null,"date":"2017-09-22T21:30:27","subject":"Re: [PATCH v2 07/10] dmaengine: sun6i: Retrieve channel count/max\n\trequest from devicetree","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Tue, Sep 19, 2017 at 04:17:59PM +0000, Brüns, Stefan wrote:\n> On Dienstag, 19. September 2017 16:25:08 CEST Maxime Ripard wrote:\n> > On Mon, Sep 18, 2017 at 02:09:43PM +0000, Brüns, Stefan wrote:\n> > > On Montag, 18. September 2017 10:18:24 CEST you wrote:\n> > > > Hi,\n> > > > \n> > > > On Sun, Sep 17, 2017 at 05:19:53AM +0200, Stefan Brüns wrote:\n> > > > > +\tret = of_property_read_u32(np, \"dma-channels\", &sdc->num_pchans);\n> > > > > +\tif (ret && !sdc->num_pchans) {\n> > > > > +\t\tdev_err(&pdev->dev, \"Can't get dma-channels.\\n\");\n> > > > > +\t\treturn ret;\n> > > > > +\t}\n> > > > > +\n> > > > > +\tif (sdc->num_pchans > DMA_MAX_CHANNELS) {\n> > > > > +\t\tdev_err(&pdev->dev, \"Number of dma-channels out of range.\\n\");\n> > > > > +\t\treturn -EINVAL;\n> > > > > +\t}\n> > > > > +\n> > > > > +\tret = of_property_read_u32(np, \"dma-requests\", &sdc->max_request);\n> > > > > +\tif (ret && !sdc->max_request) {\n> > > > > +\t\tdev_info(&pdev->dev, \"Missing dma-requests, using %u.\\n\",\n> > > > > +\t\t\t DMA_CHAN_MAX_DRQ);\n> > > > > +\t\tsdc->max_request = DMA_CHAN_MAX_DRQ;\n> > > > > +\t}\n> > > > > +\n> > > > > +\tif (sdc->max_request > DMA_CHAN_MAX_DRQ) {\n> > > > > +\t\tdev_err(&pdev->dev, \"Value of dma-requests out of range.\\n\");\n> > > > > +\t\treturn -EINVAL;\n> > > > > +\t}\n> > > > \n> > > > I'm not really convinced about these two checks. They don't catch all\n> > > > errors (the range between the actual number of channels / DRQ and the\n> > > > maximum allowed per the registers), they might increase in the future\n> > > > too, and if we want to make that check actually working, we would have\n> > > > to duplicate the number of requests and channels into the driver.\n> > > \n> > > 1. If these values increase, we have a new register layout and and\n> > > need a new compatible anyway.\n> > \n> > And you want to store a new maximum attached to the compatible? Isn't\n> > that exactly the situation you're trying to get away from?\n> \n> Yes, and no. H3, H5, A64 and R40 have the exact same register layout, but \n> different number of channels and ports. They could share a compatible (if DMA \n> channels were generalized), and we already have several register offsets/\n> widths (implicitly via the callbacks) attached to the compatible (so these \n> don't need generalization via DT).\n> \n> Now, we could also move everything that is currently attached to the \n> compatible, i.e. clock gate register offset, burst widths/lengths etc. into \n> the devicetree binding, but that would just be too much.\n> \n> The idea is to find a middle ground here, using common patterns in the \n> existing SoCs. The register layout has hardly changed, while the number of DMA \n> channels and ports changes all the time. Moving the number of DMA channels and \n> ports to the DT is trivial, and a pattern also found in other DMA controller \n> drivers.\n\nI'm sorry, but the code is inconsistent here. You basically have two\nvariables from one SoC to the other, the number of channels and\nrequests.\n\nIn one case (channels), it mandates that the property is provided in\nthe device tree, and doesn't default to anything.\n\nIn the other case (requests), the property is optional and it will\nprovide a default. All that in 20 lines.\n\nI guess we already reached that middle ground by providing them\nthrough the DT, we just have to make sure we remain consistent.\n\n> *If* the number of dma channels and ports is ever increased,\n> exceeding the current maximum, this would amount to major changes in\n> the driver and maybe even warrant a completely new driver.\n> \n> > > 2. As long as the the limits are adhered to, no other registers/register\n> > > fields are overwritten. As the channel number and port are used to\n> > > calculate memory offsets bounds checking is IMHO a good idea.\n> > \n> > And this is true for many other resources, starting with the one\n> > defined in reg. We don't error check every register range, clock\n> > index, reset line, interrupt, DMA channel, the memory size, etc. yet\n> > you could make the same argument.\n> > \n> > The DT has to be right, and we have to trust it. Otherwise we can just\n> > throw it away.\n> \n> So your argument here basically is - don't do any checks on DT provided \n> values, these are always correct. So, following this argument, not only the \n> range check, but also the of_property_read return values should be ignored, as \n> the DT is correct, thus of_property_read will never return an error.\n\nNo, my argument is don't do a check if you can catch only half of the\nerrors, and with no hope of fixing it.\n\nThe functions you mentionned have a 100% error catch rate. This is the\ndifference.\n\n> That clearly does not match the implementation of drivers throughout the \n> various subsystems for DT properties, which is in general - do all the checks \n> that can be done, trust everything you can not verify.\n\nAnd my point is that we're falling into the latter here. You cannot\nverify it properly.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"SeB67vQ1\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzRVl1q7Kz9sRm\n\tfor ;\n\tSat, 23 Sep 2017 07:31:11 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dvVXN-0001f2-Np; Fri, 22 Sep 2017 21:31:05 +0000","from mail.free-electrons.com ([62.4.15.54])\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dvVXI-0001Zn-Ry for linux-arm-kernel@lists.infradead.org;\n\tFri, 22 Sep 2017 21:31:03 +0000","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 2B29720A1A; Fri, 22 Sep 2017 23:30:37 +0200 (CEST)","from localhost (LFbn-TOU-1-209-191.w86-201.abo.wanadoo.fr\n\t[86.201.56.191])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id F15C420A10;\n\tFri, 22 Sep 2017 23:30:26 +0200 (CEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type:Cc:\n\tList-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:\n\tIn-Reply-To:MIME-Version:References:Message-ID:Subject:To:From:Date:Reply-To:\n\tContent-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;\n\tbh=/AY1j1vgT932CopW6gqO10PhJ02S0Du8GKpQ3JZkRmo=;\n\tb=SeB67vQ1rMirYXlccxHYBBtQV\n\tBI0KWrZ+s2n9sEwnNJucSPxEvSrsG8FyR2jtUrOp3ifVKNTyHSet+LZGNzkR9um5rYsD0r2LphLzV\n\tRcmZJb8N2E9SfkmgKVX76WKX/17czY1vKrD4KTAO2ibdq0pUkj3IwEDFmzStWj4cerQ1OEakChTIV\n\t/dgmLNEUICu+jFtQvsKCBgyYuackJendN+9+cBlL7jDHfdhjJuRL+DNsHX4bbGW9rROZQFHwSKrfK\n\tMRDWix+O/+wQ/BeFokcq5ZvcKc9cmhKx+4OJLGpmoWl03Z2IN8BbcSzWGZLdb1g6el2KtRy9+mxf9\n\twz3JhbOSg==;","X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Fri, 22 Sep 2017 23:30:27 +0200","From":"Maxime Ripard ","To":"=?iso-8859-1?q?Br=FCns=2C?= Stefan ","Subject":"Re: [PATCH v2 07/10] dmaengine: sun6i: Retrieve channel count/max\n\trequest from devicetree","Message-ID":"<20170922213027.xpnaut3an5or6edl@flea.home>","References":"<20170917031956.28010-1-stefan.bruens@rwth-aachen.de>\n\t<2791817.czGZyN6WKS@sbruens-linux>\n\t<20170919142508.woslovwjtecgygpo@flea.lan>\n\t<6028407.VKu5LCmQv0@sbruens-linux>","MIME-Version":"1.0","In-Reply-To":"<6028407.VKu5LCmQv0@sbruens-linux>","User-Agent":"NeoMutt/20170914 (1.9.0)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170922_143101_218643_AA123F45 ","X-CRM114-Status":"GOOD ( 29.48 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"devicetree@vger.kernel.org\" ,\n\tVinod Koul ,\n\tAndre Przywara , \n\t\"linux-kernel@vger.kernel.org\" ,\n\tCode Kipper ,\n\t\"linux-sunxi@googlegroups.com\" ,\n\tRob Herring ,\n\t\"dmaengine@vger.kernel.org\" ,\n\tChen-Yu Tsai , \"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Type":"multipart/mixed;\n\tboundary=\"===============8033499863611904360==\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1773942,"web_url":"http://patchwork.ozlabs.org/comment/1773942/","msgid":"<3154933.I7MMVk5mkV@sbruens-linux>","list_archive_url":null,"date":"2017-09-23T00:00:15","subject":"Re: [PATCH v2 07/10] dmaengine: sun6i: Retrieve channel count/max\n\trequest from devicetree","submitter":{"id":67055,"url":"http://patchwork.ozlabs.org/api/people/67055/","name":"Stefan Brüns","email":"stefan.bruens@rwth-aachen.de"},"content":"On Freitag, 22. September 2017 23:30:27 CEST Maxime Ripard wrote:\n> On Tue, Sep 19, 2017 at 04:17:59PM +0000, Brüns, Stefan wrote:\n> > On Dienstag, 19. September 2017 16:25:08 CEST Maxime Ripard wrote:\n> > > On Mon, Sep 18, 2017 at 02:09:43PM +0000, Brüns, Stefan wrote:\n> > > > On Montag, 18. September 2017 10:18:24 CEST you wrote:\n> > > > > Hi,\n> > > > > \n> > > > > On Sun, Sep 17, 2017 at 05:19:53AM +0200, Stefan Brüns wrote:\n> > > > > > +\tret = of_property_read_u32(np, \"dma-channels\",\n> > > > > > &sdc->num_pchans);\n> > > > > > +\tif (ret && !sdc->num_pchans) {\n> > > > > > +\t\tdev_err(&pdev->dev, \"Can't get dma-channels.\\n\");\n> > > > > > +\t\treturn ret;\n> > > > > > +\t}\n> > > > > > +\n> > > > > > +\tif (sdc->num_pchans > DMA_MAX_CHANNELS) {\n> > > > > > +\t\tdev_err(&pdev->dev, \"Number of dma-channels out of range.\n\\n\");\n> > > > > > +\t\treturn -EINVAL;\n> > > > > > +\t}\n> > > > > > +\n> > > > > > +\tret = of_property_read_u32(np, \"dma-requests\",\n> > > > > > &sdc->max_request);\n> > > > > > +\tif (ret && !sdc->max_request) {\n> > > > > > +\t\tdev_info(&pdev->dev, \"Missing dma-requests, using %u.\\n\",\n> > > > > > +\t\t\t DMA_CHAN_MAX_DRQ);\n> > > > > > +\t\tsdc->max_request = DMA_CHAN_MAX_DRQ;\n> > > > > > +\t}\n> > > > > > +\n> > > > > > +\tif (sdc->max_request > DMA_CHAN_MAX_DRQ) {\n> > > > > > +\t\tdev_err(&pdev->dev, \"Value of dma-requests out of range.\\n\");\n> > > > > > +\t\treturn -EINVAL;\n> > > > > > +\t}\n> > > > > \n> > > > > I'm not really convinced about these two checks. They don't catch\n> > > > > all\n> > > > > errors (the range between the actual number of channels / DRQ and\n> > > > > the\n> > > > > maximum allowed per the registers), they might increase in the\n> > > > > future\n> > > > > too, and if we want to make that check actually working, we would\n> > > > > have\n> > > > > to duplicate the number of requests and channels into the driver.\n> > > > \n> > > > 1. If these values increase, we have a new register layout and and\n> > > > need a new compatible anyway.\n> > > \n> > > And you want to store a new maximum attached to the compatible? Isn't\n> > > that exactly the situation you're trying to get away from?\n> > \n> > Yes, and no. H3, H5, A64 and R40 have the exact same register layout, but\n> > different number of channels and ports. They could share a compatible (if\n> > DMA channels were generalized), and we already have several register\n> > offsets/ widths (implicitly via the callbacks) attached to the compatible\n> > (so these don't need generalization via DT).\n> > \n> > Now, we could also move everything that is currently attached to the\n> > compatible, i.e. clock gate register offset, burst widths/lengths etc.\n> > into\n> > the devicetree binding, but that would just be too much.\n> > \n> > The idea is to find a middle ground here, using common patterns in the\n> > existing SoCs. The register layout has hardly changed, while the number of\n> > DMA channels and ports changes all the time. Moving the number of DMA\n> > channels and ports to the DT is trivial, and a pattern also found in\n> > other DMA controller drivers.\n> \n> I'm sorry, but the code is inconsistent here. You basically have two\n> variables from one SoC to the other, the number of channels and\n> requests.\n> \n> In one case (channels), it mandates that the property is provided in\n> the device tree, and doesn't default to anything.\n> \n> In the other case (requests), the property is optional and it will\n> provide a default. All that in 20 lines.\n\nThe channel number is a hardware property. Using more channels than the \nhardware provides is a bug. There is no default.\n\nThe port/request is just some lax property to limit the resource allocation \nupfront. As long as the bindings of the different IP blocks (SPI, audio, ...) \nprovide the correct port numbers, all required information is available.\n \n> I guess we already reached that middle ground by providing them\n> through the DT, we just have to make sure we remain consistent.\n> \n> > *If* the number of dma channels and ports is ever increased,\n> > exceeding the current maximum, this would amount to major changes in\n> > the driver and maybe even warrant a completely new driver.\n> > \n> > > > 2. As long as the the limits are adhered to, no other\n> > > > registers/register\n> > > > fields are overwritten. As the channel number and port are used to\n> > > > calculate memory offsets bounds checking is IMHO a good idea.\n> > > \n> > > And this is true for many other resources, starting with the one\n> > > defined in reg. We don't error check every register range, clock\n> > > index, reset line, interrupt, DMA channel, the memory size, etc. yet\n> > > you could make the same argument.\n> > > \n> > > The DT has to be right, and we have to trust it. Otherwise we can just\n> > > throw it away.\n> > \n> > So your argument here basically is - don't do any checks on DT provided\n> > values, these are always correct. So, following this argument, not only\n> > the\n> > range check, but also the of_property_read return values should be\n> > ignored, as the DT is correct, thus of_property_read will never return an\n> > error.\n> No, my argument is don't do a check if you can catch only half of the\n> errors, and with no hope of fixing it.\n> \n> The functions you mentionned have a 100% error catch rate. This is the\n> difference.\n> \n> > That clearly does not match the implementation of drivers throughout the\n> > various subsystems for DT properties, which is in general - do all the\n> > checks that can be done, trust everything you can not verify.\n> \n> And my point is that we're falling into the latter here. You cannot\n> verify it properly.\n\nPlease check the following line:\n\nhttps://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/\ndrivers/dma/sun6i-dma.c#n951\n\nThats far from 100% - the highest allowed port for each SoC differs between RX \nand TX, and port allocation is sparse.\n\nRegards,\n\nStefan","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"Sby6UwkU\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzVqs298tz9sNw\n\tfor ;\n\tSat, 23 Sep 2017 10:01:10 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dvXsP-0002Dd-3v; Sat, 23 Sep 2017 00:00:57 +0000","from mail-out-1.itc.rwth-aachen.de ([134.130.5.46])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dvXsB-00026c-5P for linux-arm-kernel@lists.infradead.org;\n\tSat, 23 Sep 2017 00:00:47 +0000","from rwthex-s3-a.rwth-ad.de ([134.130.26.160])\n\tby mail-in-1.itc.rwth-aachen.de with ESMTP; 23 Sep 2017 02:00:15 +0200","from rwthex-w2-a.rwth-ad.de (2002:8682:1a9e::8682:1a9e) by\n\trwthex-s3-a.rwth-ad.de (2002:8682:1aa0::8682:1aa0) with Microsoft\n\tSMTP Server\n\t(version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id\n\t15.1.1034.26; Sat, 23 Sep 2017 02:00:15 +0200","from rwthex-w2-a.rwth-ad.de ([fe80::18f3:313d:3e:42ff]) by\n\trwthex-w2-a.rwth-ad.de ([fe80::18f3:313d:3e:42ff%21]) with mapi id\n\t15.01.1034.026; Sat, 23 Sep 2017 02:00:15 +0200"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:Content-ID:In-Reply-To:\n\tReferences:Message-ID:Date:Subject:To:From:Reply-To:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=FawSDTyou7XhS/sxFuVlGFl8eY+DLS1yGEzgg6C1Bac=;\n\tb=Sby6UwkUFqhQ4F\n\tw+mRZ7+TiHFHfU6B2eYH9GUPIkG2tehCT5cl5aLp/c4pOFqYPi+e3FH3SKbFNrMTCuWhHW9ZVpT+5\n\tyit9/1IJJmNbhwgZtG7wPGNZiEhbmazuW52jk8tL5MXaqsJo0ulrbVoZn6rocRv116zaHEDckr19P\n\tQlrlmLCfVYis9drAW2qRS/JWXaN3RpHcMC7FKXzmyshDzzukepScxEt0n4y5Q66K9jru+MjK7QaiO\n\tYfcAVd3iEyIUalZ84c5I0anIb2Yc1wretBKcyfsjvrnD4o1oU+aHSgGG5b/UHRx8oyBF9hd/4bZj4\n\tXkzLhHRgaIRf8U6LRDtg==;","X-IronPort-AV":"E=Sophos;i=\"5.42,428,1500933600\"; d=\"scan'208\";a=\"14710137\"","From":"=?iso-8859-1?q?Br=FCns=2C_Stefan?= ","To":"Maxime Ripard ","Subject":"Re: [PATCH v2 07/10] dmaengine: sun6i: Retrieve channel count/max\n\trequest from devicetree","Thread-Topic":"[PATCH v2 07/10] dmaengine: sun6i: Retrieve channel count/max\n\trequest from devicetree","Thread-Index":"AQHTMFlrb6IcqOdVukugQ6LTh2jDNqLBe6GA","Date":"Sat, 23 Sep 2017 00:00:15 +0000","Message-ID":"<3154933.I7MMVk5mkV@sbruens-linux>","References":"<20170917031956.28010-1-stefan.bruens@rwth-aachen.de>\n\t<6028407.VKu5LCmQv0@sbruens-linux>\n\t<20170922213027.xpnaut3an5or6edl@flea.home>","In-Reply-To":"<20170922213027.xpnaut3an5or6edl@flea.home>","Accept-Language":"en-US, de-DE","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[78.35.13.203]","Content-ID":"<758DC10755E7CE4DAAECBDDD8174164F@rwth-ad.de>","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170922_170043_655676_353BAF66 ","X-CRM114-Status":"GOOD ( 25.77 )","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [134.130.5.46 listed in list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"devicetree@vger.kernel.org\" ,\n\tVinod Koul ,\n\tAndre Przywara , \n\t\"linux-kernel@vger.kernel.org\" ,\n\tCode Kipper ,\n\t\"linux-sunxi@googlegroups.com\" ,\n\tRob Herring ,\n\t\"dmaengine@vger.kernel.org\" ,\n\tChen-Yu Tsai , \"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Type":"text/plain; charset=\"iso-8859-1\"","Content-Transfer-Encoding":"quoted-printable","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1776162,"web_url":"http://patchwork.ozlabs.org/comment/1776162/","msgid":"<20170927090922.u2hnvgz7yi55sjl3@flea>","list_archive_url":null,"date":"2017-09-27T09:09:22","subject":"Re: [PATCH v2 07/10] dmaengine: sun6i: Retrieve channel count/max\n\trequest from devicetree","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Sat, Sep 23, 2017 at 12:00:15AM +0000, Brüns, Stefan wrote:\n> On Freitag, 22. September 2017 23:30:27 CEST Maxime Ripard wrote:\n> > On Tue, Sep 19, 2017 at 04:17:59PM +0000, Brüns, Stefan wrote:\n> > > On Dienstag, 19. September 2017 16:25:08 CEST Maxime Ripard wrote:\n> > > > On Mon, Sep 18, 2017 at 02:09:43PM +0000, Brüns, Stefan wrote:\n> > > > > On Montag, 18. September 2017 10:18:24 CEST you wrote:\n> > > > > > Hi,\n> > > > > > \n> > > > > > On Sun, Sep 17, 2017 at 05:19:53AM +0200, Stefan Brüns wrote:\n> > > > > > > +\tret = of_property_read_u32(np, \"dma-channels\",\n> > > > > > > &sdc->num_pchans);\n> > > > > > > +\tif (ret && !sdc->num_pchans) {\n> > > > > > > +\t\tdev_err(&pdev->dev, \"Can't get dma-channels.\\n\");\n> > > > > > > +\t\treturn ret;\n> > > > > > > +\t}\n> > > > > > > +\n> > > > > > > +\tif (sdc->num_pchans > DMA_MAX_CHANNELS) {\n> > > > > > > +\t\tdev_err(&pdev->dev, \"Number of dma-channels out of range.\n> \\n\");\n> > > > > > > +\t\treturn -EINVAL;\n> > > > > > > +\t}\n> > > > > > > +\n> > > > > > > +\tret = of_property_read_u32(np, \"dma-requests\",\n> > > > > > > &sdc->max_request);\n> > > > > > > +\tif (ret && !sdc->max_request) {\n> > > > > > > +\t\tdev_info(&pdev->dev, \"Missing dma-requests, using %u.\\n\",\n> > > > > > > +\t\t\t DMA_CHAN_MAX_DRQ);\n> > > > > > > +\t\tsdc->max_request = DMA_CHAN_MAX_DRQ;\n> > > > > > > +\t}\n> > > > > > > +\n> > > > > > > +\tif (sdc->max_request > DMA_CHAN_MAX_DRQ) {\n> > > > > > > +\t\tdev_err(&pdev->dev, \"Value of dma-requests out of range.\\n\");\n> > > > > > > +\t\treturn -EINVAL;\n> > > > > > > +\t}\n> > > > > > \n> > > > > > I'm not really convinced about these two checks. They don't catch\n> > > > > > all\n> > > > > > errors (the range between the actual number of channels / DRQ and\n> > > > > > the\n> > > > > > maximum allowed per the registers), they might increase in the\n> > > > > > future\n> > > > > > too, and if we want to make that check actually working, we would\n> > > > > > have\n> > > > > > to duplicate the number of requests and channels into the driver.\n> > > > > \n> > > > > 1. If these values increase, we have a new register layout and and\n> > > > > need a new compatible anyway.\n> > > > \n> > > > And you want to store a new maximum attached to the compatible? Isn't\n> > > > that exactly the situation you're trying to get away from?\n> > > \n> > > Yes, and no. H3, H5, A64 and R40 have the exact same register layout, but\n> > > different number of channels and ports. They could share a compatible (if\n> > > DMA channels were generalized), and we already have several register\n> > > offsets/ widths (implicitly via the callbacks) attached to the compatible\n> > > (so these don't need generalization via DT).\n> > > \n> > > Now, we could also move everything that is currently attached to the\n> > > compatible, i.e. clock gate register offset, burst widths/lengths etc.\n> > > into\n> > > the devicetree binding, but that would just be too much.\n> > > \n> > > The idea is to find a middle ground here, using common patterns in the\n> > > existing SoCs. The register layout has hardly changed, while the number of\n> > > DMA channels and ports changes all the time. Moving the number of DMA\n> > > channels and ports to the DT is trivial, and a pattern also found in\n> > > other DMA controller drivers.\n> > \n> > I'm sorry, but the code is inconsistent here. You basically have two\n> > variables from one SoC to the other, the number of channels and\n> > requests.\n> > \n> > In one case (channels), it mandates that the property is provided in\n> > the device tree, and doesn't default to anything.\n> > \n> > In the other case (requests), the property is optional and it will\n> > provide a default. All that in 20 lines.\n> \n> The channel number is a hardware property. Using more channels than the \n> hardware provides is a bug. There is no default.\n> \n> The port/request is just some lax property to limit the resource allocation \n> upfront. As long as the bindings of the different IP blocks (SPI, audio, ...) \n> provide the correct port numbers, all required information is available.\n\nUsing an improper request ID or out of bounds will be just as much as\na bug. You will not get your DMA transfer to the proper device you\nwere trying to, the data will not reach the device or memory, your\ndriver will not work => a bug.\n\nIt will not be for the same reasons, you will not overwrite other\nregisters, but the end result is just the same: your transfer will not\nwork.\n\n> > I guess we already reached that middle ground by providing them\n> > through the DT, we just have to make sure we remain consistent.\n> > \n> > > *If* the number of dma channels and ports is ever increased,\n> > > exceeding the current maximum, this would amount to major changes in\n> > > the driver and maybe even warrant a completely new driver.\n> > > \n> > > > > 2. As long as the the limits are adhered to, no other\n> > > > > registers/register\n> > > > > fields are overwritten. As the channel number and port are used to\n> > > > > calculate memory offsets bounds checking is IMHO a good idea.\n> > > > \n> > > > And this is true for many other resources, starting with the one\n> > > > defined in reg. We don't error check every register range, clock\n> > > > index, reset line, interrupt, DMA channel, the memory size, etc. yet\n> > > > you could make the same argument.\n> > > > \n> > > > The DT has to be right, and we have to trust it. Otherwise we can just\n> > > > throw it away.\n> > > \n> > > So your argument here basically is - don't do any checks on DT provided\n> > > values, these are always correct. So, following this argument, not only\n> > > the\n> > > range check, but also the of_property_read return values should be\n> > > ignored, as the DT is correct, thus of_property_read will never return an\n> > > error.\n> > No, my argument is don't do a check if you can catch only half of the\n> > errors, and with no hope of fixing it.\n> > \n> > The functions you mentionned have a 100% error catch rate. This is the\n> > difference.\n> > \n> > > That clearly does not match the implementation of drivers throughout the\n> > > various subsystems for DT properties, which is in general - do all the\n> > > checks that can be done, trust everything you can not verify.\n> > \n> > And my point is that we're falling into the latter here. You cannot\n> > verify it properly.\n> \n> Please check the following line:\n> \n> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/dma/sun6i-dma.c#n951\n> \n> Thats far from 100% - the highest allowed port for each SoC differs between RX \n> and TX, and port allocation is sparse.\n\nBut until your patches, you *could* fix it and reach that 100%.\n\nAnd I guess now we could indeed remove it.\n\nLook, this discussion is going nowhere. I told you what the condition\nfor my Acked-by was already.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"ubAlOXrs\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2BqB1tNQz9tXf\n\tfor ;\n\tWed, 27 Sep 2017 19:09:58 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dx8Lp-00058y-Qp; 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September 2017 11:09:22 CEST Maxime Ripard wrote:\n> On Sat, Sep 23, 2017 at 12:00:15AM +0000, Brüns, Stefan wrote:\n> > On Freitag, 22. September 2017 23:30:27 CEST Maxime Ripard wrote:\n> > > On Tue, Sep 19, 2017 at 04:17:59PM +0000, Brüns, Stefan wrote:\n> > > > On Dienstag, 19. September 2017 16:25:08 CEST Maxime Ripard wrote:\n> > > > > On Mon, Sep 18, 2017 at 02:09:43PM +0000, Brüns, Stefan wrote:\n> > > > > > On Montag, 18. September 2017 10:18:24 CEST you wrote:\n> > > > > > > Hi,\n> > > > > > > \n> > > > > > > On Sun, Sep 17, 2017 at 05:19:53AM +0200, Stefan Brüns wrote:\n> > > > > > > > +\tret = of_property_read_u32(np, \"dma-channels\",\n> > > > > > > > &sdc->num_pchans);\n> > > > > > > > +\tif (ret && !sdc->num_pchans) {\n> > > > > > > > +\t\tdev_err(&pdev->dev, \"Can't get dma-channels.\\n\");\n> > > > > > > > +\t\treturn ret;\n> > > > > > > > +\t}\n> > > > > > > > +\n> > > > > > > > +\tif (sdc->num_pchans > DMA_MAX_CHANNELS) {\n> > > > > > > > +\t\tdev_err(&pdev->dev, \"Number of dma-channels out of range.\n> > \n> > \\n\");\n> > \n> > > > > > > > +\t\treturn -EINVAL;\n> > > > > > > > +\t}\n> > > > > > > > +\n> > > > > > > > +\tret = of_property_read_u32(np, \"dma-requests\",\n> > > > > > > > &sdc->max_request);\n> > > > > > > > +\tif (ret && !sdc->max_request) {\n> > > > > > > > +\t\tdev_info(&pdev->dev, \"Missing dma-requests, using %u.\\n\",\n> > > > > > > > +\t\t\t DMA_CHAN_MAX_DRQ);\n> > > > > > > > +\t\tsdc->max_request = DMA_CHAN_MAX_DRQ;\n> > > > > > > > +\t}\n> > > > > > > > +\n> > > > > > > > +\tif (sdc->max_request > DMA_CHAN_MAX_DRQ) {\n> > > > > > > > +\t\tdev_err(&pdev->dev, \"Value of dma-requests out of\n> > > > > > > > range.\\n\");\n> > > > > > > > +\t\treturn -EINVAL;\n> > > > > > > > +\t}\n> > > > > > > \n> > > > > > > I'm not really convinced about these two checks. They don't\n> > > > > > > catch\n> > > > > > > all\n> > > > > > > errors (the range between the actual number of channels / DRQ\n> > > > > > > and\n> > > > > > > the\n> > > > > > > maximum allowed per the registers), they might increase in the\n> > > > > > > future\n> > > > > > > too, and if we want to make that check actually working, we\n> > > > > > > would\n> > > > > > > have\n> > > > > > > to duplicate the number of requests and channels into the\n> > > > > > > driver.\n> > > > > > \n> > > > > > 1. If these values increase, we have a new register layout and and\n> > > > > > need a new compatible anyway.\n> > > > > \n> > > > > And you want to store a new maximum attached to the compatible?\n> > > > > Isn't\n> > > > > that exactly the situation you're trying to get away from?\n> > > > \n> > > > Yes, and no. H3, H5, A64 and R40 have the exact same register layout,\n> > > > but\n> > > > different number of channels and ports. They could share a compatible\n> > > > (if\n> > > > DMA channels were generalized), and we already have several register\n> > > > offsets/ widths (implicitly via the callbacks) attached to the\n> > > > compatible\n> > > > (so these don't need generalization via DT).\n> > > > \n> > > > Now, we could also move everything that is currently attached to the\n> > > > compatible, i.e. clock gate register offset, burst widths/lengths etc.\n> > > > into\n> > > > the devicetree binding, but that would just be too much.\n> > > > \n> > > > The idea is to find a middle ground here, using common patterns in the\n> > > > existing SoCs. The register layout has hardly changed, while the\n> > > > number of\n> > > > DMA channels and ports changes all the time. Moving the number of DMA\n> > > > channels and ports to the DT is trivial, and a pattern also found in\n> > > > other DMA controller drivers.\n> > > \n> > > I'm sorry, but the code is inconsistent here. You basically have two\n> > > variables from one SoC to the other, the number of channels and\n> > > requests.\n> > > \n> > > In one case (channels), it mandates that the property is provided in\n> > > the device tree, and doesn't default to anything.\n> > > \n> > > In the other case (requests), the property is optional and it will\n> > > provide a default. All that in 20 lines.\n> > \n> > The channel number is a hardware property. Using more channels than the\n> > hardware provides is a bug. There is no default.\n> > \n> > The port/request is just some lax property to limit the resource\n> > allocation\n> > upfront. As long as the bindings of the different IP blocks (SPI, audio,\n> > ...) provide the correct port numbers, all required information is\n> > available.\n> Using an improper request ID or out of bounds will be just as much as\n> a bug. You will not get your DMA transfer to the proper device you\n> were trying to, the data will not reach the device or memory, your\n> driver will not work => a bug.\n> \n> It will not be for the same reasons, you will not overwrite other\n> registers, but the end result is just the same: your transfer will not\n> work.\n\nWriting adjacent registers breaks other users of the DMA controller. \n\"Everytime I play a sound, my MMC breaks\" - oh, what fun.\n\n> > > I guess we already reached that middle ground by providing them\n> > > through the DT, we just have to make sure we remain consistent.\n> > > \n> > > > *If* the number of dma channels and ports is ever increased,\n> > > > exceeding the current maximum, this would amount to major changes in\n> > > > the driver and maybe even warrant a completely new driver.\n> > > > \n> > > > > > 2. As long as the the limits are adhered to, no other\n> > > > > > registers/register\n> > > > > > fields are overwritten. As the channel number and port are used to\n> > > > > > calculate memory offsets bounds checking is IMHO a good idea.\n> > > > > \n> > > > > And this is true for many other resources, starting with the one\n> > > > > defined in reg. We don't error check every register range, clock\n> > > > > index, reset line, interrupt, DMA channel, the memory size, etc. yet\n> > > > > you could make the same argument.\n> > > > > \n> > > > > The DT has to be right, and we have to trust it. Otherwise we can\n> > > > > just\n> > > > > throw it away.\n> > > > \n> > > > So your argument here basically is - don't do any checks on DT\n> > > > provided\n> > > > values, these are always correct. So, following this argument, not\n> > > > only\n> > > > the\n> > > > range check, but also the of_property_read return values should be\n> > > > ignored, as the DT is correct, thus of_property_read will never return\n> > > > an\n> > > > error.\n> > > \n> > > No, my argument is don't do a check if you can catch only half of the\n> > > errors, and with no hope of fixing it.\n> > > \n> > > The functions you mentionned have a 100% error catch rate. This is the\n> > > difference.\n> > > \n> > > > That clearly does not match the implementation of drivers throughout\n> > > > the\n> > > > various subsystems for DT properties, which is in general - do all the\n> > > > checks that can be done, trust everything you can not verify.\n> > > \n> > > And my point is that we're falling into the latter here. You cannot\n> > > verify it properly.\n> > \n> > Please check the following line:\n> > \n> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/dr\n> > ivers/dma/sun6i-dma.c#n951\n> > \n> > Thats far from 100% - the highest allowed port for each SoC differs\n> > between RX and TX, and port allocation is sparse.\n> \n> But until your patches, you *could* fix it and reach that 100%.\n\n1. You had 3 years to do that, but you never cared.\n2. Its still possible to do, just add a property to the devicetree.\n\n> And I guess now we could indeed remove it.\n> \n> Look, this discussion is going nowhere. I told you what the condition\n> for my Acked-by was already.\n\nYeah, and its your power as a so called maintainer to force your opinion on \nanyone crossing your way. Fine, go for it ...\n\nStefan","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"eH+yhXtV\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2YVC3X8Jz9t6C\n\tfor ;\n\tThu, 28 Sep 2017 09:11:30 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dxLU9-0004Hf-S7; Wed, 27 Sep 2017 23:11:21 +0000","from mail-out-1.itc.rwth-aachen.de ([134.130.5.46])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dxLU5-0004G1-L8 for linux-arm-kernel@lists.infradead.org;\n\tWed, 27 Sep 2017 23:11:20 +0000","from rwthex-w2-a.rwth-ad.de ([134.130.26.158])\n\tby mail-in-1.itc.rwth-aachen.de with ESMTP; 28 Sep 2017 01:10:48 +0200","from pebbles.site (77.182.56.60) by rwthex-w2-a.rwth-ad.de\n\t(2002:8682:1a9e::8682:1a9e) with Microsoft SMTP Server\n\t(version=TLS1_2, \n\tcipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1034.26;\n\tThu, 28 Sep 2017 01:10:47 +0200"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:\n\tMessage-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=0RUlhDAniATH+V3QUlJcjobhboF6hovNYy1MguLCgAo=;\n\tb=eH+yhXtVTXArSH\n\tK7TleOIfX6LDpiXGFUI0n4paVGwUou03EOZA3y6s+hYd5S/wN5xCZkeV8mZaOlXFVUZNIgU8JmjyH\n\tr9qWVuL0HYL4cVSUwfqzQ6SNz+QAiMJ66laYY58tqwpcLIsPONudLVegkDja1k/BogSi1ZK2cjsXo\n\tCMyJxFE/xCeqScyIq60bxCGzToae7yDQnOQVZYzwnreB2u8AKJkYybS7r+CqjlQDFKz58EeUnoL7M\n\tZ1l4DrUcUuTXXyC7ER5vhfGpoEXAZdpUc1MnGY4uP6m/E/dUA6gep1x3FmpzUlackAeCLDoee3fB5\n\tWBJpJKOvSClJCQhwmFvw==;","X-IronPort-AV":"E=Sophos;i=\"5.42,446,1500933600\"; d=\"scan'208\";a=\"15557831\"","From":"Stefan Bruens ","To":"Maxime Ripard ","Subject":"Re: [PATCH v2 07/10] dmaengine: sun6i: Retrieve channel count/max\n\trequest from devicetree","Date":"Thu, 28 Sep 2017 01:10:46 +0200","Message-ID":"<9434998.NR9mI8DG1i@pebbles.site>","In-Reply-To":"<20170927090922.u2hnvgz7yi55sjl3@flea>","References":"<20170917031956.28010-1-stefan.bruens@rwth-aachen.de>\n\t<3154933.I7MMVk5mkV@sbruens-linux>\n\t<20170927090922.u2hnvgz7yi55sjl3@flea>","MIME-Version":"1.0","X-Originating-IP":"[77.182.56.60]","X-ClientProxiedBy":"rwthex-s1-a.rwth-ad.de (2002:8682:1a98::8682:1a98) To\n\trwthex-w2-a.rwth-ad.de (2002:8682:1a9e::8682:1a9e)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170927_161118_014132_DA208279 ","X-CRM114-Status":"GOOD ( 35.27 )","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [134.130.5.46 listed in list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"devicetree@vger.kernel.org\" ,\n\tVinod Koul ,\n\tAndre Przywara , \n\t\"linux-kernel@vger.kernel.org\" ,\n\tCode Kipper ,\n\t\"linux-sunxi@googlegroups.com\" ,\n\tRob Herring ,\n\t\"dmaengine@vger.kernel.org\" ,\n\tChen-Yu Tsai , \"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Type":"text/plain; charset=\"iso-8859-1\"","Content-Transfer-Encoding":"quoted-printable","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}}]