[{"id":1770826,"web_url":"http://patchwork.ozlabs.org/comment/1770826/","msgid":"<87o9q7m1uu.fsf@linux.vnet.ibm.com>","list_archive_url":null,"date":"2017-09-19T10:14:49","subject":"Re: [Skiboot] [PATCH v5 0/8] Enable stop4 idle state","submitter":{"id":48041,"url":"http://patchwork.ozlabs.org/api/people/48041/","name":"Stewart Smith","email":"stewart@linux.vnet.ibm.com"},"content":"Akshay Adiga writes:\n> When cpu enters stop4 or deeper state it losses few critical hypervisor\n> sprs. In the POWER9 platform stop-api provides interface for opal to call\n> into low level platform firmware/microcode to configure and setup various\n> actions on wakeup from deep idle state.\n>\n> Some SPRs that have implicit value like HRMOR are directly set from\n> OPAL, while other are left to be configured from Linux using opal\n> calls.\n>\n> p9 stop api is used to restore these hypervisor sprs with\n> correct values. Sprs like HRMOR is configured from skiboot,\n> where as LPCR, HID and MSR are configured by kernel. Kernel\n> uses opal_slw_set_reg() to configure these sprs.\n>\n> Patch 1: p9_stop_api from hostboot code.\n> Patch 2: Add glibc style endianness check in CCAN endian.h\n> Patch 3: Fixes build erros caused due to mixed code and declaration\n> Patch 4: Enable opal_slw_set_reg() for power9\n> Patch 5: Configure HRMOR restore using stop api\n> Patch 6: Allows deeper stop states (like stop4) if homer address is set\n> Patch 7: Fix stop4 related flags that are exposed in device-tree for DD2\n> Patch 8: Add Documentaion for opal_slw_set_reg\n>\n> Changes from v1 :\n> * Added patch6, which adds stop4 to device-tree\n>\n> Changes from v2 :\n> * Updated latest p9_stop_api code base from hostboot\n> * Removed \"code under development\" from commit log for p9_stop_api\n> * added Patch 2 , for a p9_stop_api build fix\n> * Remove stop4 support for power9 DD1, stop1 is the deepest stop\n> state in DD1.\n> * Modify stop4 related flags (for DD2 and further rev's)\n>\n> Changes form v3 :\n> * Added glib style endianess check to ccan.\n> * Added documentation\n> * Added explicit check for power8 in opal_slw_set_reg()\n>\n> Changes from v4 :\n> * Changes in commit message as suggested by Vaidy in Patch 1.\n>\n> Akshay Adiga (8):\n> SLW: Add support for p9_stop_api\n> Add glibc style endianess check in CCAN\n> libpore: Build fix for p9_stop_api\n> SLW: Add opal_slw_set_reg support for power9\n> SLW: Configure self-restore for HRMOR\n> SLW: Allow deep states if homer address is known\n> SLW: Removing timebase related flags for stop4\n> Add Documenation for opal_slw_set_reg\n>\n> ccan/endian/endian.h | 9 +\n> doc/opal-api/opal-slw-set-reg-100.rst | 46 ++\n> hw/slw.c | 116 +++-\n> include/p9_stop_api.H | 163 +++++\n> libpore/Makefile.inc | 2 +-\n> libpore/p9_cpu_reg_restore_instruction.H | 76 +++\n> libpore/p9_hcd_header_defs.H | 152 +++++\n> libpore/p9_hcd_memmap_base.H | 522 +++++++++++++++\n> libpore/p9_stop_api.C | 1028 ++++++++++++++++++++++++++++++\n> libpore/p9_stop_api.H | 163 +++++\n> libpore/p9_stop_data_struct.H | 149 +++++\n> libpore/p9_stop_util.C | 187 ++++++\n> libpore/p9_stop_util.H | 145 +++++\n> 13 files changed, 2729 insertions(+), 29 deletions(-)\n> create mode 100644 doc/opal-api/opal-slw-set-reg-100.rst\n> create mode 100644 include/p9_stop_api.H\n> create mode 100644 libpore/p9_cpu_reg_restore_instruction.H\n> create mode 100644 libpore/p9_hcd_header_defs.H\n> create mode 100644 libpore/p9_hcd_memmap_base.H\n> create mode 100644 libpore/p9_stop_api.C\n> create mode 100644 libpore/p9_stop_api.H\n> create mode 100644 libpore/p9_stop_data_struct.H\n> create mode 100644 libpore/p9_stop_util.C\n> create mode 100644 libpore/p9_stop_util.H\n\nThansk for this, especially adding documentation at the end - that's\n*fantastic* and even closes out\nhttps://github.com/open-power/skiboot/issues/129\n\nMerged to master as of b7f41322c61ea903f298544463d386a8a9cc6de5","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","skiboot@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","skiboot@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxJj36hzxz9s3T\n\tfor ;\n\tTue, 19 Sep 2017 20:17:43 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xxJj35wFXzDqYQ\n\tfor ;\n\tTue, 19 Sep 2017 20:17:43 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xxJdw01S8zDqjB\n\tfor ; Tue, 19 Sep 2017 20:14:59 +1000 (AEST)","from pps.filterd (m0098410.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8JAEBck004167\n\tfor ; Tue, 19 Sep 2017 06:14:57 -0400","from e16.ny.us.ibm.com (e16.ny.us.ibm.com [129.33.205.206])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2d2yywmjpu-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Tue, 19 Sep 2017 06:14:57 -0400","from localhost\n\tby e16.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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