[{"id":1769584,"web_url":"http://patchwork.ozlabs.org/comment/1769584/","msgid":"<445ea236-35e9-8d5a-e580-b2bdcf5f7776@free-electrons.com>","list_archive_url":null,"date":"2017-09-16T09:45:47","subject":"Re: [PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3\n\tthermal sensor","submitter":{"id":69366,"url":"http://patchwork.ozlabs.org/api/people/69366/","name":"Quentin Schulz","email":"quentin.schulz@free-electrons.com"},"content":"Hi Icenowy,\n\nOn 14/09/2017 16:52, Icenowy Zheng wrote:\n> This adds support for the Allwinner H3 thermal sensor.\n> \n> Allwinner H3 has a thermal sensor like the one in A33, but have its\n> registers nearly all re-arranged, sample clock moved to CCU and a pair\n> of bus clock and reset added. It's also the base of newer SoCs' thermal\n> sensors.\n> \n> The thermal sensors on A64 and H5 is like the one on H3, but with of\n> course different formula factors.\n> \n> Signed-off-by: Icenowy Zheng \n> ---\n> Changes in v4:\n> - Splitted out some code refactors.\n> - Code sequence changed back. (The gpadc_data went back to the start of\n> the source file)\n> \n> drivers/iio/adc/sun4i-gpadc-iio.c | 48 +++++++++++++++++++++++++++++++++++++++\n> include/linux/mfd/sun4i-gpadc.h | 27 ++++++++++++++++++++++\n> 2 files changed, 75 insertions(+)\n[...]\n> diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h\n> index 78d31984a222..5c2a12101052 100644\n> --- a/include/linux/mfd/sun4i-gpadc.h\n> +++ b/include/linux/mfd/sun4i-gpadc.h\n[...]\n> +#define SUN8I_H3_GPADC_CTRL2_T_ACQ1(x)\t\t\t((GENMASK(15, 0) * (x)) << 16)\n> +\n\nYou want to replace * by &.\n\n((GENMASK(15, 0) & (x)) << 16)\n\nWould ((GENMASK(31, 16) & ((x) << 16)) make the bits you set even more\nobvious?\n\n> #define SUN4I_GPADC_CTRL3\t\t\t\t0x0c\n> +/*\n> + * This register is named \"Average filter Control Register\" in H3 Datasheet,\n> + * but the register's definition is the same as the old CTRL3 register.\n> + */\n> +#define SUN8I_H3_GPADC_CTRL3\t\t\t\t0x70\n> \n\nI would name it as it is in the documentation:\nSUN8I_H3_THS_FILTER\n\nNo need for comments then.\n\n> #define SUN4I_GPADC_CTRL3_FILTER_EN\t\t\tBIT(2)\n> #define SUN4I_GPADC_CTRL3_FILTER_TYPE(x)\t\t(GENMASK(1, 0) & (x))\n> @@ -71,6 +84,13 @@\n> #define SUN4I_GPADC_INT_FIFOC_TP_UP_IRQ_EN\t\tBIT(1)\n> #define SUN4I_GPADC_INT_FIFOC_TP_DOWN_IRQ_EN\t\tBIT(0)\n> \n> +#define SUN8I_H3_GPADC_INTC\t\t\t\t0x44\n> +\n> +#define SUN8I_H3_GPADC_INTC_TEMP_PERIOD(x)\t\t((GENMASK(19, 0) & (x)) << 12)\n> +#define SUN8I_H3_GPADC_INTC_TEMP_DATA\t\t\tBIT(8)\n> +#define SUN8I_H3_GPADC_INTC_TEMP_SHUT\t\t\tBIT(4)\n> +#define SUN8I_H3_GPADC_INTC_TEMP_ALARM\t\t\tBIT(0)\n> +\n\nSince it isn't an ADC anymore but rather just a THS, why don't you use\nSUN8I_H3_THS instead of SUN8I_H3_GPADC? That way, it also matches the\ndatasheet.\n\n> #define SUN4I_GPADC_INT_FIFOS\t\t\t\t0x14\n> \n> #define SUN4I_GPADC_INT_FIFOS_TEMP_DATA_PENDING\t\tBIT(18)\n> @@ -80,9 +100,16 @@\n> #define SUN4I_GPADC_INT_FIFOS_TP_UP_PENDING\t\tBIT(1)\n> #define SUN4I_GPADC_INT_FIFOS_TP_DOWN_PENDING\t\tBIT(0)\n> \n> +#define SUN8I_H3_GPADC_INTS\t\t\t\t0x44\n\n0x48\n\n[...]\n\n1) You're not using irqs, why would you define registers that will never\nbe used?\n\n2) Why aren't you using irqs? I remember we discussed on IRC that you\nhad some problems with the H3 when resuming or when probing the driver.\nThe register would have a zero in it until you have a first sample that\narrived (i.e. after the sample rate you set with T_ACQ) that would make\nthe thermal framework panic since the thermal sensor would return\nsomething way too hot and shutdown your board?\n\nThe H3 apparently supports IRQs, why do you not support them for the\ntemperature? They might be broken as it is on A33 but then it might be a\ngood idea to write it down in a comment in the driver (and not adding\nthe unused registers in the header file) or at least in the commit log.\n\n3) Now that you have support for clocks, wouldn't it be a good idea to\ndisable them during suspend?\n\nThanks,\nQuentin","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xvS7g63r8z9sPk\n\tfor ;\n\tSat, 16 Sep 2017 19:45:51 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751203AbdIPJpu (ORCPT\n\t);\n\tSat, 16 Sep 2017 05:45:50 -0400","from mail.free-electrons.com ([62.4.15.54]:54904 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751050AbdIPJpt (ORCPT\n\t); Sat, 16 Sep 2017 05:45:49 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 37521209E2; Sat, 16 Sep 2017 11:45:47 +0200 (CEST)","from [192.168.1.14] (LFbn-1-10600-115.w90-89.abo.wanadoo.fr\n\t[90.89.191.115])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id E0BBB20917;\n\tSat, 16 Sep 2017 11:45:46 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT\n\tshortcircuit=ham autolearn=disabled version=3.4.0","Subject":"Re: [PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3\n\tthermal sensor","To":"Icenowy Zheng , Lee Jones ,\n\tRob Herring ,\n\tMaxime Ripard ,\n\tChen-Yu Tsai , Jonathan Cameron ","Cc":"devicetree@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,\n\tlinux-arm-kernel@lists.infradead.org","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-5-icenowy@aosc.io>","From":"Quentin Schulz ","Message-ID":"<445ea236-35e9-8d5a-e580-b2bdcf5f7776@free-electrons.com>","Date":"Sat, 16 Sep 2017 11:45:47 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170914145251.21784-5-icenowy@aosc.io>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1769588,"web_url":"http://patchwork.ozlabs.org/comment/1769588/","msgid":"","list_archive_url":null,"date":"2017-09-16T10:05:49","subject":"Re: [PATCH v4 6/6] ARM: sun8i: h3: add partial CPU thermal zone","submitter":{"id":69366,"url":"http://patchwork.ozlabs.org/api/people/69366/","name":"Quentin Schulz","email":"quentin.schulz@free-electrons.com"},"content":"Hi Icenowy,\n\nOn 14/09/2017 16:52, Icenowy Zheng wrote:\n> Because of the restriction of the OF thermal framework, the thermal\n> sensor will fail to probe if the thermal zone doesn't exist.\n> \n\nOh no, that's not good.\n\nWe discussed about it on IRC and I even proposed a patch for it, telling\nyou I would post it on the mailing list soon after. Of course, I forgot\nand you definitely should have yelled at me for not doing it :)\n\nI won't be able to test the patch soon. I can send it to you so that you\ncan test it and integrate it in your patch series so it won't block you.\nOtherwise, we'll have to wait for a week or two for me to test it.\n\nThanks and sorry for forgetting to post the patch you need,\nQuentin\n\n> Add a partial thermal zone which claims the H3 THS as the thermal sensor.\n> \n> The cooling device (CPU DVFS) is still not added as it's not ready, and\n> the trip points are also not added yet.\n> \n> Signed-off-by: Icenowy Zheng \n> ---\n> arch/arm/boot/dts/sun8i-h3.dtsi | 9 +++++++++\n> 1 file changed, 9 insertions(+)\n> \n> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi\n> index 3220da3ad790..687c6457d214 100644\n> --- a/arch/arm/boot/dts/sun8i-h3.dtsi\n> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi\n> @@ -89,6 +89,15 @@\n> \t\t};\n> \t};\n> \n> +\tthermal-zones {\n> +\t\tcpu-thermal {\n> +\t\t\t/* milliseconds */\n> +\t\t\tpolling-delay-passive = <250>;\n> +\t\t\tpolling-delay = <1000>;\n> +\t\t\tthermal-sensors = <&ths>;\n> +\t\t};\n> +\t};\n> +\n> \ttimer {\n> \t\tcompatible = \"arm,armv7-timer\";\n> \t\tinterrupts = ,\n>","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xvSZs3K6sz9t2l\n\tfor ;\n\tSat, 16 Sep 2017 20:05:57 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751183AbdIPKFw (ORCPT\n\t);\n\tSat, 16 Sep 2017 06:05:52 -0400","from mail.free-electrons.com ([62.4.15.54]:55125 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751161AbdIPKFv (ORCPT\n\t); Sat, 16 Sep 2017 06:05:51 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid AF8BE209E8; Sat, 16 Sep 2017 12:05:49 +0200 (CEST)","from [192.168.1.14] (LFbn-1-10600-115.w90-89.abo.wanadoo.fr\n\t[90.89.191.115])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 67DCA209E0;\n\tSat, 16 Sep 2017 12:05:49 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Subject":"Re: [PATCH v4 6/6] ARM: sun8i: h3: add partial CPU thermal zone","To":"Icenowy Zheng , Lee Jones ,\n\tRob Herring ,\n\tMaxime Ripard ,\n\tChen-Yu Tsai , Jonathan Cameron ","Cc":"devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-7-icenowy@aosc.io>","From":"Quentin Schulz ","Message-ID":"","Date":"Sat, 16 Sep 2017 12:05:49 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170914145251.21784-7-icenowy@aosc.io>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1769592,"web_url":"http://patchwork.ozlabs.org/comment/1769592/","msgid":"<0b395ea1743a14a62855fc2a2dc74411@aosc.io>","list_archive_url":null,"date":"2017-09-16T10:14:08","subject":"Re: [PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3\n\tthermal sensor","submitter":{"id":71295,"url":"http://patchwork.ozlabs.org/api/people/71295/","name":"Icenowy Zheng","email":"icenowy@aosc.io"},"content":"在 2017-09-16 17:45，Quentin Schulz 写道：\n> Hi Icenowy,\n> \n> On 14/09/2017 16:52, Icenowy Zheng wrote:\n>> This adds support for the Allwinner H3 thermal sensor.\n>> \n>> Allwinner H3 has a thermal sensor like the one in A33, but have its\n>> registers nearly all re-arranged, sample clock moved to CCU and a pair\n>> of bus clock and reset added. It's also the base of newer SoCs' \n>> thermal\n>> sensors.\n>> \n>> The thermal sensors on A64 and H5 is like the one on H3, but with of\n>> course different formula factors.\n>> \n>> Signed-off-by: Icenowy Zheng \n>> ---\n>> Changes in v4:\n>> - Splitted out some code refactors.\n>> - Code sequence changed back. (The gpadc_data went back to the start \n>> of\n>> the source file)\n>> \n>> drivers/iio/adc/sun4i-gpadc-iio.c | 48 \n>> +++++++++++++++++++++++++++++++++++++++\n>> include/linux/mfd/sun4i-gpadc.h | 27 ++++++++++++++++++++++\n>> 2 files changed, 75 insertions(+)\n> [...]\n>> diff --git a/include/linux/mfd/sun4i-gpadc.h \n>> b/include/linux/mfd/sun4i-gpadc.h\n>> index 78d31984a222..5c2a12101052 100644\n>> --- a/include/linux/mfd/sun4i-gpadc.h\n>> +++ b/include/linux/mfd/sun4i-gpadc.h\n> [...]\n>> +#define SUN8I_H3_GPADC_CTRL2_T_ACQ1(x)\t\t\t((GENMASK(15, 0) * (x)) << \n>> 16)\n>> +\n> \n> You want to replace * by &.\n> \n> ((GENMASK(15, 0) & (x)) << 16)\n> \n> Would ((GENMASK(31, 16) & ((x) << 16)) make the bits you set even more\n> obvious?\n> \n>> #define SUN4I_GPADC_CTRL3\t\t\t\t0x0c\n>> +/*\n>> + * This register is named \"Average filter Control Register\" in H3 \n>> Datasheet,\n>> + * but the register's definition is the same as the old CTRL3 \n>> register.\n>> + */\n>> +#define SUN8I_H3_GPADC_CTRL3\t\t\t\t0x70\n>> \n> \n> I would name it as it is in the documentation:\n> SUN8I_H3_THS_FILTER\n\nThe definition of this register is the same as the CTRL3.\n\nMaybe this name is better, but the similarity between them still needs\nto be documented, as the SUN4I_GPADC_CTRL3_XXX macros will be used to\npopulate this register.\n\n> \n> No need for comments then.\n> \n>> #define SUN4I_GPADC_CTRL3_FILTER_EN\t\t\tBIT(2)\n>> #define SUN4I_GPADC_CTRL3_FILTER_TYPE(x)\t\t(GENMASK(1, 0) & (x))\n>> @@ -71,6 +84,13 @@\n>> #define SUN4I_GPADC_INT_FIFOC_TP_UP_IRQ_EN\t\tBIT(1)\n>> #define SUN4I_GPADC_INT_FIFOC_TP_DOWN_IRQ_EN\t\tBIT(0)\n>> \n>> +#define SUN8I_H3_GPADC_INTC\t\t\t\t0x44\n>> +\n>> +#define SUN8I_H3_GPADC_INTC_TEMP_PERIOD(x)\t\t((GENMASK(19, 0) & (x)) \n>> << 12)\n>> +#define SUN8I_H3_GPADC_INTC_TEMP_DATA\t\t\tBIT(8)\n>> +#define SUN8I_H3_GPADC_INTC_TEMP_SHUT\t\t\tBIT(4)\n>> +#define SUN8I_H3_GPADC_INTC_TEMP_ALARM\t\t\tBIT(0)\n>> +\n> \n> Since it isn't an ADC anymore but rather just a THS, why don't you use\n> SUN8I_H3_THS instead of SUN8I_H3_GPADC? That way, it also matches the\n> datasheet.\n> \n>> #define SUN4I_GPADC_INT_FIFOS\t\t\t\t0x14\n>> \n>> #define SUN4I_GPADC_INT_FIFOS_TEMP_DATA_PENDING\t\tBIT(18)\n>> @@ -80,9 +100,16 @@\n>> #define SUN4I_GPADC_INT_FIFOS_TP_UP_PENDING\t\tBIT(1)\n>> #define SUN4I_GPADC_INT_FIFOS_TP_DOWN_PENDING\t\tBIT(0)\n>> \n>> +#define SUN8I_H3_GPADC_INTS\t\t\t\t0x44\n> \n> 0x48\n> \n> [...]\n> \n> 1) You're not using irqs, why would you define registers that will \n> never\n> be used?\n\nI will then rework it to use IRQs, but not now.\n\nMaybe I should add it when I use them?\n\n> \n> 2) Why aren't you using irqs? I remember we discussed on IRC that you\n> had some problems with the H3 when resuming or when probing the driver.\n> The register would have a zero in it until you have a first sample that\n> arrived (i.e. after the sample rate you set with T_ACQ) that would make\n> the thermal framework panic since the thermal sensor would return\n> something way too hot and shutdown your board?\n\nNope, it's another problem -- the runtime resume function is even not\ncalled before the first sample, and the first sample will happen when\nthe THS is still suspended.\n\n> \n> The H3 apparently supports IRQs, why do you not support them for the\n> temperature? They might be broken as it is on A33 but then it might be \n> a\n> good idea to write it down in a comment in the driver (and not adding\n> the unused registers in the header file) or at least in the commit log.\n> \n> 3) Now that you have support for clocks, wouldn't it be a good idea to\n> disable them during suspend?\n\nInteresting... It's meaningful to disable the mod clock during suspend.\n\n> \n> Thanks,\n> Quentin\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xvSmP2nftz9t30\n\tfor ;\n\tSat, 16 Sep 2017 20:14:13 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751262AbdIPKOL (ORCPT\n\t);\n\tSat, 16 Sep 2017 06:14:11 -0400","from hermes.aosc.io ([199.195.250.187]:43474 \"EHLO hermes.aosc.io\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751161AbdIPKOK (ORCPT );\n\tSat, 16 Sep 2017 06:14:10 -0400","from localhost (localhost [127.0.0.1]) (Authenticated sender:\n\ticenowy@aosc.io)\n\tby hermes.aosc.io (Postfix) with ESMTPSA id 405014646A;\n\tSat, 16 Sep 2017 10:14:08 +0000 (UTC)"],"MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8;\n format=flowed","Content-Transfer-Encoding":"8bit","Date":"Sat, 16 Sep 2017 18:14:08 +0800","From":"icenowy@aosc.io","To":"Quentin Schulz ","Cc":"Lee Jones , Rob Herring ,\n\tMaxime Ripard ,\n\tChen-Yu Tsai , Jonathan Cameron ,\n\tdevicetree@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,\n\tlinux-arm-kernel@lists.infradead.org","Subject":"Re: [PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3\n\tthermal sensor","In-Reply-To":"<445ea236-35e9-8d5a-e580-b2bdcf5f7776@free-electrons.com>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-5-icenowy@aosc.io>\n\t<445ea236-35e9-8d5a-e580-b2bdcf5f7776@free-electrons.com>","Message-ID":"<0b395ea1743a14a62855fc2a2dc74411@aosc.io>","X-Sender":"icenowy@aosc.io","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1769595,"web_url":"http://patchwork.ozlabs.org/comment/1769595/","msgid":"<486005c0-3954-bd49-d2e1-072661fe31a7@free-electrons.com>","list_archive_url":null,"date":"2017-09-16T10:35:01","subject":"Re: [PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3\n\tthermal sensor","submitter":{"id":69366,"url":"http://patchwork.ozlabs.org/api/people/69366/","name":"Quentin Schulz","email":"quentin.schulz@free-electrons.com"},"content":"Hi Icenowy,\n\nOn 16/09/2017 12:14, icenowy@aosc.io wrote:\n> 在 2017-09-16 17:45，Quentin Schulz 写道：\n>> Hi Icenowy,\n>>\n>> On 14/09/2017 16:52, Icenowy Zheng wrote:\n>>> This adds support for the Allwinner H3 thermal sensor.\n>>>\n>>> Allwinner H3 has a thermal sensor like the one in A33, but have its\n>>> registers nearly all re-arranged, sample clock moved to CCU and a pair\n>>> of bus clock and reset added. It's also the base of newer SoCs' thermal\n>>> sensors.\n>>>\n>>> The thermal sensors on A64 and H5 is like the one on H3, but with of\n>>> course different formula factors.\n>>>\n>>> Signed-off-by: Icenowy Zheng \n>>> ---\n>>> Changes in v4:\n>>> - Splitted out some code refactors.\n>>> - Code sequence changed back. (The gpadc_data went back to the start of\n>>>   the source file)\n>>>\n>>>  drivers/iio/adc/sun4i-gpadc-iio.c | 48\n>>> +++++++++++++++++++++++++++++++++++++++\n>>>  include/linux/mfd/sun4i-gpadc.h   | 27 ++++++++++++++++++++++\n>>>  2 files changed, 75 insertions(+)\n[...]\n>>>  #define SUN4I_GPADC_CTRL3                0x0c\n>>> +/*\n>>> + * This register is named \"Average filter Control Register\" in H3\n>>> Datasheet,\n>>> + * but the register's definition is the same as the old CTRL3 register.\n>>> + */\n>>> +#define SUN8I_H3_GPADC_CTRL3                0x70\n>>>\n>>\n>> I would name it as it is in the documentation:\n>> SUN8I_H3_THS_FILTER\n> \n> The definition of this register is the same as the CTRL3.\n> \n> Maybe this name is better, but the similarity between them still needs\n> to be documented, as the SUN4I_GPADC_CTRL3_XXX macros will be used to\n> populate this register.\n> \n>>\n>> No need for comments then.\n>>\n>>>  #define SUN4I_GPADC_CTRL3_FILTER_EN            BIT(2)\n>>>  #define SUN4I_GPADC_CTRL3_FILTER_TYPE(x)        (GENMASK(1, 0) & (x))\n\nThey have _FILTER_ in their name, isn't it enough?\n\nJust a matter of taste for me.\n\n>>> @@ -71,6 +84,13 @@\n>>>  #define SUN4I_GPADC_INT_FIFOC_TP_UP_IRQ_EN        BIT(1)\n>>>  #define SUN4I_GPADC_INT_FIFOC_TP_DOWN_IRQ_EN        BIT(0)\n>>>\n>>> +#define SUN8I_H3_GPADC_INTC                0x44\n>>> +\n>>> +#define SUN8I_H3_GPADC_INTC_TEMP_PERIOD(x)        ((GENMASK(19, 0) &\n>>> (x)) << 12)\n>>> +#define SUN8I_H3_GPADC_INTC_TEMP_DATA            BIT(8)\n>>> +#define SUN8I_H3_GPADC_INTC_TEMP_SHUT            BIT(4)\n>>> +#define SUN8I_H3_GPADC_INTC_TEMP_ALARM            BIT(0)\n>>> +\n>>\n>> Since it isn't an ADC anymore but rather just a THS, why don't you use\n>> SUN8I_H3_THS instead of SUN8I_H3_GPADC? That way, it also matches the\n>> datasheet.\n>>\n>>>  #define SUN4I_GPADC_INT_FIFOS                0x14\n>>>\n>>>  #define SUN4I_GPADC_INT_FIFOS_TEMP_DATA_PENDING        BIT(18)\n>>> @@ -80,9 +100,16 @@\n>>>  #define SUN4I_GPADC_INT_FIFOS_TP_UP_PENDING        BIT(1)\n>>>  #define SUN4I_GPADC_INT_FIFOS_TP_DOWN_PENDING        BIT(0)\n>>>\n>>> +#define SUN8I_H3_GPADC_INTS                0x44\n>>\n>> 0x48\n>>\n>> [...]\n>>\n>> 1) You're not using irqs, why would you define registers that will never\n>> be used?\n> \n> I will then rework it to use IRQs, but not now.\n> \n> Maybe I should add it when I use them?\n> \n\nWhy not make it work right away the way we want :)?\n\n>>\n>> 2) Why aren't you using irqs? I remember we discussed on IRC that you\n>> had some problems with the H3 when resuming or when probing the driver.\n>> The register would have a zero in it until you have a first sample that\n>> arrived (i.e. after the sample rate you set with T_ACQ) that would make\n>> the thermal framework panic since the thermal sensor would return\n>> something way too hot and shutdown your board?\n> \n> Nope, it's another problem -- the runtime resume function is even not\n> called before the first sample, and the first sample will happen when\n> the THS is still suspended.\n> \n\nAs discussed on IRC (a long time ago :) ), it's a combination of two\nproblems:\n1) get_temp (used by thermal framework) uses pm_runtime function that\nisn't ready yet <= I will send a patch for registering thermal framework\nafter pm_runtime to you, hopefully in the upcoming hour or tomorrow,\n\n2) The A33 (and H3 in your implementation) does not wait for an\ninterrupt to read the TEMP_DATA register which resets to 0 when the\nsensor is disabled (or until a first sample arrives) i.e. when probing\nor when resuming. Using IRQs would get rid of 2). It isn't critical for\nA33 as the formula for temp returns something really cold so thermal\ndoes not care. But for the H3, it's critically hot and shuts down your\nboard. To make it work on the H3, we would have to use a delay in the\npm_resume function equal to the sensor sampling rate and I don't really\nlike that. If we could use IRQs, it'd be better IMHO (but they aren't\nworking on A33).\n\nThanks,\nQuentin\n\n>>\n>> The H3 apparently supports IRQs, why do you not support them for the\n>> temperature? They might be broken as it is on A33 but then it might be a\n>> good idea to write it down in a comment in the driver (and not adding\n>> the unused registers in the header file) or at least in the commit log.\n>>\n>> 3) Now that you have support for clocks, wouldn't it be a good idea to\n>> disable them during suspend?\n> \n> Interesting... It's meaningful to disable the mod clock during suspend.\n> \n>>\n>> Thanks,\n>> Quentin\n> \n> _______________________________________________\n> linux-arm-kernel mailing list\n> linux-arm-kernel@lists.infradead.org\n> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xvTDb3tQXz9t2c\n\tfor ;\n\tSat, 16 Sep 2017 20:35:11 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751198AbdIPKfF (ORCPT\n\t);\n\tSat, 16 Sep 2017 06:35:05 -0400","from mail.free-electrons.com ([62.4.15.54]:55400 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751183AbdIPKfE (ORCPT\n\t); Sat, 16 Sep 2017 06:35:04 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid B0F65209FC; Sat, 16 Sep 2017 12:35:02 +0200 (CEST)","from [192.168.1.14] (LFbn-1-10600-115.w90-89.abo.wanadoo.fr\n\t[90.89.191.115])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 1CE7C209E8;\n\tSat, 16 Sep 2017 12:35:02 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Subject":"Re: [PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3\n\tthermal sensor","To":"icenowy@aosc.io","Cc":"devicetree@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,\n\tChen-Yu Tsai , Rob Herring ,\n\tlinux-arm-kernel@lists.infradead.org,\n\tMaxime Ripard ,\n\tLee Jones , Jonathan Cameron ","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-5-icenowy@aosc.io>\n\t<445ea236-35e9-8d5a-e580-b2bdcf5f7776@free-electrons.com>\n\t<0b395ea1743a14a62855fc2a2dc74411@aosc.io>","From":"Quentin Schulz ","Message-ID":"<486005c0-3954-bd49-d2e1-072661fe31a7@free-electrons.com>","Date":"Sat, 16 Sep 2017 12:35:01 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<0b395ea1743a14a62855fc2a2dc74411@aosc.io>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1769646,"web_url":"http://patchwork.ozlabs.org/comment/1769646/","msgid":"<20170916151628.001dc421@archlinux>","list_archive_url":null,"date":"2017-09-16T22:16:28","subject":"Re: [PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3\n\tthermal sensor","submitter":{"id":10151,"url":"http://patchwork.ozlabs.org/api/people/10151/","name":"Jonathan Cameron","email":"jic23@kernel.org"},"content":"On Sat, 16 Sep 2017 11:45:47 +0200\nQuentin Schulz wrote:\n\n> Hi Icenowy,\n> \n> On 14/09/2017 16:52, Icenowy Zheng wrote:\n> > This adds support for the Allwinner H3 thermal sensor.\n> > \n> > Allwinner H3 has a thermal sensor like the one in A33, but have its\n> > registers nearly all re-arranged, sample clock moved to CCU and a pair\n> > of bus clock and reset added. It's also the base of newer SoCs' thermal\n> > sensors.\n> > \n> > The thermal sensors on A64 and H5 is like the one on H3, but with of\n> > course different formula factors.\n> > \n> > Signed-off-by: Icenowy Zheng \n> > ---\n> > Changes in v4:\n> > - Splitted out some code refactors.\n> > - Code sequence changed back. (The gpadc_data went back to the start of\n> > the source file)\n> > \n> > drivers/iio/adc/sun4i-gpadc-iio.c | 48 +++++++++++++++++++++++++++++++++++++++\n> > include/linux/mfd/sun4i-gpadc.h | 27 ++++++++++++++++++++++\n> > 2 files changed, 75 insertions(+) \n> [...]\n> > diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h\n> > index 78d31984a222..5c2a12101052 100644\n> > --- a/include/linux/mfd/sun4i-gpadc.h\n> > +++ b/include/linux/mfd/sun4i-gpadc.h \n> [...]\n> > +#define SUN8I_H3_GPADC_CTRL2_T_ACQ1(x)\t\t\t((GENMASK(15, 0) * (x)) << 16)\n> > + \n> \n> You want to replace * by &.\n> \n> ((GENMASK(15, 0) & (x)) << 16)\n> \n> Would ((GENMASK(31, 16) & ((x) << 16)) make the bits you set even more\n> obvious?\n\nAgreed. Would act as better 'documentation'.\n\nJonathan\n> \n> > #define SUN4I_GPADC_CTRL3\t\t\t\t0x0c\n> > +/*\n> > + * This register is named \"Average filter Control Register\" in H3 Datasheet,\n> > + * but the register's definition is the same as the old CTRL3 register.\n> > + */\n> > +#define SUN8I_H3_GPADC_CTRL3\t\t\t\t0x70\n> > \n> \n> I would name it as it is in the documentation:\n> SUN8I_H3_THS_FILTER\n> \n> No need for comments then.\n> \n> > #define SUN4I_GPADC_CTRL3_FILTER_EN\t\t\tBIT(2)\n> > #define SUN4I_GPADC_CTRL3_FILTER_TYPE(x)\t\t(GENMASK(1, 0) & (x))\n> > @@ -71,6 +84,13 @@\n> > #define SUN4I_GPADC_INT_FIFOC_TP_UP_IRQ_EN\t\tBIT(1)\n> > #define SUN4I_GPADC_INT_FIFOC_TP_DOWN_IRQ_EN\t\tBIT(0)\n> > \n> > +#define SUN8I_H3_GPADC_INTC\t\t\t\t0x44\n> > +\n> > +#define SUN8I_H3_GPADC_INTC_TEMP_PERIOD(x)\t\t((GENMASK(19, 0) & (x)) << 12)\n> > +#define SUN8I_H3_GPADC_INTC_TEMP_DATA\t\t\tBIT(8)\n> > +#define SUN8I_H3_GPADC_INTC_TEMP_SHUT\t\t\tBIT(4)\n> > +#define SUN8I_H3_GPADC_INTC_TEMP_ALARM\t\t\tBIT(0)\n> > + \n> \n> Since it isn't an ADC anymore but rather just a THS, why don't you use\n> SUN8I_H3_THS instead of SUN8I_H3_GPADC? That way, it also matches the\n> datasheet.\n> \n> > #define SUN4I_GPADC_INT_FIFOS\t\t\t\t0x14\n> > \n> > #define SUN4I_GPADC_INT_FIFOS_TEMP_DATA_PENDING\t\tBIT(18)\n> > @@ -80,9 +100,16 @@\n> > #define SUN4I_GPADC_INT_FIFOS_TP_UP_PENDING\t\tBIT(1)\n> > #define SUN4I_GPADC_INT_FIFOS_TP_DOWN_PENDING\t\tBIT(0)\n> > \n> > +#define SUN8I_H3_GPADC_INTS\t\t\t\t0x44 \n> \n> 0x48\n> \n> [...]\n> \n> 1) You're not using irqs, why would you define registers that will never\n> be used?\n> \n> 2) Why aren't you using irqs? I remember we discussed on IRC that you\n> had some problems with the H3 when resuming or when probing the driver.\n> The register would have a zero in it until you have a first sample that\n> arrived (i.e. after the sample rate you set with T_ACQ) that would make\n> the thermal framework panic since the thermal sensor would return\n> something way too hot and shutdown your board?\n> \n> The H3 apparently supports IRQs, why do you not support them for the\n> temperature? They might be broken as it is on A33 but then it might be a\n> good idea to write it down in a comment in the driver (and not adding\n> the unused registers in the header file) or at least in the commit log.\n> \n> 3) Now that you have support for clocks, wouldn't it be a good idea to\n> disable them during suspend?\n> \n> Thanks,\n> Quentin\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=jic23@kernel.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xvmnv0b5Rz9t2M\n\tfor ;\n\tSun, 17 Sep 2017 08:16:34 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751299AbdIPWQc (ORCPT\n\t);\n\tSat, 16 Sep 2017 18:16:32 -0400","from mail.kernel.org ([198.145.29.99]:33618 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751294AbdIPWQc (ORCPT );\n\tSat, 16 Sep 2017 18:16:32 -0400","from archlinux (unknown [207.243.58.180])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id D41F322A73;\n\tSat, 16 Sep 2017 22:16:30 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org D41F322A73","Date":"Sat, 16 Sep 2017 15:16:28 -0700","From":"Jonathan Cameron ","To":"Quentin Schulz ","Cc":"Icenowy Zheng , Lee Jones ,\n\tRob Herring ,\n\tMaxime Ripard ,\n\tChen-Yu Tsai , devicetree@vger.kernel.org,\n\tlinux-iio@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com, linux-arm-kernel@lists.infradead.org","Subject":"Re: [PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3\n\tthermal sensor","Message-ID":"<20170916151628.001dc421@archlinux>","In-Reply-To":"<445ea236-35e9-8d5a-e580-b2bdcf5f7776@free-electrons.com>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-5-icenowy@aosc.io>\n\t<445ea236-35e9-8d5a-e580-b2bdcf5f7776@free-electrons.com>","X-Mailer":"Claws Mail 3.15.1-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu)","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1769648,"web_url":"http://patchwork.ozlabs.org/comment/1769648/","msgid":"<20170916151734.10968b7a@archlinux>","list_archive_url":null,"date":"2017-09-16T22:17:34","subject":"Re: [PATCH v4 6/6] ARM: sun8i: h3: add partial CPU thermal zone","submitter":{"id":10151,"url":"http://patchwork.ozlabs.org/api/people/10151/","name":"Jonathan Cameron","email":"jic23@kernel.org"},"content":"On Sat, 16 Sep 2017 12:05:49 +0200\nQuentin Schulz wrote:\n\n> Hi Icenowy,\n> \n> On 14/09/2017 16:52, Icenowy Zheng wrote:\n> > Because of the restriction of the OF thermal framework, the thermal\n> > sensor will fail to probe if the thermal zone doesn't exist.\n> > \n> \n> Oh no, that's not good.\n> \n> We discussed about it on IRC and I even proposed a patch for it, telling\n> you I would post it on the mailing list soon after. Of course, I forgot\n> and you definitely should have yelled at me for not doing it :)\n> \n> I won't be able to test the patch soon. I can send it to you so that you\n> can test it and integrate it in your patch series so it won't block you.\n> Otherwise, we'll have to wait for a week or two for me to test it.\n> \n> Thanks and sorry for forgetting to post the patch you need,\n> Quentin\n\nOther this outstanding issue I'm happy with the series, so hopefully\nwith Quentin's patch added we should be good to merge this one.\n\nJonathan\n\n> \n> > Add a partial thermal zone which claims the H3 THS as the thermal sensor.\n> > \n> > The cooling device (CPU DVFS) is still not added as it's not ready, and\n> > the trip points are also not added yet.\n> > \n> > Signed-off-by: Icenowy Zheng \n> > ---\n> > arch/arm/boot/dts/sun8i-h3.dtsi | 9 +++++++++\n> > 1 file changed, 9 insertions(+)\n> > \n> > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi\n> > index 3220da3ad790..687c6457d214 100644\n> > --- a/arch/arm/boot/dts/sun8i-h3.dtsi\n> > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi\n> > @@ -89,6 +89,15 @@\n> > \t\t};\n> > \t};\n> > \n> > +\tthermal-zones {\n> > +\t\tcpu-thermal {\n> > +\t\t\t/* milliseconds */\n> > +\t\t\tpolling-delay-passive = <250>;\n> > +\t\t\tpolling-delay = <1000>;\n> > +\t\t\tthermal-sensors = <&ths>;\n> > +\t\t};\n> > +\t};\n> > +\n> > \ttimer {\n> > \t\tcompatible = \"arm,armv7-timer\";\n> > \t\tinterrupts = ,\n> > \n> \n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=jic23@kernel.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xvmqC1mPGz9t2M\n\tfor ;\n\tSun, 17 Sep 2017 08:17:43 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751299AbdIPWRi (ORCPT\n\t);\n\tSat, 16 Sep 2017 18:17:38 -0400","from mail.kernel.org ([198.145.29.99]:33718 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751294AbdIPWRh (ORCPT );\n\tSat, 16 Sep 2017 18:17:37 -0400","from archlinux (unknown [207.243.58.180])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id E68C922A73;\n\tSat, 16 Sep 2017 22:17:36 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org E68C922A73","Date":"Sat, 16 Sep 2017 15:17:34 -0700","From":"Jonathan Cameron ","To":"Quentin Schulz ","Cc":"Icenowy Zheng , Lee Jones ,\n\tRob Herring ,\n\tMaxime Ripard ,\n\tChen-Yu Tsai , devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tlinux-iio@vger.kernel.org, linux-sunxi@googlegroups.com","Subject":"Re: [PATCH v4 6/6] ARM: sun8i: h3: add partial CPU thermal zone","Message-ID":"<20170916151734.10968b7a@archlinux>","In-Reply-To":"","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-7-icenowy@aosc.io>\n\t","X-Mailer":"Claws Mail 3.15.1-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu)","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1769911,"web_url":"http://patchwork.ozlabs.org/comment/1769911/","msgid":"<20170918073452.2jizidgu4rvqesiq@flea.lan>","list_archive_url":null,"date":"2017-09-18T07:34:52","subject":"Re: [PATCH v4 2/6] iio: adc: sun4i-gpadc-iio: rename A33-specified\n\tregisters to contain A33","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Thu, Sep 14, 2017 at 10:52:47PM +0800, Icenowy Zheng wrote:\n> As the H3 SoC, which is also in sun8i line, has totally different\n> register map for the thermal sensor (a cut down version of GPADC), we\n> should rename A23/A33-specified registers to contain A33, in order to\n> prevent obfuscation with H3 registers. Currently these registers are\n> only prefixed \"SUN8I\", not \"SUN8I_A33\".\n> \n> Add \"_A33\" after \"SUN8I\" on the register names.\n> \n> Signed-off-by: Icenowy Zheng \n> Reviewed-by: Chen-Yu Tsai \n\nAcked-by: Maxime Ripard \n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwd8260jbz9s72\n\tfor ;\n\tMon, 18 Sep 2017 17:35:14 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752344AbdIRHey (ORCPT\n\t);\n\tMon, 18 Sep 2017 03:34:54 -0400","from mail.free-electrons.com ([62.4.15.54]:54270 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751683AbdIRHex (ORCPT\n\t); Mon, 18 Sep 2017 03:34:53 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 11EFB209DF; Mon, 18 Sep 2017 09:34:52 +0200 (CEST)","from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id D813F2094F;\n\tMon, 18 Sep 2017 09:34:51 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Mon, 18 Sep 2017 09:34:52 +0200","From":"Maxime Ripard ","To":"Icenowy Zheng ","Cc":"Lee Jones , Rob Herring ,\n\tChen-Yu Tsai , Jonathan Cameron ,\n\tQuentin Schulz ,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com","Subject":"Re: [PATCH v4 2/6] iio: adc: sun4i-gpadc-iio: rename A33-specified\n\tregisters to contain A33","Message-ID":"<20170918073452.2jizidgu4rvqesiq@flea.lan>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-3-icenowy@aosc.io>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\"; boundary=\"uoz2scjs6reg45vo\"","Content-Disposition":"inline","In-Reply-To":"<20170914145251.21784-3-icenowy@aosc.io>","User-Agent":"NeoMutt/20170714 (1.8.3)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1769913,"web_url":"http://patchwork.ozlabs.org/comment/1769913/","msgid":"<20170918073601.oiqshnhhl7yb6fv2@flea.lan>","list_archive_url":null,"date":"2017-09-18T07:36:01","subject":"Re: [PATCH v4 3/6] iio: adc: sun4i-gpadc-iio: rework code for\n\tsupporting newer THS variants","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Thu, Sep 14, 2017 at 10:52:48PM +0800, Icenowy Zheng wrote:\n> The SoCs after H3 has newer thermal sensor ADCs, which have two clock\n> inputs (bus clock and sampling clock) and a reset. The registers are\n> also re-arranged.\n> \n> This commit reworks the code, adds the process of the clocks and\n> resets, and allows the sampling start/end code and the position of value\n> readout register to be altered.\n> \n> Signed-off-by: Icenowy Zheng \n\nPlease split that into separate commits.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwd9227S3z9ryQ\n\tfor ;\n\tMon, 18 Sep 2017 17:36:06 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751845AbdIRHgE (ORCPT\n\t);\n\tMon, 18 Sep 2017 03:36:04 -0400","from mail.free-electrons.com ([62.4.15.54]:54349 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751683AbdIRHgD (ORCPT\n\t); Mon, 18 Sep 2017 03:36:03 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid C9EEE20A08; Mon, 18 Sep 2017 09:36:01 +0200 (CEST)","from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 9BCC72094F;\n\tMon, 18 Sep 2017 09:36:01 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Mon, 18 Sep 2017 09:36:01 +0200","From":"Maxime Ripard ","To":"Icenowy Zheng ","Cc":"Lee Jones , Rob Herring ,\n\tChen-Yu Tsai , Jonathan Cameron ,\n\tQuentin Schulz ,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com","Subject":"Re: [PATCH v4 3/6] iio: adc: sun4i-gpadc-iio: rework code for\n\tsupporting newer THS variants","Message-ID":"<20170918073601.oiqshnhhl7yb6fv2@flea.lan>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-4-icenowy@aosc.io>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\"; boundary=\"k6i73kubcroskaqa\"","Content-Disposition":"inline","In-Reply-To":"<20170914145251.21784-4-icenowy@aosc.io>","User-Agent":"NeoMutt/20170714 (1.8.3)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1769967,"web_url":"http://patchwork.ozlabs.org/comment/1769967/","msgid":"<20170918082402.fa5mg2ucqouh3ti5@flea.lan>","list_archive_url":null,"date":"2017-09-18T08:24:02","subject":"Re: [PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3\n\tthermal sensor","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Sat, Sep 16, 2017 at 06:14:08PM +0800, icenowy@aosc.io wrote:\n> > The H3 apparently supports IRQs, why do you not support them for the\n> > temperature? They might be broken as it is on A33 but then it might be a\n> > good idea to write it down in a comment in the driver (and not adding\n> > the unused registers in the header file) or at least in the commit log.\n> > \n> > 3) Now that you have support for clocks, wouldn't it be a good idea to\n> > disable them during suspend?\n> \n> Interesting... It's meaningful to disable the mod clock during suspend.\n\nAll clocks, actually. And put the device back into reset.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwfDr063Zz9s7M\n\tfor ;\n\tMon, 18 Sep 2017 18:24:28 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752518AbdIRIYO (ORCPT\n\t);\n\tMon, 18 Sep 2017 04:24:14 -0400","from mail.free-electrons.com ([62.4.15.54]:56776 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752299AbdIRIYN (ORCPT\n\t); Mon, 18 Sep 2017 04:24:13 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 1D34F2081C; Mon, 18 Sep 2017 10:24:12 +0200 (CEST)","from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id E53A3207F6;\n\tMon, 18 Sep 2017 10:24:01 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Mon, 18 Sep 2017 10:24:02 +0200","From":"Maxime Ripard ","To":"icenowy@aosc.io","Cc":"Quentin Schulz ,\n\tLee Jones ,\n\tRob Herring , Chen-Yu Tsai ,\n\tJonathan Cameron ,\n\tdevicetree@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,\n\tlinux-arm-kernel@lists.infradead.org","Subject":"Re: [PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3\n\tthermal sensor","Message-ID":"<20170918082402.fa5mg2ucqouh3ti5@flea.lan>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-5-icenowy@aosc.io>\n\t<445ea236-35e9-8d5a-e580-b2bdcf5f7776@free-electrons.com>\n\t<0b395ea1743a14a62855fc2a2dc74411@aosc.io>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\"; boundary=\"yc6aqu6lsph33767\"","Content-Disposition":"inline","In-Reply-To":"<0b395ea1743a14a62855fc2a2dc74411@aosc.io>","User-Agent":"NeoMutt/20170714 (1.8.3)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1769969,"web_url":"http://patchwork.ozlabs.org/comment/1769969/","msgid":"<20170918082512.ovzwuorvwqjkueqa@flea.lan>","list_archive_url":null,"date":"2017-09-18T08:25:12","subject":"Re: [PATCH v4 5/6] ARM: sun8i: h3: add support for the thermal\n\tsensor in H3","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Thu, Sep 14, 2017 at 10:52:50PM +0800, Icenowy Zheng wrote:\n> As we have gained the support for the thermal sensor in H3, we can now\n> add its device nodes to the device tree.\n> \n> Add them to the H3 device tree.\n> \n> The calibration data of the thermal sensor is still not added, as\n> it's currently not used, and the SID node is not added yet.\n> \n> The H5 thermal sensor has some differences, and will be added furtherly.\n> \n> Signed-off-by: Icenowy Zheng \n> Reviewed-by: Chen-Yu Tsai \n> ---\n> Changes in v4:\n> - Mention calibration data in commit message.\n> Changes in v3:\n> - Clock name changes.\n> - Splited out thermal zone addition.\n> \n> arch/arm/boot/dts/sun8i-h3.dtsi | 17 +++++++++++++++++\n> 1 file changed, 17 insertions(+)\n> \n> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi\n> index b36f9f423c39..3220da3ad790 100644\n> --- a/arch/arm/boot/dts/sun8i-h3.dtsi\n> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi\n> @@ -72,6 +72,23 @@\n> \t\t};\n> \t};\n> \n> +\tiio-hwmon {\n> +\t\tcompatible = \"iio-hwmon\";\n> +\t\tio-channels = <&ths>;\n> +\t};\n> +\n> +\tsoc {\n> +\t\tths: thermal-sensor@1c25000 {\n> +\t\t\tcompatible = \"allwinner,sun8i-h3-ths\";\n> +\t\t\treg = <0x01c25000 0x100>;\n> +\t\t\tclocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;\n> +\t\t\tclock-names = \"bus\", \"mod\";\n> +\t\t\tresets = <&ccu RST_BUS_THS>;\n> +\t\t\t#thermal-sensor-cells = <0>;\n> +\t\t\t#io-channel-cells = <0>;\n\nYou're missing your interrupt.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwfG10bSWz9s7M\n\tfor ;\n\tMon, 18 Sep 2017 18:25:29 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752290AbdIRIZ1 (ORCPT\n\t);\n\tMon, 18 Sep 2017 04:25:27 -0400","from mail.free-electrons.com ([62.4.15.54]:56835 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752315AbdIRIZ0 (ORCPT\n\t); Mon, 18 Sep 2017 04:25:26 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid E73AA20811; Mon, 18 Sep 2017 10:25:24 +0200 (CEST)","from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id B08A420924;\n\tMon, 18 Sep 2017 10:25:12 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Mon, 18 Sep 2017 10:25:12 +0200","From":"Maxime Ripard ","To":"Icenowy Zheng ","Cc":"Lee Jones , Rob Herring ,\n\tChen-Yu Tsai , Jonathan Cameron ,\n\tQuentin Schulz ,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com","Subject":"Re: [PATCH v4 5/6] ARM: sun8i: h3: add support for the thermal\n\tsensor in H3","Message-ID":"<20170918082512.ovzwuorvwqjkueqa@flea.lan>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-6-icenowy@aosc.io>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\"; boundary=\"uppqkaastklkpelm\"","Content-Disposition":"inline","In-Reply-To":"<20170914145251.21784-6-icenowy@aosc.io>","User-Agent":"NeoMutt/20170714 (1.8.3)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1769971,"web_url":"http://patchwork.ozlabs.org/comment/1769971/","msgid":"<20170918082703.riqntqilakzhirc5@flea.lan>","list_archive_url":null,"date":"2017-09-18T08:27:03","subject":"Re: [PATCH v4 6/6] ARM: sun8i: h3: add partial CPU thermal zone","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"Hi Jonathan,\n\nOn Sat, Sep 16, 2017 at 03:17:34PM -0700, Jonathan Cameron wrote:\n> On Sat, 16 Sep 2017 12:05:49 +0200\n> Quentin Schulz wrote:\n> \n> > Hi Icenowy,\n> > \n> > On 14/09/2017 16:52, Icenowy Zheng wrote:\n> > > Because of the restriction of the OF thermal framework, the thermal\n> > > sensor will fail to probe if the thermal zone doesn't exist.\n> > > \n> > \n> > Oh no, that's not good.\n> > \n> > We discussed about it on IRC and I even proposed a patch for it, telling\n> > you I would post it on the mailing list soon after. Of course, I forgot\n> > and you definitely should have yelled at me for not doing it :)\n> > \n> > I won't be able to test the patch soon. I can send it to you so that you\n> > can test it and integrate it in your patch series so it won't block you.\n> > Otherwise, we'll have to wait for a week or two for me to test it.\n> > \n> > Thanks and sorry for forgetting to post the patch you need,\n> > Quentin\n> \n> Other this outstanding issue I'm happy with the series, so hopefully\n> with Quentin's patch added we should be good to merge this one.\n\nWe will at least need a v5.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwfJ53vHhz9rxm\n\tfor ;\n\tMon, 18 Sep 2017 18:27:17 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752324AbdIRI1P (ORCPT\n\t);\n\tMon, 18 Sep 2017 04:27:15 -0400","from mail.free-electrons.com ([62.4.15.54]:56980 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752275AbdIRI1P (ORCPT\n\t); Mon, 18 Sep 2017 04:27:15 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 46BCD20B90; Mon, 18 Sep 2017 10:27:13 +0200 (CEST)","from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 1C11620A5C;\n\tMon, 18 Sep 2017 10:27:03 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Mon, 18 Sep 2017 10:27:03 +0200","From":"Maxime Ripard ","To":"Jonathan Cameron ","Cc":"Quentin Schulz ,\n\tIcenowy Zheng , Lee Jones ,\n\tRob Herring , Chen-Yu Tsai ,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com","Subject":"Re: [PATCH v4 6/6] ARM: sun8i: h3: add partial CPU thermal zone","Message-ID":"<20170918082703.riqntqilakzhirc5@flea.lan>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-7-icenowy@aosc.io>\n\t\n\t<20170916151734.10968b7a@archlinux>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\"; boundary=\"dmmblfkwzntjwbo4\"","Content-Disposition":"inline","In-Reply-To":"<20170916151734.10968b7a@archlinux>","User-Agent":"NeoMutt/20170714 (1.8.3)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1769973,"web_url":"http://patchwork.ozlabs.org/comment/1769973/","msgid":"<20170918082948.2bl5e44tzsufdj7n@dell>","list_archive_url":null,"date":"2017-09-18T08:29:48","subject":"Re: [PATCH v4 2/6] iio: adc: sun4i-gpadc-iio: rename A33-specified\n\tregisters to contain A33","submitter":{"id":12720,"url":"http://patchwork.ozlabs.org/api/people/12720/","name":"Lee Jones","email":"lee.jones@linaro.org"},"content":"On Thu, 14 Sep 2017, Icenowy Zheng wrote:\n\n> As the H3 SoC, which is also in sun8i line, has totally different\n> register map for the thermal sensor (a cut down version of GPADC), we\n> should rename A23/A33-specified registers to contain A33, in order to\n> prevent obfuscation with H3 registers. Currently these registers are\n> only prefixed \"SUN8I\", not \"SUN8I_A33\".\n> \n> Add \"_A33\" after \"SUN8I\" on the register names.\n> \n> Signed-off-by: Icenowy Zheng \n> Reviewed-by: Chen-Yu Tsai \n> ---\n> Changes in v4:\n> - Change A23 to A33, as the driver never supports A23.\n> \n> drivers/iio/adc/sun4i-gpadc-iio.c | 2 +-\n\n> include/linux/mfd/sun4i-gpadc.h | 6 +++---\n\nAcked-by: Lee Jones ","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"CHO/rHWX\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwfM642jdz9rxm\n\tfor ;\n\tMon, 18 Sep 2017 18:29:54 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752004AbdIRI3x (ORCPT\n\t);\n\tMon, 18 Sep 2017 04:29:53 -0400","from mail-wr0-f171.google.com ([209.85.128.171]:47158 \"EHLO\n\tmail-wr0-f171.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751916AbdIRI3w (ORCPT\n\t); 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charset=utf-8","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"<20170914145251.21784-3-icenowy@aosc.io>","User-Agent":"NeoMutt/20170113 (1.7.2)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1774213,"web_url":"http://patchwork.ozlabs.org/comment/1774213/","msgid":"<20170924152304.02551715@archlinux>","list_archive_url":null,"date":"2017-09-24T14:23:04","subject":"Re: [PATCH v4 6/6] ARM: sun8i: h3: add partial CPU thermal zone","submitter":{"id":10151,"url":"http://patchwork.ozlabs.org/api/people/10151/","name":"Jonathan Cameron","email":"jic23@kernel.org"},"content":"On Mon, 18 Sep 2017 10:27:03 +0200\nMaxime Ripard wrote:\n\n> Hi Jonathan,\n> \n> On Sat, Sep 16, 2017 at 03:17:34PM -0700, Jonathan Cameron wrote:\n> > On Sat, 16 Sep 2017 12:05:49 +0200\n> > Quentin Schulz wrote:\n> > \n> > > Hi Icenowy,\n> > > \n> > > On 14/09/2017 16:52, Icenowy Zheng wrote: \n> > > > Because of the restriction of the OF thermal framework, the thermal\n> > > > sensor will fail to probe if the thermal zone doesn't exist.\n> > > > \n> > > \n> > > Oh no, that's not good.\n> > > \n> > > We discussed about it on IRC and I even proposed a patch for it, telling\n> > > you I would post it on the mailing list soon after. Of course, I forgot\n> > > and you definitely should have yelled at me for not doing it :)\n> > > \n> > > I won't be able to test the patch soon. I can send it to you so that you\n> > > can test it and integrate it in your patch series so it won't block you.\n> > > Otherwise, we'll have to wait for a week or two for me to test it.\n> > > \n> > > Thanks and sorry for forgetting to post the patch you need,\n> > > Quentin \n> > \n> > Other this outstanding issue I'm happy with the series, so hopefully\n> > with Quentin's patch added we should be good to merge this one. \n> \n> We will at least need a v5.\n> \n> Maxime\n> \nSure - I can see other issues are coming out of the woodwork!\n\nThanks,\n\nJonathan\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=jic23@kernel.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y0Tw02SBPz9sRV\n\tfor ;\n\tMon, 25 Sep 2017 00:23:12 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752429AbdIXOXK (ORCPT\n\t);\n\tSun, 24 Sep 2017 10:23:10 -0400","from mail.kernel.org ([198.145.29.99]:60656 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1752349AbdIXOXJ (ORCPT );\n\tSun, 24 Sep 2017 10:23:09 -0400","from archlinux (cpc91196-cmbg18-2-0-cust659.5-4.cable.virginm.net\n\t[81.96.234.148])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 16BCB217C3;\n\tSun, 24 Sep 2017 14:23:06 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org 16BCB217C3","Date":"Sun, 24 Sep 2017 15:23:04 +0100","From":"Jonathan Cameron ","To":"Maxime Ripard ","Cc":"Quentin Schulz ,\n\tIcenowy Zheng , Lee Jones ,\n\tRob Herring , Chen-Yu Tsai ,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com","Subject":"Re: [PATCH v4 6/6] ARM: sun8i: h3: add partial CPU thermal zone","Message-ID":"<20170924152304.02551715@archlinux>","In-Reply-To":"<20170918082703.riqntqilakzhirc5@flea.lan>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-7-icenowy@aosc.io>\n\t\n\t<20170916151734.10968b7a@archlinux>\n\t<20170918082703.riqntqilakzhirc5@flea.lan>","X-Mailer":"Claws Mail 3.15.1-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu)","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]