[{"id":1769585,"web_url":"http://patchwork.ozlabs.org/comment/1769585/","msgid":"<445ea236-35e9-8d5a-e580-b2bdcf5f7776@free-electrons.com>","list_archive_url":null,"date":"2017-09-16T09:45:47","subject":"Re: [PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3\n\tthermal sensor","submitter":{"id":69366,"url":"http://patchwork.ozlabs.org/api/people/69366/","name":"Quentin Schulz","email":"quentin.schulz@free-electrons.com"},"content":"Hi Icenowy,\n\nOn 14/09/2017 16:52, Icenowy Zheng wrote:\n> This adds support for the Allwinner H3 thermal sensor.\n> \n> Allwinner H3 has a thermal sensor like the one in A33, but have its\n> registers nearly all re-arranged, sample clock moved to CCU and a pair\n> of bus clock and reset added. It's also the base of newer SoCs' thermal\n> sensors.\n> \n> The thermal sensors on A64 and H5 is like the one on H3, but with of\n> course different formula factors.\n> \n> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n> ---\n> Changes in v4:\n> - Splitted out some code refactors.\n> - Code sequence changed back. (The gpadc_data went back to the start of\n>   the source file)\n> \n>  drivers/iio/adc/sun4i-gpadc-iio.c | 48 +++++++++++++++++++++++++++++++++++++++\n>  include/linux/mfd/sun4i-gpadc.h   | 27 ++++++++++++++++++++++\n>  2 files changed, 75 insertions(+)\n[...]\n> diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h\n> index 78d31984a222..5c2a12101052 100644\n> --- a/include/linux/mfd/sun4i-gpadc.h\n> +++ b/include/linux/mfd/sun4i-gpadc.h\n[...]\n> +#define SUN8I_H3_GPADC_CTRL2_T_ACQ1(x)\t\t\t((GENMASK(15, 0) * (x)) << 16)\n> +\n\nYou want to replace * by &.\n\n((GENMASK(15, 0) & (x)) << 16)\n\nWould ((GENMASK(31, 16) & ((x) << 16)) make the bits you set even more\nobvious?\n\n>  #define SUN4I_GPADC_CTRL3\t\t\t\t0x0c\n> +/*\n> + * This register is named \"Average filter Control Register\" in H3 Datasheet,\n> + * but the register's definition is the same as the old CTRL3 register.\n> + */\n> +#define SUN8I_H3_GPADC_CTRL3\t\t\t\t0x70\n>  \n\nI would name it as it is in the documentation:\nSUN8I_H3_THS_FILTER\n\nNo need for comments then.\n\n>  #define SUN4I_GPADC_CTRL3_FILTER_EN\t\t\tBIT(2)\n>  #define SUN4I_GPADC_CTRL3_FILTER_TYPE(x)\t\t(GENMASK(1, 0) & (x))\n> @@ -71,6 +84,13 @@\n>  #define SUN4I_GPADC_INT_FIFOC_TP_UP_IRQ_EN\t\tBIT(1)\n>  #define SUN4I_GPADC_INT_FIFOC_TP_DOWN_IRQ_EN\t\tBIT(0)\n>  \n> +#define SUN8I_H3_GPADC_INTC\t\t\t\t0x44\n> +\n> +#define SUN8I_H3_GPADC_INTC_TEMP_PERIOD(x)\t\t((GENMASK(19, 0) & (x)) << 12)\n> +#define SUN8I_H3_GPADC_INTC_TEMP_DATA\t\t\tBIT(8)\n> +#define SUN8I_H3_GPADC_INTC_TEMP_SHUT\t\t\tBIT(4)\n> +#define SUN8I_H3_GPADC_INTC_TEMP_ALARM\t\t\tBIT(0)\n> +\n\nSince it isn't an ADC anymore but rather just a THS, why don't you use\nSUN8I_H3_THS instead of SUN8I_H3_GPADC? That way, it also matches the\ndatasheet.\n\n>  #define SUN4I_GPADC_INT_FIFOS\t\t\t\t0x14\n>  \n>  #define SUN4I_GPADC_INT_FIFOS_TEMP_DATA_PENDING\t\tBIT(18)\n> @@ -80,9 +100,16 @@\n>  #define SUN4I_GPADC_INT_FIFOS_TP_UP_PENDING\t\tBIT(1)\n>  #define SUN4I_GPADC_INT_FIFOS_TP_DOWN_PENDING\t\tBIT(0)\n>  \n> +#define SUN8I_H3_GPADC_INTS\t\t\t\t0x44\n\n0x48\n\n[...]\n\n1) You're not using irqs, why would you define registers that will never\nbe used?\n\n2) Why aren't you using irqs? I remember we discussed on IRC that you\nhad some problems with the H3 when resuming or when probing the driver.\nThe register would have a zero in it until you have a first sample that\narrived (i.e. after the sample rate you set with T_ACQ) that would make\nthe thermal framework panic since the thermal sensor would return\nsomething way too hot and shutdown your board?\n\nThe H3 apparently supports IRQs, why do you not support them for the\ntemperature? They might be broken as it is on A33 but then it might be a\ngood idea to write it down in a comment in the driver (and not adding\nthe unused registers in the header file) or at least in the commit log.\n\n3) Now that you have support for clocks, wouldn't it be a good idea to\ndisable them during suspend?\n\nThanks,\nQuentin","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"avRh2tCf\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xvS8F0Hptz9t2c\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tSat, 16 Sep 2017 19:46:21 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dt9g1-0003VR-K0; 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bh=nSlfKsbx4Ghn+1qa+QsfJPbh/O9YL2+ooucLWHmzemY=;\n\tb=avRh2tCfUHK8+s\n\tL7K73+JsyNuilzS77aW6XAccPwGaYUc2ZtW6HSeAc9yz5eTu2+MQ5T6jNQlgKh/nBttPk+Q5/b9V2\n\tkNS6BGqZetucfNIO5DaB6WsXTJMxu638wM5m8blTQ0S0VNJkj5JAIeFwDiVo+i7Ep4SXVgJMy63wb\n\tvf6c+PlKwA44Z8KsVBtfLbRajJ33BDf9vuMfpFvKx+v7dViPhMaukQFPnVm1y36WmHZ1kiSxHlXDM\n\tA56UkOP4synFzdj5kWaPnW02VyTmWHKbdIWpmzXkyC/Q3PEGTu8QnOVqvqpJ2sFS7mqg4WUvcffBn\n\tKmi0AKzL+4x5OLVLRHHw==;","X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT\n\tshortcircuit=ham autolearn=disabled version=3.4.0","Subject":"Re: [PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3\n\tthermal sensor","To":"Icenowy Zheng <icenowy@aosc.io>, Lee Jones <lee.jones@linaro.org>,\n\tRob Herring <robh+dt@kernel.org>,\n\tMaxime Ripard <maxime.ripard@free-electrons.com>,\n\tChen-Yu Tsai <wens@csie.org>, Jonathan Cameron <jic23@kernel.org>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-5-icenowy@aosc.io>","From":"Quentin Schulz <quentin.schulz@free-electrons.com>","Message-ID":"<445ea236-35e9-8d5a-e580-b2bdcf5f7776@free-electrons.com>","Date":"Sat, 16 Sep 2017 11:45:47 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170914145251.21784-5-icenowy@aosc.io>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170916_024613_509169_A922F6A1 ","X-CRM114-Status":"GOOD (  22.85  )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-1.9 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"linux-iio@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1769589,"web_url":"http://patchwork.ozlabs.org/comment/1769589/","msgid":"<b41a80ec-23d5-a614-f6cc-d09c5a459e03@free-electrons.com>","list_archive_url":null,"date":"2017-09-16T10:05:49","subject":"Re: [PATCH v4 6/6] ARM: sun8i: h3: add partial CPU thermal zone","submitter":{"id":69366,"url":"http://patchwork.ozlabs.org/api/people/69366/","name":"Quentin Schulz","email":"quentin.schulz@free-electrons.com"},"content":"Hi Icenowy,\n\nOn 14/09/2017 16:52, Icenowy Zheng wrote:\n> Because of the restriction of the OF thermal framework, the thermal\n> sensor will fail to probe if the thermal zone doesn't exist.\n> \n\nOh no, that's not good.\n\nWe discussed about it on IRC and I even proposed a patch for it, telling\nyou I would post it on the mailing list soon after. Of course, I forgot\nand you definitely should have yelled at me for not doing it :)\n\nI won't be able to test the patch soon. I can send it to you so that you\ncan test it and integrate it in your patch series so it won't block you.\nOtherwise, we'll have to wait for a week or two for me to test it.\n\nThanks and sorry for forgetting to post the patch you need,\nQuentin\n\n> Add a partial thermal zone which claims the H3 THS as the thermal sensor.\n> \n> The cooling device (CPU DVFS) is still not added as it's not ready, and\n> the trip points are also not added yet.\n> \n> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n> ---\n>  arch/arm/boot/dts/sun8i-h3.dtsi | 9 +++++++++\n>  1 file changed, 9 insertions(+)\n> \n> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi\n> index 3220da3ad790..687c6457d214 100644\n> --- a/arch/arm/boot/dts/sun8i-h3.dtsi\n> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi\n> @@ -89,6 +89,15 @@\n>  \t\t};\n>  \t};\n>  \n> +\tthermal-zones {\n> +\t\tcpu-thermal {\n> +\t\t\t/* milliseconds */\n> +\t\t\tpolling-delay-passive = <250>;\n> +\t\t\tpolling-delay = <1000>;\n> +\t\t\tthermal-sensors = <&ths>;\n> +\t\t};\n> +\t};\n> +\n>  \ttimer {\n>  \t\tcompatible = \"arm,armv7-timer\";\n>  \t\tinterrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,\n>","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170914145251.21784-7-icenowy@aosc.io>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170916_030615_682375_476F6D6D ","X-CRM114-Status":"GOOD (  17.71  )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-1.9 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"linux-iio@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1769593,"web_url":"http://patchwork.ozlabs.org/comment/1769593/","msgid":"<0b395ea1743a14a62855fc2a2dc74411@aosc.io>","list_archive_url":null,"date":"2017-09-16T10:14:08","subject":"Re: [PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3\n\tthermal sensor","submitter":{"id":71295,"url":"http://patchwork.ozlabs.org/api/people/71295/","name":"Icenowy Zheng","email":"icenowy@aosc.io"},"content":"在 2017-09-16 17:45，Quentin Schulz 写道：\n> Hi Icenowy,\n> \n> On 14/09/2017 16:52, Icenowy Zheng wrote:\n>> This adds support for the Allwinner H3 thermal sensor.\n>> \n>> Allwinner H3 has a thermal sensor like the one in A33, but have its\n>> registers nearly all re-arranged, sample clock moved to CCU and a pair\n>> of bus clock and reset added. It's also the base of newer SoCs' \n>> thermal\n>> sensors.\n>> \n>> The thermal sensors on A64 and H5 is like the one on H3, but with of\n>> course different formula factors.\n>> \n>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n>> ---\n>> Changes in v4:\n>> - Splitted out some code refactors.\n>> - Code sequence changed back. (The gpadc_data went back to the start \n>> of\n>>   the source file)\n>> \n>>  drivers/iio/adc/sun4i-gpadc-iio.c | 48 \n>> +++++++++++++++++++++++++++++++++++++++\n>>  include/linux/mfd/sun4i-gpadc.h   | 27 ++++++++++++++++++++++\n>>  2 files changed, 75 insertions(+)\n> [...]\n>> diff --git a/include/linux/mfd/sun4i-gpadc.h \n>> b/include/linux/mfd/sun4i-gpadc.h\n>> index 78d31984a222..5c2a12101052 100644\n>> --- a/include/linux/mfd/sun4i-gpadc.h\n>> +++ b/include/linux/mfd/sun4i-gpadc.h\n> [...]\n>> +#define SUN8I_H3_GPADC_CTRL2_T_ACQ1(x)\t\t\t((GENMASK(15, 0) * (x)) << \n>> 16)\n>> +\n> \n> You want to replace * by &.\n> \n> ((GENMASK(15, 0) & (x)) << 16)\n> \n> Would ((GENMASK(31, 16) & ((x) << 16)) make the bits you set even more\n> obvious?\n> \n>>  #define SUN4I_GPADC_CTRL3\t\t\t\t0x0c\n>> +/*\n>> + * This register is named \"Average filter Control Register\" in H3 \n>> Datasheet,\n>> + * but the register's definition is the same as the old CTRL3 \n>> register.\n>> + */\n>> +#define SUN8I_H3_GPADC_CTRL3\t\t\t\t0x70\n>> \n> \n> I would name it as it is in the documentation:\n> SUN8I_H3_THS_FILTER\n\nThe definition of this register is the same as the CTRL3.\n\nMaybe this name is better, but the similarity between them still needs\nto be documented, as the SUN4I_GPADC_CTRL3_XXX macros will be used to\npopulate this register.\n\n> \n> No need for comments then.\n> \n>>  #define SUN4I_GPADC_CTRL3_FILTER_EN\t\t\tBIT(2)\n>>  #define SUN4I_GPADC_CTRL3_FILTER_TYPE(x)\t\t(GENMASK(1, 0) & (x))\n>> @@ -71,6 +84,13 @@\n>>  #define SUN4I_GPADC_INT_FIFOC_TP_UP_IRQ_EN\t\tBIT(1)\n>>  #define SUN4I_GPADC_INT_FIFOC_TP_DOWN_IRQ_EN\t\tBIT(0)\n>> \n>> +#define SUN8I_H3_GPADC_INTC\t\t\t\t0x44\n>> +\n>> +#define SUN8I_H3_GPADC_INTC_TEMP_PERIOD(x)\t\t((GENMASK(19, 0) & (x)) \n>> << 12)\n>> +#define SUN8I_H3_GPADC_INTC_TEMP_DATA\t\t\tBIT(8)\n>> +#define SUN8I_H3_GPADC_INTC_TEMP_SHUT\t\t\tBIT(4)\n>> +#define SUN8I_H3_GPADC_INTC_TEMP_ALARM\t\t\tBIT(0)\n>> +\n> \n> Since it isn't an ADC anymore but rather just a THS, why don't you use\n> SUN8I_H3_THS instead of SUN8I_H3_GPADC? That way, it also matches the\n> datasheet.\n> \n>>  #define SUN4I_GPADC_INT_FIFOS\t\t\t\t0x14\n>> \n>>  #define SUN4I_GPADC_INT_FIFOS_TEMP_DATA_PENDING\t\tBIT(18)\n>> @@ -80,9 +100,16 @@\n>>  #define SUN4I_GPADC_INT_FIFOS_TP_UP_PENDING\t\tBIT(1)\n>>  #define SUN4I_GPADC_INT_FIFOS_TP_DOWN_PENDING\t\tBIT(0)\n>> \n>> +#define SUN8I_H3_GPADC_INTS\t\t\t\t0x44\n> \n> 0x48\n> \n> [...]\n> \n> 1) You're not using irqs, why would you define registers that will \n> never\n> be used?\n\nI will then rework it to use IRQs, but not now.\n\nMaybe I should add it when I use them?\n\n> \n> 2) Why aren't you using irqs? I remember we discussed on IRC that you\n> had some problems with the H3 when resuming or when probing the driver.\n> The register would have a zero in it until you have a first sample that\n> arrived (i.e. after the sample rate you set with T_ACQ) that would make\n> the thermal framework panic since the thermal sensor would return\n> something way too hot and shutdown your board?\n\nNope, it's another problem -- the runtime resume function is even not\ncalled before the first sample, and the first sample will happen when\nthe THS is still suspended.\n\n> \n> The H3 apparently supports IRQs, why do you not support them for the\n> temperature? They might be broken as it is on A33 but then it might be \n> a\n> good idea to write it down in a comment in the driver (and not adding\n> the unused registers in the header file) or at least in the commit log.\n> \n> 3) Now that you have support for clocks, wouldn't it be a good idea to\n> disable them during suspend?\n\nInteresting... It's meaningful to disable the mod clock during suspend.\n\n> \n> Thanks,\n> Quentin","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"UfOHangI\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xvSmy3xl4z9t2l\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tSat, 16 Sep 2017 20:14:42 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dtA7T-0007h8-Bj; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type:\n\tContent-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive:\n\tList-Unsubscribe:List-Id:Message-ID:References:In-Reply-To:Subject:To:From:\n\tDate:MIME-Version:Reply-To:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;\n\tbh=Kx3IO2oGKmxqfYCsFVFAQKgpvCr/aZ9cylNd419dlIA=;\n\tb=UfOHangIDqNYvKGPUC2SBNkSi\n\tUg3qmaG74K/ERYBkJj9MQuz1itidNDHgojPb43o7bsudzMGfkl4NV8qrP4vYHD3BCFpoEiJYw75Mg\n\tLfHWX4SQLSZpG6XMIqfEkhJJQwOwLgpbPoCpPlfIPYBl/A4GrCvq3BkIzh+TfQu8BKEcg3/4noVpO\n\tV46GuJc4I6GgMre09uaYwk5oZnXtSCp76vZzRb5KhyMYKTXWZxK8q55xmNJPjeihoWi2O+5+2j2Hg\n\tolYKYJaHEYL/y9ACAMuRwUvg56IXSoHYACNvbt1maQMh6SSEDUOwm01mtvOu8TVHuxJ+1F6PuikK3\n\tGrhRogV0Q==;","X-Sender-Id":["lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io","lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io"],"X-MC-Relay":"Neutral","X-MailChannels-SenderId":"lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io","X-MailChannels-Auth-Id":"lmn-TZDUIOWCRQMW","X-Attack-Shelf":"49c3b4f4033a25db_1505556851709_535831261","X-MC-Loop-Signature":"1505556851709:709954192","X-MC-Ingress-Time":"1505556851708","MIME-Version":"1.0","Date":"Sat, 16 Sep 2017 18:14:08 +0800","From":"icenowy@aosc.io","To":"Quentin Schulz <quentin.schulz@free-electrons.com>","Subject":"Re: [PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3\n\tthermal sensor","In-Reply-To":"<445ea236-35e9-8d5a-e580-b2bdcf5f7776@free-electrons.com>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-5-icenowy@aosc.io>\n\t<445ea236-35e9-8d5a-e580-b2bdcf5f7776@free-electrons.com>","Message-ID":"<0b395ea1743a14a62855fc2a2dc74411@aosc.io>","X-Sender":"icenowy@aosc.io","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170916_031434_590749_8A31DA07 ","X-CRM114-Status":"GOOD (  23.03  )","X-Spam-Score":"-4.7 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-4.7 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [23.83.209.53 listed in list.dnswl.org]\n\t-2.8 RCVD_IN_MSPIKE_H2      RBL: Average reputation (+2)\n\t[23.83.209.53 listed in wl.mailspike.net]\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"devicetree@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,\n\tChen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>,\n\tlinux-arm-kernel@lists.infradead.org,\n\tMaxime Ripard <maxime.ripard@free-electrons.com>,\n\tLee Jones <lee.jones@linaro.org>, Jonathan Cameron <jic23@kernel.org>","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=\"utf-8\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1769596,"web_url":"http://patchwork.ozlabs.org/comment/1769596/","msgid":"<486005c0-3954-bd49-d2e1-072661fe31a7@free-electrons.com>","list_archive_url":null,"date":"2017-09-16T10:35:01","subject":"Re: [PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3\n\tthermal sensor","submitter":{"id":69366,"url":"http://patchwork.ozlabs.org/api/people/69366/","name":"Quentin Schulz","email":"quentin.schulz@free-electrons.com"},"content":"Hi Icenowy,\n\nOn 16/09/2017 12:14, icenowy@aosc.io wrote:\n> 在 2017-09-16 17:45，Quentin Schulz 写道：\n>> Hi Icenowy,\n>>\n>> On 14/09/2017 16:52, Icenowy Zheng wrote:\n>>> This adds support for the Allwinner H3 thermal sensor.\n>>>\n>>> Allwinner H3 has a thermal sensor like the one in A33, but have its\n>>> registers nearly all re-arranged, sample clock moved to CCU and a pair\n>>> of bus clock and reset added. It's also the base of newer SoCs' thermal\n>>> sensors.\n>>>\n>>> The thermal sensors on A64 and H5 is like the one on H3, but with of\n>>> course different formula factors.\n>>>\n>>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n>>> ---\n>>> Changes in v4:\n>>> - Splitted out some code refactors.\n>>> - Code sequence changed back. (The gpadc_data went back to the start of\n>>>   the source file)\n>>>\n>>>  drivers/iio/adc/sun4i-gpadc-iio.c | 48\n>>> +++++++++++++++++++++++++++++++++++++++\n>>>  include/linux/mfd/sun4i-gpadc.h   | 27 ++++++++++++++++++++++\n>>>  2 files changed, 75 insertions(+)\n[...]\n>>>  #define SUN4I_GPADC_CTRL3                0x0c\n>>> +/*\n>>> + * This register is named \"Average filter Control Register\" in H3\n>>> Datasheet,\n>>> + * but the register's definition is the same as the old CTRL3 register.\n>>> + */\n>>> +#define SUN8I_H3_GPADC_CTRL3                0x70\n>>>\n>>\n>> I would name it as it is in the documentation:\n>> SUN8I_H3_THS_FILTER\n> \n> The definition of this register is the same as the CTRL3.\n> \n> Maybe this name is better, but the similarity between them still needs\n> to be documented, as the SUN4I_GPADC_CTRL3_XXX macros will be used to\n> populate this register.\n> \n>>\n>> No need for comments then.\n>>\n>>>  #define SUN4I_GPADC_CTRL3_FILTER_EN            BIT(2)\n>>>  #define SUN4I_GPADC_CTRL3_FILTER_TYPE(x)        (GENMASK(1, 0) & (x))\n\nThey have _FILTER_ in their name, isn't it enough?\n\nJust a matter of taste for me.\n\n>>> @@ -71,6 +84,13 @@\n>>>  #define SUN4I_GPADC_INT_FIFOC_TP_UP_IRQ_EN        BIT(1)\n>>>  #define SUN4I_GPADC_INT_FIFOC_TP_DOWN_IRQ_EN        BIT(0)\n>>>\n>>> +#define SUN8I_H3_GPADC_INTC                0x44\n>>> +\n>>> +#define SUN8I_H3_GPADC_INTC_TEMP_PERIOD(x)        ((GENMASK(19, 0) &\n>>> (x)) << 12)\n>>> +#define SUN8I_H3_GPADC_INTC_TEMP_DATA            BIT(8)\n>>> +#define SUN8I_H3_GPADC_INTC_TEMP_SHUT            BIT(4)\n>>> +#define SUN8I_H3_GPADC_INTC_TEMP_ALARM            BIT(0)\n>>> +\n>>\n>> Since it isn't an ADC anymore but rather just a THS, why don't you use\n>> SUN8I_H3_THS instead of SUN8I_H3_GPADC? That way, it also matches the\n>> datasheet.\n>>\n>>>  #define SUN4I_GPADC_INT_FIFOS                0x14\n>>>\n>>>  #define SUN4I_GPADC_INT_FIFOS_TEMP_DATA_PENDING        BIT(18)\n>>> @@ -80,9 +100,16 @@\n>>>  #define SUN4I_GPADC_INT_FIFOS_TP_UP_PENDING        BIT(1)\n>>>  #define SUN4I_GPADC_INT_FIFOS_TP_DOWN_PENDING        BIT(0)\n>>>\n>>> +#define SUN8I_H3_GPADC_INTS                0x44\n>>\n>> 0x48\n>>\n>> [...]\n>>\n>> 1) You're not using irqs, why would you define registers that will never\n>> be used?\n> \n> I will then rework it to use IRQs, but not now.\n> \n> Maybe I should add it when I use them?\n> \n\nWhy not make it work right away the way we want :)?\n\n>>\n>> 2) Why aren't you using irqs? I remember we discussed on IRC that you\n>> had some problems with the H3 when resuming or when probing the driver.\n>> The register would have a zero in it until you have a first sample that\n>> arrived (i.e. after the sample rate you set with T_ACQ) that would make\n>> the thermal framework panic since the thermal sensor would return\n>> something way too hot and shutdown your board?\n> \n> Nope, it's another problem -- the runtime resume function is even not\n> called before the first sample, and the first sample will happen when\n> the THS is still suspended.\n> \n\nAs discussed on IRC (a long time ago :) ), it's a combination of two\nproblems:\n1) get_temp (used by thermal framework) uses pm_runtime function that\nisn't ready yet <= I will send a patch for registering thermal framework\nafter pm_runtime to you, hopefully in the upcoming hour or tomorrow,\n\n2) The A33 (and H3 in your implementation) does not wait for an\ninterrupt to read the TEMP_DATA register which resets to 0 when the\nsensor is disabled (or until a first sample arrives) i.e. when probing\nor when resuming. Using IRQs would get rid of 2). It isn't critical for\nA33 as the formula for temp returns something really cold so thermal\ndoes not care. But for the H3, it's critically hot and shuts down your\nboard. To make it work on the H3, we would have to use a delay in the\npm_resume function equal to the sensor sampling rate and I don't really\nlike that. If we could use IRQs, it'd be better IMHO (but they aren't\nworking on A33).\n\nThanks,\nQuentin\n\n>>\n>> The H3 apparently supports IRQs, why do you not support them for the\n>> temperature? They might be broken as it is on A33 but then it might be a\n>> good idea to write it down in a comment in the driver (and not adding\n>> the unused registers in the header file) or at least in the commit log.\n>>\n>> 3) Now that you have support for clocks, wouldn't it be a good idea to\n>> disable them during suspend?\n> \n> Interesting... It's meaningful to disable the mod clock during suspend.\n> \n>>\n>> Thanks,\n>> Quentin\n> \n> _______________________________________________\n> linux-arm-kernel mailing list\n> linux-arm-kernel@lists.infradead.org\n> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"WiIAouQ/\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xvTF14k3Jz9t30\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tSat, 16 Sep 2017 20:35:33 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dtARd-0002E3-Er; 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bh=MdiU9QvSTrdfSwzE9xSVyBoWuYg+Ujl5spNHxAJcvUA=;\n\tb=WiIAouQ/8akSUy\n\toR6rsAO2cKd92+SQ7cf+iYcn0GJ6bs27SIzIx8OtPcD675mM0htHcjaIUfi74+HPICmp85BwKwVjZ\n\tAaPV8dfCvYBQ3qFQd7EwV6wPxkIbaw0SnDzZxTV3hxDKEW4wLejAXIrZdpSQ5vqmo/wQFnPA2HT8o\n\tflGS9elu1ztqJpkL9OqBnikS265XV2N5bgSoeNOph3Oj4o/njnG38IEGmzRBSGF9CWcwHVcXAZ2QE\n\tjbfz3VCs7nSrpKA/W2Tq14zsKr/A9H7q6fcHVV2PKx7Dox0J/4bhxI7ojuckj9OkloEOlBExVWYW6\n\thL9B5wltz+rEL9OGSGjw==;","X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Subject":"Re: [PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3\n\tthermal sensor","To":"icenowy@aosc.io","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-5-icenowy@aosc.io>\n\t<445ea236-35e9-8d5a-e580-b2bdcf5f7776@free-electrons.com>\n\t<0b395ea1743a14a62855fc2a2dc74411@aosc.io>","From":"Quentin Schulz <quentin.schulz@free-electrons.com>","Message-ID":"<486005c0-3954-bd49-d2e1-072661fe31a7@free-electrons.com>","Date":"Sat, 16 Sep 2017 12:35:01 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<0b395ea1743a14a62855fc2a2dc74411@aosc.io>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170916_033524_880938_D0375546 ","X-CRM114-Status":"GOOD (  31.57  )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-1.9 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"devicetree@vger.kernel.org, linux-iio@vger.kernel.org,\n\tChen-Yu Tsai <wens@csie.org>, linux-kernel@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com, Rob Herring <robh+dt@kernel.org>,\n\tJonathan Cameron <jic23@kernel.org>,\n\tMaxime Ripard <maxime.ripard@free-electrons.com>,\n\tLee Jones <lee.jones@linaro.org>, linux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1769645,"web_url":"http://patchwork.ozlabs.org/comment/1769645/","msgid":"<20170916151224.777e5b56@archlinux>","list_archive_url":null,"date":"2017-09-16T22:12:24","subject":"Re: [PATCH v4 1/6] dt-bindings: update the Allwinner GPADC device\n\ttree binding for H3","submitter":{"id":10151,"url":"http://patchwork.ozlabs.org/api/people/10151/","name":"Jonathan Cameron","email":"jic23@kernel.org"},"content":"On Thu, 14 Sep 2017 22:52:46 +0800\nIcenowy Zheng <icenowy@aosc.io> wrote:\n\n> Allwinner H3 features a thermal sensor like the one in A33, but has its\n> register re-arranged, the clock divider moved to CCU (originally the\n> clock divider is in ADC) and added a pair of bus clock and reset.\n> \n> Update the binding document to cover H3.\n> \n> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n> Reviewed-by: Chen-Yu Tsai <wens@csie.org>\n> ---\n> Changes in v4:\n> - Add nvmem calibration data (not yet used by the driver)\n> Changes in v3:\n> - Clock name changes.\n> - Example node name changes.\n> - Add interupts (not yet used by the driver).\n> \n>  .../devicetree/bindings/mfd/sun4i-gpadc.txt        | 30 ++++++++++++++++++++--\n>  1 file changed, 28 insertions(+), 2 deletions(-)\n> \n> diff --git a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n> index badff3611a98..6c470d584bf9 100644\n> --- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n> +++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n> @@ -4,12 +4,26 @@ The Allwinner SoCs all have an ADC that can also act as a thermal sensor\n>  and sometimes as a touchscreen controller.\n>  \n>  Required properties:\n> -  - compatible: \"allwinner,sun8i-a33-ths\",\n> +  - compatible: must contain one of the following compatibles:\n> +\t\t- \"allwinner,sun8i-a33-ths\"\n> +\t\t- \"allwinner,sun8i-h3-ths\"\n>    - reg: mmio address range of the chip,\n>    - #thermal-sensor-cells: shall be 0,\n>    - #io-channel-cells: shall be 0,\n>  \n> -Example:\n> +Optional properties:\n> +  - nvmem-cells: A phandle to the calibration data provided by a nvmem device.\n> +                 If unspecified default values shall be used.\n> +  - nvmem-cell-names: Should be \"calibration-data\"\n\nI think a cross reference to the nvmem binding docs would be good here.\nIt wasn't something I could remember coming across before.  Obviously\ngrep gets you there quickly enough, but a cross reference would be even\nbetter.\n\nAlso would it make sense to have an example with these in?\n\nJonathan\n> +\n> +Required properties for the following compatibles:\n> +\t\t- \"allwinner,sun8i-h3-ths\"\n> +  - clocks: the bus clock and the input clock of the ADC,\n> +  - clock-names: should be \"bus\" and \"mod\",\n> +  - resets: the bus reset of the ADC,\n> +  - interrupts: the sampling interrupt of the ADC,\n> +\n> +Example for A33:\n>  \tths: ths@01c25000 {\n>  \t\tcompatible = \"allwinner,sun8i-a33-ths\";\n>  \t\treg = <0x01c25000 0x100>;\n> @@ -17,6 +31,18 @@ Example:\n>  \t\t#io-channel-cells = <0>;\n>  \t};\n>  \n> +Example for H3:\n> +\tths: thermal-sensor@1c25000 {\n> +\t\tcompatible = \"allwinner,sun8i-h3-ths\";\n> +\t\treg = <0x01c25000 0x400>;\n> +\t\tclocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;\n> +\t\tclock-names = \"bus\", \"mod\";\n> +\t\tresets = <&ccu RST_BUS_THS>;\n> +\t\tinterrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;\n> +\t\t#thermal-sensor-cells = <0>;\n> +\t\t#io-channel-cells = <0>;\n> +\t};\n> +\n>  sun4i, sun5i and sun6i SoCs are also supported via the older binding:\n>  \n>  sun4i resistive touchscreen controller","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"gJ2tJ03p\"; dkim-atps=neutral","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=jic23@kernel.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xvmk62kPsz9sRm\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tSun, 17 Sep 2017 08:13:18 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dtLKs-0007og-Ct; Sat, 16 Sep 2017 22:13:14 +0000","from mail.kernel.org ([198.145.29.99])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dtLKU-0007gU-6R for linux-arm-kernel@lists.infradead.org;\n\tSat, 16 Sep 2017 22:13:11 +0000","from archlinux (unknown [207.243.58.180])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 1716622A73;\n\tSat, 16 Sep 2017 22:12:27 +0000 (UTC)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=R0Cjj111yacvxzQqUyvAI0JHqKwV7fLflP9lm9EiIf8=;\n\tb=gJ2tJ03pSG4wxC\n\t7/csI9aJt4MGeDVzNq54lTsbQ5cFxldVpLa32OF1BWuw8gH/c98ulOYl6wTgmqfbZkAXe/rcGOadQ\n\tM4wbYKQ9o4+2O4jfYahkd69mNxRScKi2rfLydFbT/korPPQVJG9iCR5JvBpf1n6hFgYx0eIt4fvep\n\tTC2nbPjF/2pEvmR6deEXaZadiSn37uO8aqnwXvokZMBlP+y3TbnR6+Up5aBLHv76VpvxxEOCt92PO\n\tSEvktPVtwa6ADFsq2X05rNVhEMsYY0naWGNaQZN1BFNLax7FfcJbs3hCFIB1u3XUtsYSFtsg8rTRN\n\tuQQhVjYgLheAwxXjRdaw==;","DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org 1716622A73","Date":"Sat, 16 Sep 2017 15:12:24 -0700","From":"Jonathan Cameron <jic23@kernel.org>","To":"Icenowy Zheng <icenowy@aosc.io>","Subject":"Re: [PATCH v4 1/6] dt-bindings: update the Allwinner GPADC device\n\ttree binding for H3","Message-ID":"<20170916151224.777e5b56@archlinux>","In-Reply-To":"<20170914145251.21784-2-icenowy@aosc.io>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-2-icenowy@aosc.io>","X-Mailer":"Claws Mail 3.15.1-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu)","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170916_151309_634103_D5E8B6FF ","X-CRM114-Status":"GOOD (  18.07  )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-6.9 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [198.145.29.99 listed in list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"devicetree@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,\n\tQuentin Schulz <quentin.schulz@free-electrons.com>,\n\tChen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>,\n\tMaxime Ripard <maxime.ripard@free-electrons.com>,\n\tLee Jones <lee.jones@linaro.org>, linux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1769647,"web_url":"http://patchwork.ozlabs.org/comment/1769647/","msgid":"<20170916151628.001dc421@archlinux>","list_archive_url":null,"date":"2017-09-16T22:16:28","subject":"Re: [PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3\n\tthermal sensor","submitter":{"id":10151,"url":"http://patchwork.ozlabs.org/api/people/10151/","name":"Jonathan Cameron","email":"jic23@kernel.org"},"content":"On Sat, 16 Sep 2017 11:45:47 +0200\nQuentin Schulz <quentin.schulz@free-electrons.com> wrote:\n\n> Hi Icenowy,\n> \n> On 14/09/2017 16:52, Icenowy Zheng wrote:\n> > This adds support for the Allwinner H3 thermal sensor.\n> > \n> > Allwinner H3 has a thermal sensor like the one in A33, but have its\n> > registers nearly all re-arranged, sample clock moved to CCU and a pair\n> > of bus clock and reset added. It's also the base of newer SoCs' thermal\n> > sensors.\n> > \n> > The thermal sensors on A64 and H5 is like the one on H3, but with of\n> > course different formula factors.\n> > \n> > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n> > ---\n> > Changes in v4:\n> > - Splitted out some code refactors.\n> > - Code sequence changed back. (The gpadc_data went back to the start of\n> >   the source file)\n> > \n> >  drivers/iio/adc/sun4i-gpadc-iio.c | 48 +++++++++++++++++++++++++++++++++++++++\n> >  include/linux/mfd/sun4i-gpadc.h   | 27 ++++++++++++++++++++++\n> >  2 files changed, 75 insertions(+)  \n> [...]\n> > diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h\n> > index 78d31984a222..5c2a12101052 100644\n> > --- a/include/linux/mfd/sun4i-gpadc.h\n> > +++ b/include/linux/mfd/sun4i-gpadc.h  \n> [...]\n> > +#define SUN8I_H3_GPADC_CTRL2_T_ACQ1(x)\t\t\t((GENMASK(15, 0) * (x)) << 16)\n> > +  \n> \n> You want to replace * by &.\n> \n> ((GENMASK(15, 0) & (x)) << 16)\n> \n> Would ((GENMASK(31, 16) & ((x) << 16)) make the bits you set even more\n> obvious?\n\nAgreed. Would act as better 'documentation'.\n\nJonathan\n> \n> >  #define SUN4I_GPADC_CTRL3\t\t\t\t0x0c\n> > +/*\n> > + * This register is named \"Average filter Control Register\" in H3 Datasheet,\n> > + * but the register's definition is the same as the old CTRL3 register.\n> > + */\n> > +#define SUN8I_H3_GPADC_CTRL3\t\t\t\t0x70\n> >    \n> \n> I would name it as it is in the documentation:\n> SUN8I_H3_THS_FILTER\n> \n> No need for comments then.\n> \n> >  #define SUN4I_GPADC_CTRL3_FILTER_EN\t\t\tBIT(2)\n> >  #define SUN4I_GPADC_CTRL3_FILTER_TYPE(x)\t\t(GENMASK(1, 0) & (x))\n> > @@ -71,6 +84,13 @@\n> >  #define SUN4I_GPADC_INT_FIFOC_TP_UP_IRQ_EN\t\tBIT(1)\n> >  #define SUN4I_GPADC_INT_FIFOC_TP_DOWN_IRQ_EN\t\tBIT(0)\n> >  \n> > +#define SUN8I_H3_GPADC_INTC\t\t\t\t0x44\n> > +\n> > +#define SUN8I_H3_GPADC_INTC_TEMP_PERIOD(x)\t\t((GENMASK(19, 0) & (x)) << 12)\n> > +#define SUN8I_H3_GPADC_INTC_TEMP_DATA\t\t\tBIT(8)\n> > +#define SUN8I_H3_GPADC_INTC_TEMP_SHUT\t\t\tBIT(4)\n> > +#define SUN8I_H3_GPADC_INTC_TEMP_ALARM\t\t\tBIT(0)\n> > +  \n> \n> Since it isn't an ADC anymore but rather just a THS, why don't you use\n> SUN8I_H3_THS instead of SUN8I_H3_GPADC? That way, it also matches the\n> datasheet.\n> \n> >  #define SUN4I_GPADC_INT_FIFOS\t\t\t\t0x14\n> >  \n> >  #define SUN4I_GPADC_INT_FIFOS_TEMP_DATA_PENDING\t\tBIT(18)\n> > @@ -80,9 +100,16 @@\n> >  #define SUN4I_GPADC_INT_FIFOS_TP_UP_PENDING\t\tBIT(1)\n> >  #define SUN4I_GPADC_INT_FIFOS_TP_DOWN_PENDING\t\tBIT(0)\n> >  \n> > +#define SUN8I_H3_GPADC_INTS\t\t\t\t0x44  \n> \n> 0x48\n> \n> [...]\n> \n> 1) You're not using irqs, why would you define registers that will never\n> be used?\n> \n> 2) Why aren't you using irqs? I remember we discussed on IRC that you\n> had some problems with the H3 when resuming or when probing the driver.\n> The register would have a zero in it until you have a first sample that\n> arrived (i.e. after the sample rate you set with T_ACQ) that would make\n> the thermal framework panic since the thermal sensor would return\n> something way too hot and shutdown your board?\n> \n> The H3 apparently supports IRQs, why do you not support them for the\n> temperature? They might be broken as it is on A33 but then it might be a\n> good idea to write it down in a comment in the driver (and not adding\n> the unused registers in the header file) or at least in the commit log.\n> \n> 3) Now that you have support for clocks, wouldn't it be a good idea to\n> disable them during suspend?\n> \n> Thanks,\n> Quentin","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"js6s85eT\"; dkim-atps=neutral","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=jic23@kernel.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xvmpS2T9Xz9sRm\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tSun, 17 Sep 2017 08:17:04 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dtLOU-0001ge-UG; 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x86_64-pc-linux-gnu)","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170916_151652_107962_904A24E6 ","X-CRM114-Status":"GOOD (  27.68  )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-6.9 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [198.145.29.99 listed in list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"devicetree@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,\n\tChen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>,\n\tMaxime Ripard <maxime.ripard@free-electrons.com>,\n\tLee Jones <lee.jones@linaro.org>, linux-arm-kernel@lists.infradead.org,\n\tIcenowy Zheng <icenowy@aosc.io>","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1769649,"web_url":"http://patchwork.ozlabs.org/comment/1769649/","msgid":"<20170916151734.10968b7a@archlinux>","list_archive_url":null,"date":"2017-09-16T22:17:34","subject":"Re: [PATCH v4 6/6] ARM: sun8i: h3: add partial CPU thermal zone","submitter":{"id":10151,"url":"http://patchwork.ozlabs.org/api/people/10151/","name":"Jonathan Cameron","email":"jic23@kernel.org"},"content":"On Sat, 16 Sep 2017 12:05:49 +0200\nQuentin Schulz <quentin.schulz@free-electrons.com> wrote:\n\n> Hi Icenowy,\n> \n> On 14/09/2017 16:52, Icenowy Zheng wrote:\n> > Because of the restriction of the OF thermal framework, the thermal\n> > sensor will fail to probe if the thermal zone doesn't exist.\n> >   \n> \n> Oh no, that's not good.\n> \n> We discussed about it on IRC and I even proposed a patch for it, telling\n> you I would post it on the mailing list soon after. Of course, I forgot\n> and you definitely should have yelled at me for not doing it :)\n> \n> I won't be able to test the patch soon. I can send it to you so that you\n> can test it and integrate it in your patch series so it won't block you.\n> Otherwise, we'll have to wait for a week or two for me to test it.\n> \n> Thanks and sorry for forgetting to post the patch you need,\n> Quentin\n\nOther this outstanding issue I'm happy with the series, so hopefully\nwith Quentin's patch added we should be good to merge this one.\n\nJonathan\n\n> \n> > Add a partial thermal zone which claims the H3 THS as the thermal sensor.\n> > \n> > The cooling device (CPU DVFS) is still not added as it's not ready, and\n> > the trip points are also not added yet.\n> > \n> > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n> > ---\n> >  arch/arm/boot/dts/sun8i-h3.dtsi | 9 +++++++++\n> >  1 file changed, 9 insertions(+)\n> > \n> > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi\n> > index 3220da3ad790..687c6457d214 100644\n> > --- a/arch/arm/boot/dts/sun8i-h3.dtsi\n> > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi\n> > @@ -89,6 +89,15 @@\n> >  \t\t};\n> >  \t};\n> >  \n> > +\tthermal-zones {\n> > +\t\tcpu-thermal {\n> > +\t\t\t/* milliseconds */\n> > +\t\t\tpolling-delay-passive = <250>;\n> > +\t\t\tpolling-delay = <1000>;\n> > +\t\t\tthermal-sensors = <&ths>;\n> > +\t\t};\n> > +\t};\n> > +\n> >  \ttimer {\n> >  \t\tcompatible = \"arm,armv7-timer\";\n> >  \t\tinterrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,\n> >   \n>","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"tWAGYf0g\"; dkim-atps=neutral","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=jic23@kernel.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xvmqj3qdwz9sRm\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tSun, 17 Sep 2017 08:18:09 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dtLPZ-00028B-W1; Sat, 16 Sep 2017 22:18:06 +0000","from mail.kernel.org ([198.145.29.99])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dtLPR-0001xn-R9 for linux-arm-kernel@lists.infradead.org;\n\tSat, 16 Sep 2017 22:18:03 +0000","from archlinux (unknown [207.243.58.180])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id E68C922A73;\n\tSat, 16 Sep 2017 22:17:36 +0000 (UTC)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=p8wbhntSfHw5+zao7sENki5wRmZHGGAg9zjQt+ffjS8=;\n\tb=tWAGYf0gjhyzP/\n\tVwjVBmP63jXy3iXwCCseuKW31ANWW4mfDcgW60zGemwbtGMNF1mXzgSPlB/En2ZdLas2szklWxvMf\n\txyJmlhP7+h8faNsTq6UWT7wrKqFq/3M+AstqZ0wTvvl4LyAkF8c1WXWBbvUgwk+oFg4Sc7zcm6dCY\n\t2nDGvRSr2vnACKehwUSKKzQwc4gPmPrQDXww3g1KAcNYnJfH4ZifvKXkutdRpMtROtoMDBWioc1Se\n\tln3nav29iVSalwIkBLvsFkCpC9iLGclY5L1toe5GSQN+5wa8MmwlFUgbgCHD1adbULIj9O7E2lePM\n\tZKM2bk12cRRJ4TLfGFkQ==;","DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org E68C922A73","Date":"Sat, 16 Sep 2017 15:17:34 -0700","From":"Jonathan Cameron <jic23@kernel.org>","To":"Quentin Schulz <quentin.schulz@free-electrons.com>","Subject":"Re: [PATCH v4 6/6] ARM: sun8i: h3: add partial CPU thermal zone","Message-ID":"<20170916151734.10968b7a@archlinux>","In-Reply-To":"<b41a80ec-23d5-a614-f6cc-d09c5a459e03@free-electrons.com>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-7-icenowy@aosc.io>\n\t<b41a80ec-23d5-a614-f6cc-d09c5a459e03@free-electrons.com>","X-Mailer":"Claws Mail 3.15.1-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu)","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170916_151758_081194_35B842AB ","X-CRM114-Status":"GOOD (  22.03  )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-6.9 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [198.145.29.99 listed in list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"devicetree@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,\n\tChen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>,\n\tMaxime Ripard <maxime.ripard@free-electrons.com>,\n\tLee Jones <lee.jones@linaro.org>, linux-arm-kernel@lists.infradead.org,\n\tIcenowy Zheng <icenowy@aosc.io>","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1769910,"web_url":"http://patchwork.ozlabs.org/comment/1769910/","msgid":"<20170918073336.j7finend3g76chsu@flea.lan>","list_archive_url":null,"date":"2017-09-18T07:33:36","subject":"Re: [PATCH v4 1/6] dt-bindings: update the Allwinner GPADC device\n\ttree binding for H3","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Thu, Sep 14, 2017 at 10:52:46PM +0800, Icenowy Zheng wrote:\n> Allwinner H3 features a thermal sensor like the one in A33, but has its\n> register re-arranged, the clock divider moved to CCU (originally the\n> clock divider is in ADC) and added a pair of bus clock and reset.\n> \n> Update the binding document to cover H3.\n> \n> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n> Reviewed-by: Chen-Yu Tsai <wens@csie.org>\n> ---\n> Changes in v4:\n> - Add nvmem calibration data (not yet used by the driver)\n> Changes in v3:\n> - Clock name changes.\n> - Example node name changes.\n> - Add interupts (not yet used by the driver).\n> \n>  .../devicetree/bindings/mfd/sun4i-gpadc.txt        | 30 ++++++++++++++++++++--\n>  1 file changed, 28 insertions(+), 2 deletions(-)\n> \n> diff --git a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n> index badff3611a98..6c470d584bf9 100644\n> --- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n> +++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n> @@ -4,12 +4,26 @@ The Allwinner SoCs all have an ADC that can also act as a thermal sensor\n>  and sometimes as a touchscreen controller.\n>  \n>  Required properties:\n> -  - compatible: \"allwinner,sun8i-a33-ths\",\n> +  - compatible: must contain one of the following compatibles:\n> +\t\t- \"allwinner,sun8i-a33-ths\"\n> +\t\t- \"allwinner,sun8i-h3-ths\"\n>    - reg: mmio address range of the chip,\n>    - #thermal-sensor-cells: shall be 0,\n>    - #io-channel-cells: shall be 0,\n>  \n> -Example:\n> +Optional properties:\n> +  - nvmem-cells: A phandle to the calibration data provided by a nvmem device.\n> +                 If unspecified default values shall be used.\n> +  - nvmem-cell-names: Should be \"calibration-data\"\n\nI'd prefer to have which sensor it applies to here. It wouldn't change\nanything for the H3, but it definitely does for example for the A83t\nthat has two sensors, one for each cluster, and one for the GPU, each\nwith calibration data.\n\nWhat about cluster0-calibration?\n\n> +\n> +Required properties for the following compatibles:\n> +\t\t- \"allwinner,sun8i-h3-ths\"\n> +  - clocks: the bus clock and the input clock of the ADC,\n> +  - clock-names: should be \"bus\" and \"mod\",\n> +  - resets: the bus reset of the ADC,\n> +  - interrupts: the sampling interrupt of the ADC,\n\nFor resets and interrupts, you should list all of them. If there's\nonly one, then there's no point telling which one it is.\n\n\nThanks,\nMaxime","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"a3jHiMUF\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwd736Zsxz9ryQ\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tMon, 18 Sep 2017 17:34:22 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dtqZN-0007We-Oj; Mon, 18 Sep 2017 07:34:17 +0000","from mail.free-electrons.com ([62.4.15.54])\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dtqZB-0007Rz-HN for linux-arm-kernel@lists.infradead.org;\n\tMon, 18 Sep 2017 07:34:11 +0000","by mail.free-electrons.com (Postfix, from userid 110)\n\tid EC0A8209DF; Mon, 18 Sep 2017 09:33:36 +0200 (CEST)","from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id B854D2094F;\n\tMon, 18 Sep 2017 09:33:36 +0200 (CEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type:Cc:\n\tList-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:\n\tIn-Reply-To:MIME-Version:References:Message-ID:Subject:To:From:Date:Reply-To:\n\tContent-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;\n\tbh=8zCFhAiCfGJbEjdf4UCGv7Z/0ASVeqR/eeiomXUSyRU=;\n\tb=a3jHiMUFNJeMV/h0Hs0KdwPOp\n\tcN/Bl0DPisSk46zzs4MZpkJ+lewmABCwPaFMv8ILAux0fpvTnMbowLCtEWhRxzYsowq6God/Q8JEY\n\t/wBKp/BlpLzhgIYnjbUO7jM32SiypRNpiNp2cJjBUYFmsN7/zqNIZlgeCfu7DPjWLJl4iTGAxCBUO\n\t+YZH0dcvJ/BfTfW3KvdiGqFRSKACDKJrguitGI49M1FFs6d/J1OG354VtIZ8RE/PcsSU5pJZx8oNL\n\tmgnUHxJd6gRYk4nsVKVnCmYjHPv0ABL8VzfokdDtf03bJSTvNsfBhVv4X7/6yzXJfAw9Z4lElaXtr\n\tvzGu0H6iA==;","X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Mon, 18 Sep 2017 09:33:36 +0200","From":"Maxime Ripard <maxime.ripard@free-electrons.com>","To":"Icenowy Zheng <icenowy@aosc.io>","Subject":"Re: [PATCH v4 1/6] dt-bindings: update the Allwinner GPADC device\n\ttree binding for H3","Message-ID":"<20170918073336.j7finend3g76chsu@flea.lan>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-2-icenowy@aosc.io>","MIME-Version":"1.0","In-Reply-To":"<20170914145251.21784-2-icenowy@aosc.io>","User-Agent":"NeoMutt/20170714 (1.8.3)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170918_003408_587369_0D0BD8A3 ","X-CRM114-Status":"GOOD (  19.68  )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-1.9 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"devicetree@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,\n\tQuentin Schulz <quentin.schulz@free-electrons.com>,\n\tChen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>,\n\tlinux-arm-kernel@lists.infradead.org, Lee Jones <lee.jones@linaro.org>,\n\tJonathan Cameron <jic23@kernel.org>","Content-Type":"multipart/mixed;\n\tboundary=\"===============6460418565171357810==\"","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1769912,"web_url":"http://patchwork.ozlabs.org/comment/1769912/","msgid":"<20170918073452.2jizidgu4rvqesiq@flea.lan>","list_archive_url":null,"date":"2017-09-18T07:34:52","subject":"Re: [PATCH v4 2/6] iio: adc: sun4i-gpadc-iio: rename A33-specified\n\tregisters to contain A33","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Thu, Sep 14, 2017 at 10:52:47PM +0800, Icenowy Zheng wrote:\n> As the H3 SoC, which is also in sun8i line, has totally different\n> register map for the thermal sensor (a cut down version of GPADC), we\n> should rename A23/A33-specified registers to contain A33, in order to\n> prevent obfuscation with H3 registers. Currently these registers are\n> only prefixed \"SUN8I\", not \"SUN8I_A33\".\n> \n> Add \"_A33\" after \"SUN8I\" on the register names.\n> \n> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n> Reviewed-by: Chen-Yu Tsai <wens@csie.org>\n\nAcked-by: Maxime Ripard <maxime.ripard@free-electrons.com>\n\nMaxime","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"SSrsVx57\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwd8F0vTzz9ryQ\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tMon, 18 Sep 2017 17:35:25 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dtqaP-0000mM-AC; Mon, 18 Sep 2017 07:35:21 +0000","from mail.free-electrons.com ([62.4.15.54])\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dtqaH-0007uW-9Y for linux-arm-kernel@lists.infradead.org;\n\tMon, 18 Sep 2017 07:35:18 +0000","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 11EFB209DF; Mon, 18 Sep 2017 09:34:52 +0200 (CEST)","from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id D813F2094F;\n\tMon, 18 Sep 2017 09:34:51 +0200 (CEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type:Cc:\n\tList-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:\n\tIn-Reply-To:MIME-Version:References:Message-ID:Subject:To:From:Date:Reply-To:\n\tContent-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;\n\tbh=LtnmByquZFCYbpXRzXRvO6zC+slHCqGCzTo6svmksbs=;\n\tb=SSrsVx57QqgtDQUhNNLOnSesf\n\tmJyyv4u8XmLE/vytpPzK6FcK96C99zNNDsnAvJFxvGt514zJvRyLV4tC1yBErIW3x8cSnc/RJDZYC\n\teZSeR2SzDMWLCh9gFmE0mPqlBndq2ie8Fs/H7lxAqW/6i9O3JPU+MrgkGNFybFfwJZDDlu6/wgmAp\n\tdpigo3NjXv5/N3Jiep8vooVLl7JuDDKFQyv0kpZ7HwMp6tfzeArQzCWB0H0aDl2LgZ3Ah5fksLPO6\n\t6sEea0SFw8JM+HECwkWBJK70IaDYrx3hlGnmoo736ZunbyNdOds8zedSstA/dWj4LzPpf1Bkd4tJz\n\tK5xf4/DiA==;","X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Mon, 18 Sep 2017 09:34:52 +0200","From":"Maxime Ripard <maxime.ripard@free-electrons.com>","To":"Icenowy Zheng <icenowy@aosc.io>","Subject":"Re: [PATCH v4 2/6] iio: adc: sun4i-gpadc-iio: rename A33-specified\n\tregisters to contain A33","Message-ID":"<20170918073452.2jizidgu4rvqesiq@flea.lan>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-3-icenowy@aosc.io>","MIME-Version":"1.0","In-Reply-To":"<20170914145251.21784-3-icenowy@aosc.io>","User-Agent":"NeoMutt/20170714 (1.8.3)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170918_003513_591940_5E84333F ","X-CRM114-Status":"GOOD (  11.38  )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-1.9 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"devicetree@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,\n\tQuentin Schulz <quentin.schulz@free-electrons.com>,\n\tChen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>,\n\tlinux-arm-kernel@lists.infradead.org, Lee Jones <lee.jones@linaro.org>,\n\tJonathan Cameron <jic23@kernel.org>","Content-Type":"multipart/mixed;\n\tboundary=\"===============5733893595607598087==\"","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1769915,"web_url":"http://patchwork.ozlabs.org/comment/1769915/","msgid":"<20170918073601.oiqshnhhl7yb6fv2@flea.lan>","list_archive_url":null,"date":"2017-09-18T07:36:01","subject":"Re: [PATCH v4 3/6] iio: adc: sun4i-gpadc-iio: rework code for\n\tsupporting newer THS variants","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Thu, Sep 14, 2017 at 10:52:48PM +0800, Icenowy Zheng wrote:\n> The SoCs after H3 has newer thermal sensor ADCs, which have two clock\n> inputs (bus clock and sampling clock) and a reset. The registers are\n> also re-arranged.\n> \n> This commit reworks the code, adds the process of the clocks and\n> resets, and allows the sampling start/end code and the position of value\n> readout register to be altered.\n> \n> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n\nPlease split that into separate commits.\n\nMaxime","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"nNve9Qoy\"; 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(2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Mon, 18 Sep 2017 09:36:01 +0200","From":"Maxime Ripard <maxime.ripard@free-electrons.com>","To":"Icenowy Zheng <icenowy@aosc.io>","Subject":"Re: [PATCH v4 3/6] iio: adc: sun4i-gpadc-iio: rework code for\n\tsupporting newer THS variants","Message-ID":"<20170918073601.oiqshnhhl7yb6fv2@flea.lan>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-4-icenowy@aosc.io>","MIME-Version":"1.0","In-Reply-To":"<20170914145251.21784-4-icenowy@aosc.io>","User-Agent":"NeoMutt/20170714 (1.8.3)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170918_003623_914326_2983A0E5 ","X-CRM114-Status":"GOOD (  12.07  )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-1.9 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"devicetree@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,\n\tQuentin Schulz <quentin.schulz@free-electrons.com>,\n\tChen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>,\n\tlinux-arm-kernel@lists.infradead.org, Lee Jones <lee.jones@linaro.org>,\n\tJonathan Cameron <jic23@kernel.org>","Content-Type":"multipart/mixed;\n\tboundary=\"===============6778837949778119441==\"","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1769946,"web_url":"http://patchwork.ozlabs.org/comment/1769946/","msgid":"<310CE549-B8CE-4C0C-95B1-B545E38BDAF5@aosc.io>","list_archive_url":null,"date":"2017-09-18T07:36:43","subject":"Re: [PATCH v4 1/6] dt-bindings: update the Allwinner GPADC device\n\ttree binding for H3","submitter":{"id":71295,"url":"http://patchwork.ozlabs.org/api/people/71295/","name":"Icenowy Zheng","email":"icenowy@aosc.io"},"content":"于 2017年9月18日 GMT+08:00 下午3:33:36, Maxime Ripard <maxime.ripard@free-electrons.com> 写到:\n>On Thu, Sep 14, 2017 at 10:52:46PM +0800, Icenowy Zheng wrote:\n>> Allwinner H3 features a thermal sensor like the one in A33, but has\n>its\n>> register re-arranged, the clock divider moved to CCU (originally the\n>> clock divider is in ADC) and added a pair of bus clock and reset.\n>> \n>> Update the binding document to cover H3.\n>> \n>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n>> Reviewed-by: Chen-Yu Tsai <wens@csie.org>\n>> ---\n>> Changes in v4:\n>> - Add nvmem calibration data (not yet used by the driver)\n>> Changes in v3:\n>> - Clock name changes.\n>> - Example node name changes.\n>> - Add interupts (not yet used by the driver).\n>> \n>>  .../devicetree/bindings/mfd/sun4i-gpadc.txt        | 30\n>++++++++++++++++++++--\n>>  1 file changed, 28 insertions(+), 2 deletions(-)\n>> \n>> diff --git a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n>b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n>> index badff3611a98..6c470d584bf9 100644\n>> --- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n>> +++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n>> @@ -4,12 +4,26 @@ The Allwinner SoCs all have an ADC that can also\n>act as a thermal sensor\n>>  and sometimes as a touchscreen controller.\n>>  \n>>  Required properties:\n>> -  - compatible: \"allwinner,sun8i-a33-ths\",\n>> +  - compatible: must contain one of the following compatibles:\n>> +\t\t- \"allwinner,sun8i-a33-ths\"\n>> +\t\t- \"allwinner,sun8i-h3-ths\"\n>>    - reg: mmio address range of the chip,\n>>    - #thermal-sensor-cells: shall be 0,\n>>    - #io-channel-cells: shall be 0,\n>>  \n>> -Example:\n>> +Optional properties:\n>> +  - nvmem-cells: A phandle to the calibration data provided by a\n>nvmem device.\n>> +                 If unspecified default values shall be used.\n>> +  - nvmem-cell-names: Should be \"calibration-data\"\n>\n>I'd prefer to have which sensor it applies to here. It wouldn't change\n>anything for the H3, but it definitely does for example for the A83t\n>that has two sensors, one for each cluster, and one for the GPU, each\n>with calibration data.\n>\n>What about cluster0-calibration?\n\nThe calibration data is in fact a 2 word (8 bytes) zone,\nwhich is reserved for 4 sensors on all SoCs, even on H3.\nIt's half word per sensor.\n\nI prefer to just assume a 2 word cell for every SoC.\n\n>\n>> +\n>> +Required properties for the following compatibles:\n>> +\t\t- \"allwinner,sun8i-h3-ths\"\n>> +  - clocks: the bus clock and the input clock of the ADC,\n>> +  - clock-names: should be \"bus\" and \"mod\",\n>> +  - resets: the bus reset of the ADC,\n>> +  - interrupts: the sampling interrupt of the ADC,\n>\n>For resets and interrupts, you should list all of them. If there's\n>only one, then there's no point telling which one it is.\n>\n>\n>Thanks,\n>Maxime","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"CEAkoCqg\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=infradead.org header.i=@infradead.org\n\theader.b=\"YoRSsKX9\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwdq91qcNz9s3w\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tMon, 18 Sep 2017 18:05:41 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dtr3f-0002rp-JX; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1769968,"web_url":"http://patchwork.ozlabs.org/comment/1769968/","msgid":"<20170918082402.fa5mg2ucqouh3ti5@flea.lan>","list_archive_url":null,"date":"2017-09-18T08:24:02","subject":"Re: [PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3\n\tthermal sensor","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Sat, Sep 16, 2017 at 06:14:08PM +0800, icenowy@aosc.io wrote:\n> > The H3 apparently supports IRQs, why do you not support them for the\n> > temperature? They might be broken as it is on A33 but then it might be a\n> > good idea to write it down in a comment in the driver (and not adding\n> > the unused registers in the header file) or at least in the commit log.\n> > \n> > 3) Now that you have support for clocks, wouldn't it be a good idea to\n> > disable them during suspend?\n> \n> Interesting... It's meaningful to disable the mod clock during suspend.\n\nAll clocks, actually. And put the device back into reset.\n\nMaxime","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"KFH7VFSC\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwfF46BFfz9s3w\n\tfor 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version=3.4.0","Date":"Mon, 18 Sep 2017 10:24:02 +0200","From":"Maxime Ripard <maxime.ripard@free-electrons.com>","To":"icenowy@aosc.io","Subject":"Re: [PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3\n\tthermal sensor","Message-ID":"<20170918082402.fa5mg2ucqouh3ti5@flea.lan>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-5-icenowy@aosc.io>\n\t<445ea236-35e9-8d5a-e580-b2bdcf5f7776@free-electrons.com>\n\t<0b395ea1743a14a62855fc2a2dc74411@aosc.io>","MIME-Version":"1.0","In-Reply-To":"<0b395ea1743a14a62855fc2a2dc74411@aosc.io>","User-Agent":"NeoMutt/20170714 (1.8.3)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170918_012433_357170_470E5BF4 ","X-CRM114-Status":"GOOD (  15.36  )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-1.9 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"devicetree@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,\n\tQuentin Schulz <quentin.schulz@free-electrons.com>,\n\tChen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>,\n\tlinux-arm-kernel@lists.infradead.org, Lee Jones <lee.jones@linaro.org>,\n\tJonathan Cameron <jic23@kernel.org>","Content-Type":"multipart/mixed;\n\tboundary=\"===============0220010989635840926==\"","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1769970,"web_url":"http://patchwork.ozlabs.org/comment/1769970/","msgid":"<20170918082512.ovzwuorvwqjkueqa@flea.lan>","list_archive_url":null,"date":"2017-09-18T08:25:12","subject":"Re: [PATCH v4 5/6] ARM: sun8i: h3: add support for the thermal\n\tsensor in H3","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Thu, Sep 14, 2017 at 10:52:50PM +0800, Icenowy Zheng wrote:\n> As we have gained the support for the thermal sensor in H3, we can now\n> add its device nodes to the device tree.\n> \n> Add them to the H3 device tree.\n> \n> The calibration data of the thermal sensor is still not added, as\n> it's currently not used, and the SID node is not added yet.\n> \n> The H5 thermal sensor has some differences, and will be added furtherly.\n> \n> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n> Reviewed-by: Chen-Yu Tsai <wens@csie.org>\n> ---\n> Changes in v4:\n> - Mention calibration data in commit message.\n> Changes in v3:\n> - Clock name changes.\n> - Splited out thermal zone addition.\n> \n>  arch/arm/boot/dts/sun8i-h3.dtsi | 17 +++++++++++++++++\n>  1 file changed, 17 insertions(+)\n> \n> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi\n> index b36f9f423c39..3220da3ad790 100644\n> --- a/arch/arm/boot/dts/sun8i-h3.dtsi\n> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi\n> @@ -72,6 +72,23 @@\n>  \t\t};\n>  \t};\n>  \n> +\tiio-hwmon {\n> +\t\tcompatible = \"iio-hwmon\";\n> +\t\tio-channels = <&ths>;\n> +\t};\n> +\n> +\tsoc {\n> +\t\tths: thermal-sensor@1c25000 {\n> +\t\t\tcompatible = \"allwinner,sun8i-h3-ths\";\n> +\t\t\treg = <0x01c25000 0x100>;\n> +\t\t\tclocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;\n> +\t\t\tclock-names = \"bus\", \"mod\";\n> +\t\t\tresets = <&ccu RST_BUS_THS>;\n> +\t\t\t#thermal-sensor-cells = <0>;\n> +\t\t\t#io-channel-cells = <0>;\n\nYou're missing your interrupt.\n\nMaxime","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none 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autolearn=disabled version=3.4.0","Date":"Mon, 18 Sep 2017 10:25:12 +0200","From":"Maxime Ripard <maxime.ripard@free-electrons.com>","To":"Icenowy Zheng <icenowy@aosc.io>","Subject":"Re: [PATCH v4 5/6] ARM: sun8i: h3: add support for the thermal\n\tsensor in H3","Message-ID":"<20170918082512.ovzwuorvwqjkueqa@flea.lan>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-6-icenowy@aosc.io>","MIME-Version":"1.0","In-Reply-To":"<20170914145251.21784-6-icenowy@aosc.io>","User-Agent":"NeoMutt/20170714 (1.8.3)","X-Spam-Note":"CRM114 invocation failed","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on merlin.infradead.org summary:\n\tContent analysis details:   (-1.9 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"devicetree@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,\n\tQuentin Schulz <quentin.schulz@free-electrons.com>,\n\tChen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>,\n\tlinux-arm-kernel@lists.infradead.org, Lee Jones <lee.jones@linaro.org>,\n\tJonathan Cameron <jic23@kernel.org>","Content-Type":"multipart/mixed;\n\tboundary=\"===============6068878582035759393==\"","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1769972,"web_url":"http://patchwork.ozlabs.org/comment/1769972/","msgid":"<20170918082703.riqntqilakzhirc5@flea.lan>","list_archive_url":null,"date":"2017-09-18T08:27:03","subject":"Re: [PATCH v4 6/6] ARM: sun8i: h3: add partial CPU thermal zone","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"Hi Jonathan,\n\nOn Sat, Sep 16, 2017 at 03:17:34PM -0700, Jonathan Cameron wrote:\n> On Sat, 16 Sep 2017 12:05:49 +0200\n> Quentin Schulz <quentin.schulz@free-electrons.com> wrote:\n> \n> > Hi Icenowy,\n> > \n> > On 14/09/2017 16:52, Icenowy Zheng wrote:\n> > > Because of the restriction of the OF thermal framework, the thermal\n> > > sensor will fail to probe if the thermal zone doesn't exist.\n> > >   \n> > \n> > Oh no, that's not good.\n> > \n> > We discussed about it on IRC and I even proposed a patch for it, telling\n> > you I would post it on the mailing list soon after. Of course, I forgot\n> > and you definitely should have yelled at me for not doing it :)\n> > \n> > I won't be able to test the patch soon. I can send it to you so that you\n> > can test it and integrate it in your patch series so it won't block you.\n> > Otherwise, we'll have to wait for a week or two for me to test it.\n> > \n> > Thanks and sorry for forgetting to post the patch you need,\n> > Quentin\n> \n> Other this outstanding issue I'm happy with the series, so hopefully\n> with Quentin's patch added we should be good to merge this one.\n\nWe will at least need a v5.\n\nMaxime","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) 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version=3.4.0","Date":"Mon, 18 Sep 2017 10:27:03 +0200","From":"Maxime Ripard <maxime.ripard@free-electrons.com>","To":"Jonathan Cameron <jic23@kernel.org>","Subject":"Re: [PATCH v4 6/6] ARM: sun8i: h3: add partial CPU thermal zone","Message-ID":"<20170918082703.riqntqilakzhirc5@flea.lan>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-7-icenowy@aosc.io>\n\t<b41a80ec-23d5-a614-f6cc-d09c5a459e03@free-electrons.com>\n\t<20170916151734.10968b7a@archlinux>","MIME-Version":"1.0","In-Reply-To":"<20170916151734.10968b7a@archlinux>","User-Agent":"NeoMutt/20170714 (1.8.3)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170918_012734_965823_A188B1CB ","X-CRM114-Status":"GOOD (  19.82  )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-1.9 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"devicetree@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,\n\tQuentin Schulz <quentin.schulz@free-electrons.com>,\n\tChen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>,\n\tLee Jones <lee.jones@linaro.org>, linux-arm-kernel@lists.infradead.org,\n\tIcenowy Zheng <icenowy@aosc.io>","Content-Type":"multipart/mixed;\n\tboundary=\"===============1356908577290831887==\"","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1769978,"web_url":"http://patchwork.ozlabs.org/comment/1769978/","msgid":"<20170918083045.7bfiialtbm7w6i7j@flea.lan>","list_archive_url":null,"date":"2017-09-18T08:30:45","subject":"Re: [PATCH v4 1/6] dt-bindings: update the Allwinner GPADC device\n\ttree binding for H3","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Mon, Sep 18, 2017 at 03:36:43PM +0800, Icenowy Zheng wrote:\n> 于 2017年9月18日 GMT+08:00 下午3:33:36, Maxime Ripard <maxime.ripard@free-electrons.com> 写到:\n> >On Thu, Sep 14, 2017 at 10:52:46PM +0800, Icenowy Zheng wrote:\n> >> Allwinner H3 features a thermal sensor like the one in A33, but has\n> >its\n> >> register re-arranged, the clock divider moved to CCU (originally the\n> >> clock divider is in ADC) and added a pair of bus clock and reset.\n> >> \n> >> Update the binding document to cover H3.\n> >> \n> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n> >> Reviewed-by: Chen-Yu Tsai <wens@csie.org>\n> >> ---\n> >> Changes in v4:\n> >> - Add nvmem calibration data (not yet used by the driver)\n> >> Changes in v3:\n> >> - Clock name changes.\n> >> - Example node name changes.\n> >> - Add interupts (not yet used by the driver).\n> >> \n> >>  .../devicetree/bindings/mfd/sun4i-gpadc.txt        | 30\n> >++++++++++++++++++++--\n> >>  1 file changed, 28 insertions(+), 2 deletions(-)\n> >> \n> >> diff --git a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n> >b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n> >> index badff3611a98..6c470d584bf9 100644\n> >> --- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n> >> +++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n> >> @@ -4,12 +4,26 @@ The Allwinner SoCs all have an ADC that can also\n> >act as a thermal sensor\n> >>  and sometimes as a touchscreen controller.\n> >>  \n> >>  Required properties:\n> >> -  - compatible: \"allwinner,sun8i-a33-ths\",\n> >> +  - compatible: must contain one of the following compatibles:\n> >> +\t\t- \"allwinner,sun8i-a33-ths\"\n> >> +\t\t- \"allwinner,sun8i-h3-ths\"\n> >>    - reg: mmio address range of the chip,\n> >>    - #thermal-sensor-cells: shall be 0,\n> >>    - #io-channel-cells: shall be 0,\n> >>  \n> >> -Example:\n> >> +Optional properties:\n> >> +  - nvmem-cells: A phandle to the calibration data provided by a\n> >nvmem device.\n> >> +                 If unspecified default values shall be used.\n> >> +  - nvmem-cell-names: Should be \"calibration-data\"\n> >\n> >I'd prefer to have which sensor it applies to here. It wouldn't change\n> >anything for the H3, but it definitely does for example for the A83t\n> >that has two sensors, one for each cluster, and one for the GPU, each\n> >with calibration data.\n> >\n> >What about cluster0-calibration?\n> \n> The calibration data is in fact a 2 word (8 bytes) zone,\n> which is reserved for 4 sensors on all SoCs, even on H3.\n> It's half word per sensor.\n> \n> I prefer to just assume a 2 word cell for every SoC.\n\nYou have three different data sources, it should be reprensented as\nsuch.\n\nOtherwise, the client has to get some knowledge of how the data are\nstored in the provider, which is an abstraction violation.\n\nMaxime","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"Kd4AD2py\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwfP94rNyz9s7c\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tMon, 18 Sep 2017 18:31:41 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dtrSr-0004M5-V1; Mon, 18 Sep 2017 08:31:37 +0000","from mail.free-electrons.com ([62.4.15.54])\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dtrSf-0004D3-I2 for linux-arm-kernel@lists.infradead.org;\n\tMon, 18 Sep 2017 08:31:34 +0000","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 4FA3E2092D; Mon, 18 Sep 2017 10:31:04 +0200 (CEST)","from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 362B1207F6;\n\tMon, 18 Sep 2017 10:30:45 +0200 (CEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type:Cc:\n\tList-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:\n\tIn-Reply-To:MIME-Version:References:Message-ID:Subject:To:From:Date:Reply-To:\n\tContent-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;\n\tbh=KyGW5Lbmo+Zulo0dPg+Oyxc6CyWvIZ3twi2whJbKrzU=;\n\tb=Kd4AD2py/59PTiRFxx16Fw/mm\n\t2w834YKBK2YyqufKC60DsmgF27rng9Uq8bdHJ39j6C9051N7ZmE1G6bKGxfC1ve4FKHmZHpPuUNMb\n\t2+kuIjx1Cv4vb5VAd5A6CYFjeLNlfpsgCeB5X7bFOJuNZ4mM7r7MCs1gzxJIz9VeB0+G6uYUVAwe/\n\tVtod70dmZYQcuJ5okd8WLPTCF1XHBDEnqFv/4zyAOToF/a0l8xh0KMNQ8V0qFvaQgTALKwmHxfskc\n\tefF4pHkxvDNufIAye5lrytA3JSy4NVuCHbb2gpvujYOyZyfrHMpQJoSUIR/wp8806iHm3XifUv2xT\n\ti21/mQjIw==;","X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Mon, 18 Sep 2017 10:30:45 +0200","From":"Maxime Ripard <maxime.ripard@free-electrons.com>","To":"Icenowy Zheng <icenowy@aosc.io>","Subject":"Re: [PATCH v4 1/6] dt-bindings: update the Allwinner GPADC device\n\ttree binding for H3","Message-ID":"<20170918083045.7bfiialtbm7w6i7j@flea.lan>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-2-icenowy@aosc.io>\n\t<20170918073336.j7finend3g76chsu@flea.lan>\n\t<310CE549-B8CE-4C0C-95B1-B545E38BDAF5@aosc.io>","MIME-Version":"1.0","In-Reply-To":"<310CE549-B8CE-4C0C-95B1-B545E38BDAF5@aosc.io>","User-Agent":"NeoMutt/20170714 (1.8.3)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170918_013126_190818_B6A30827 ","X-CRM114-Status":"GOOD (  23.50  )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-1.9 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"devicetree@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,\n\tQuentin Schulz <quentin.schulz@free-electrons.com>,\n\tChen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>,\n\tlinux-arm-kernel@lists.infradead.org, Lee Jones <lee.jones@linaro.org>,\n\tJonathan Cameron <jic23@kernel.org>","Content-Type":"multipart/mixed;\n\tboundary=\"===============4896578819444588065==\"","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1769985,"web_url":"http://patchwork.ozlabs.org/comment/1769985/","msgid":"<20170918082948.2bl5e44tzsufdj7n@dell>","list_archive_url":null,"date":"2017-09-18T08:29:48","subject":"Re: [PATCH v4 2/6] iio: adc: sun4i-gpadc-iio: rename A33-specified\n\tregisters to contain A33","submitter":{"id":12720,"url":"http://patchwork.ozlabs.org/api/people/12720/","name":"Lee Jones","email":"lee.jones@linaro.org"},"content":"On Thu, 14 Sep 2017, Icenowy Zheng wrote:\n\n> As the H3 SoC, which is also in sun8i line, has totally different\n> register map for the thermal sensor (a cut down version of GPADC), we\n> should rename A23/A33-specified registers to contain A33, in order to\n> prevent obfuscation with H3 registers. Currently these registers are\n> only prefixed \"SUN8I\", not \"SUN8I_A33\".\n> \n> Add \"_A33\" after \"SUN8I\" on the register names.\n> \n> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n> Reviewed-by: Chen-Yu Tsai <wens@csie.org>\n> ---\n> Changes in v4:\n> - Change A23 to A33, as the driver never supports A23.\n> \n>  drivers/iio/adc/sun4i-gpadc-iio.c | 2 +-\n\n>  include/linux/mfd/sun4i-gpadc.h   | 6 +++---\n\nAcked-by: Lee Jones <lee.jones@linaro.org>","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"DqCEgEeN\"; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1770268,"web_url":"http://patchwork.ozlabs.org/comment/1770268/","msgid":"<e73ead447af89031749e85207cac1e69@aosc.io>","list_archive_url":null,"date":"2017-09-18T15:47:25","subject":"Re: [linux-sunxi] Re: [PATCH v4 1/6] dt-bindings: update the\n\tAllwinner GPADC device tree binding for H3","submitter":{"id":71295,"url":"http://patchwork.ozlabs.org/api/people/71295/","name":"Icenowy Zheng","email":"icenowy@aosc.io"},"content":"在 2017-09-18 16:30，Maxime Ripard 写道：\n> On Mon, Sep 18, 2017 at 03:36:43PM +0800, Icenowy Zheng wrote:\n>> 于 2017年9月18日 GMT+08:00 下午3:33:36, Maxime Ripard \n>> <maxime.ripard@free-electrons.com> 写到:\n>> >On Thu, Sep 14, 2017 at 10:52:46PM +0800, Icenowy Zheng wrote:\n>> >> Allwinner H3 features a thermal sensor like the one in A33, but has\n>> >its\n>> >> register re-arranged, the clock divider moved to CCU (originally the\n>> >> clock divider is in ADC) and added a pair of bus clock and reset.\n>> >>\n>> >> Update the binding document to cover H3.\n>> >>\n>> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n>> >> Reviewed-by: Chen-Yu Tsai <wens@csie.org>\n>> >> ---\n>> >> Changes in v4:\n>> >> - Add nvmem calibration data (not yet used by the driver)\n>> >> Changes in v3:\n>> >> - Clock name changes.\n>> >> - Example node name changes.\n>> >> - Add interupts (not yet used by the driver).\n>> >>\n>> >>  .../devicetree/bindings/mfd/sun4i-gpadc.txt        | 30\n>> >++++++++++++++++++++--\n>> >>  1 file changed, 28 insertions(+), 2 deletions(-)\n>> >>\n>> >> diff --git a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n>> >b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n>> >> index badff3611a98..6c470d584bf9 100644\n>> >> --- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n>> >> +++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n>> >> @@ -4,12 +4,26 @@ The Allwinner SoCs all have an ADC that can also\n>> >act as a thermal sensor\n>> >>  and sometimes as a touchscreen controller.\n>> >>\n>> >>  Required properties:\n>> >> -  - compatible: \"allwinner,sun8i-a33-ths\",\n>> >> +  - compatible: must contain one of the following compatibles:\n>> >> +\t\t- \"allwinner,sun8i-a33-ths\"\n>> >> +\t\t- \"allwinner,sun8i-h3-ths\"\n>> >>    - reg: mmio address range of the chip,\n>> >>    - #thermal-sensor-cells: shall be 0,\n>> >>    - #io-channel-cells: shall be 0,\n>> >>\n>> >> -Example:\n>> >> +Optional properties:\n>> >> +  - nvmem-cells: A phandle to the calibration data provided by a\n>> >nvmem device.\n>> >> +                 If unspecified default values shall be used.\n>> >> +  - nvmem-cell-names: Should be \"calibration-data\"\n>> >\n>> >I'd prefer to have which sensor it applies to here. It wouldn't change\n>> >anything for the H3, but it definitely does for example for the A83t\n>> >that has two sensors, one for each cluster, and one for the GPU, each\n>> >with calibration data.\n>> >\n>> >What about cluster0-calibration?\n\nI prefer sensor0-calibration to sensor3-calibration now.\n(Theortically the new generation THS can support up to 4 sensors)\n\n>> \n>> The calibration data is in fact a 2 word (8 bytes) zone,\n>> which is reserved for 4 sensors on all SoCs, even on H3.\n>> It's half word per sensor.\n>> \n>> I prefer to just assume a 2 word cell for every SoC.\n> \n> You have three different data sources, it should be reprensented as\n> such.\n> \n> Otherwise, the client has to get some knowledge of how the data are\n> stored in the provider, which is an abstraction violation.\n> \n> Maxime\n> \n> --\n> Maxime Ripard, Free Electrons\n> Embedded Linux and Kernel engineering\n> http://free-electrons.com","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"utf-8\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1771655,"web_url":"http://patchwork.ozlabs.org/comment/1771655/","msgid":"<20170920075223.jaeswlhcqgu4yhse@flea.home>","list_archive_url":null,"date":"2017-09-20T07:52:23","subject":"Re: [linux-sunxi] Re: [PATCH v4 1/6] dt-bindings: update the\n\tAllwinner GPADC device tree binding for H3","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Mon, Sep 18, 2017 at 03:47:25PM +0000, icenowy@aosc.io wrote:\n> 在 2017-09-18 16:30，Maxime Ripard 写道：\n> > On Mon, Sep 18, 2017 at 03:36:43PM +0800, Icenowy Zheng wrote:\n> > > 于 2017年9月18日 GMT+08:00 下午3:33:36, Maxime Ripard\n> > > <maxime.ripard@free-electrons.com> 写到:\n> > > >On Thu, Sep 14, 2017 at 10:52:46PM +0800, Icenowy Zheng wrote:\n> > > >> Allwinner H3 features a thermal sensor like the one in A33, but has\n> > > >its\n> > > >> register re-arranged, the clock divider moved to CCU (originally the\n> > > >> clock divider is in ADC) and added a pair of bus clock and reset.\n> > > >>\n> > > >> Update the binding document to cover H3.\n> > > >>\n> > > >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n> > > >> Reviewed-by: Chen-Yu Tsai <wens@csie.org>\n> > > >> ---\n> > > >> Changes in v4:\n> > > >> - Add nvmem calibration data (not yet used by the driver)\n> > > >> Changes in v3:\n> > > >> - Clock name changes.\n> > > >> - Example node name changes.\n> > > >> - Add interupts (not yet used by the driver).\n> > > >>\n> > > >>  .../devicetree/bindings/mfd/sun4i-gpadc.txt        | 30\n> > > >++++++++++++++++++++--\n> > > >>  1 file changed, 28 insertions(+), 2 deletions(-)\n> > > >>\n> > > >> diff --git a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n> > > >b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n> > > >> index badff3611a98..6c470d584bf9 100644\n> > > >> --- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n> > > >> +++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n> > > >> @@ -4,12 +4,26 @@ The Allwinner SoCs all have an ADC that can also\n> > > >act as a thermal sensor\n> > > >>  and sometimes as a touchscreen controller.\n> > > >>\n> > > >>  Required properties:\n> > > >> -  - compatible: \"allwinner,sun8i-a33-ths\",\n> > > >> +  - compatible: must contain one of the following compatibles:\n> > > >> +\t\t- \"allwinner,sun8i-a33-ths\"\n> > > >> +\t\t- \"allwinner,sun8i-h3-ths\"\n> > > >>    - reg: mmio address range of the chip,\n> > > >>    - #thermal-sensor-cells: shall be 0,\n> > > >>    - #io-channel-cells: shall be 0,\n> > > >>\n> > > >> -Example:\n> > > >> +Optional properties:\n> > > >> +  - nvmem-cells: A phandle to the calibration data provided by a\n> > > >nvmem device.\n> > > >> +                 If unspecified default values shall be used.\n> > > >> +  - nvmem-cell-names: Should be \"calibration-data\"\n> > > >\n> > > >I'd prefer to have which sensor it applies to here. It wouldn't change\n> > > >anything for the H3, but it definitely does for example for the A83t\n> > > >that has two sensors, one for each cluster, and one for the GPU, each\n> > > >with calibration data.\n> > > >\n> > > >What about cluster0-calibration?\n> \n> I prefer sensor0-calibration to sensor3-calibration now.\n> (Theortically the new generation THS can support up to 4 sensors)\n\nThe mapping that explains what sensor0 means can change in the\nfuture. It's better to be explicit here, and just say upfront what\nit's about.\n\nMaxime","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"Jnlf4YgN\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxsRd02c4z9s8J\n\tfor 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version=3.4.0","Date":"Wed, 20 Sep 2017 09:52:23 +0200","From":"Maxime Ripard <maxime.ripard@free-electrons.com>","To":"icenowy@aosc.io","Subject":"Re: [linux-sunxi] Re: [PATCH v4 1/6] dt-bindings: update the\n\tAllwinner GPADC device tree binding for H3","Message-ID":"<20170920075223.jaeswlhcqgu4yhse@flea.home>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-2-icenowy@aosc.io>\n\t<20170918073336.j7finend3g76chsu@flea.lan>\n\t<310CE549-B8CE-4C0C-95B1-B545E38BDAF5@aosc.io>\n\t<20170918083045.7bfiialtbm7w6i7j@flea.lan>\n\t<e73ead447af89031749e85207cac1e69@aosc.io>","MIME-Version":"1.0","In-Reply-To":"<e73ead447af89031749e85207cac1e69@aosc.io>","User-Agent":"NeoMutt/20170914 (1.9.0)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170920_005247_014829_6E68613D ","X-CRM114-Status":"GOOD (  22.12  )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-1.9 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"devicetree@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,\n\tQuentin Schulz <quentin.schulz@free-electrons.com>,\n\tChen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>,\n\tlinux-arm-kernel@lists.infradead.org, Lee Jones <lee.jones@linaro.org>,\n\tJonathan Cameron <jic23@kernel.org>","Content-Type":"multipart/mixed;\n\tboundary=\"===============4908576174277191738==\"","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1771660,"web_url":"http://patchwork.ozlabs.org/comment/1771660/","msgid":"<27449039-F0D4-4663-B596-C95D4408D471@aosc.io>","list_archive_url":null,"date":"2017-09-20T08:04:02","subject":"Re: [linux-sunxi] Re: [PATCH v4 1/6] dt-bindings: update the\n\tAllwinner GPADC device tree binding for H3","submitter":{"id":71295,"url":"http://patchwork.ozlabs.org/api/people/71295/","name":"Icenowy Zheng","email":"icenowy@aosc.io"},"content":"于 2017年9月20日 GMT+08:00 下午3:52:23, Maxime Ripard <maxime.ripard@free-electrons.com> 写到:\n>On Mon, Sep 18, 2017 at 03:47:25PM +0000, icenowy@aosc.io wrote:\n>> 在 2017-09-18 16:30，Maxime Ripard 写道：\n>> > On Mon, Sep 18, 2017 at 03:36:43PM +0800, Icenowy Zheng wrote:\n>> > > 于 2017年9月18日 GMT+08:00 下午3:33:36, Maxime Ripard\n>> > > <maxime.ripard@free-electrons.com> 写到:\n>> > > >On Thu, Sep 14, 2017 at 10:52:46PM +0800, Icenowy Zheng wrote:\n>> > > >> Allwinner H3 features a thermal sensor like the one in A33,\n>but has\n>> > > >its\n>> > > >> register re-arranged, the clock divider moved to CCU\n>(originally the\n>> > > >> clock divider is in ADC) and added a pair of bus clock and\n>reset.\n>> > > >>\n>> > > >> Update the binding document to cover H3.\n>> > > >>\n>> > > >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n>> > > >> Reviewed-by: Chen-Yu Tsai <wens@csie.org>\n>> > > >> ---\n>> > > >> Changes in v4:\n>> > > >> - Add nvmem calibration data (not yet used by the driver)\n>> > > >> Changes in v3:\n>> > > >> - Clock name changes.\n>> > > >> - Example node name changes.\n>> > > >> - Add interupts (not yet used by the driver).\n>> > > >>\n>> > > >>  .../devicetree/bindings/mfd/sun4i-gpadc.txt        | 30\n>> > > >++++++++++++++++++++--\n>> > > >>  1 file changed, 28 insertions(+), 2 deletions(-)\n>> > > >>\n>> > > >> diff --git\n>a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n>> > > >b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n>> > > >> index badff3611a98..6c470d584bf9 100644\n>> > > >> --- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n>> > > >> +++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n>> > > >> @@ -4,12 +4,26 @@ The Allwinner SoCs all have an ADC that can\n>also\n>> > > >act as a thermal sensor\n>> > > >>  and sometimes as a touchscreen controller.\n>> > > >>\n>> > > >>  Required properties:\n>> > > >> -  - compatible: \"allwinner,sun8i-a33-ths\",\n>> > > >> +  - compatible: must contain one of the following\n>compatibles:\n>> > > >> +\t\t- \"allwinner,sun8i-a33-ths\"\n>> > > >> +\t\t- \"allwinner,sun8i-h3-ths\"\n>> > > >>    - reg: mmio address range of the chip,\n>> > > >>    - #thermal-sensor-cells: shall be 0,\n>> > > >>    - #io-channel-cells: shall be 0,\n>> > > >>\n>> > > >> -Example:\n>> > > >> +Optional properties:\n>> > > >> +  - nvmem-cells: A phandle to the calibration data provided\n>by a\n>> > > >nvmem device.\n>> > > >> +                 If unspecified default values shall be used.\n>> > > >> +  - nvmem-cell-names: Should be \"calibration-data\"\n>> > > >\n>> > > >I'd prefer to have which sensor it applies to here. It wouldn't\n>change\n>> > > >anything for the H3, but it definitely does for example for the\n>A83t\n>> > > >that has two sensors, one for each cluster, and one for the GPU,\n>each\n>> > > >with calibration data.\n>> > > >\n>> > > >What about cluster0-calibration?\n>> \n>> I prefer sensor0-calibration to sensor3-calibration now.\n>> (Theortically the new generation THS can support up to 4 sensors)\n>\n>The mapping that explains what sensor0 means can change in the\n>future. It's better to be explicit here, and just say upfront what\n>it's about.\n\nI think for some SoC (e.g. A64) there's no clear explain on\nthe functions of the sensors.\n\nIn addition, in the THS controller the sensors has a\nexplicit sequence, and when referencing it in the DT\nthe number is still needed (in thermal zones).\n\n>\n>Maxime","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"lZuTJxVd\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxsjf0W8kz9s8J\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tWed, 20 Sep 2017 18:05:07 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dua0F-0005YP-3d; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1773187,"web_url":"http://patchwork.ozlabs.org/comment/1773187/","msgid":"<20170921193211.pjsikkez5by46mfh@flea>","list_archive_url":null,"date":"2017-09-21T19:32:11","subject":"Re: [linux-sunxi] Re: [PATCH v4 1/6] dt-bindings: update the\n\tAllwinner GPADC device tree binding for H3","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Wed, Sep 20, 2017 at 08:04:02AM +0000, Icenowy Zheng wrote:\n> 于 2017年9月20日 GMT+08:00 下午3:52:23, Maxime Ripard <maxime.ripard@free-electrons.com> 写到:\n> >On Mon, Sep 18, 2017 at 03:47:25PM +0000, icenowy@aosc.io wrote:\n> >> 在 2017-09-18 16:30，Maxime Ripard 写道：\n> >> > On Mon, Sep 18, 2017 at 03:36:43PM +0800, Icenowy Zheng wrote:\n> >> > > 于 2017年9月18日 GMT+08:00 下午3:33:36, Maxime Ripard\n> >> > > <maxime.ripard@free-electrons.com> 写到:\n> >> > > >On Thu, Sep 14, 2017 at 10:52:46PM +0800, Icenowy Zheng wrote:\n> >> > > >> Allwinner H3 features a thermal sensor like the one in A33,\n> >but has\n> >> > > >its\n> >> > > >> register re-arranged, the clock divider moved to CCU\n> >(originally the\n> >> > > >> clock divider is in ADC) and added a pair of bus clock and\n> >reset.\n> >> > > >>\n> >> > > >> Update the binding document to cover H3.\n> >> > > >>\n> >> > > >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n> >> > > >> Reviewed-by: Chen-Yu Tsai <wens@csie.org>\n> >> > > >> ---\n> >> > > >> Changes in v4:\n> >> > > >> - Add nvmem calibration data (not yet used by the driver)\n> >> > > >> Changes in v3:\n> >> > > >> - Clock name changes.\n> >> > > >> - Example node name changes.\n> >> > > >> - Add interupts (not yet used by the driver).\n> >> > > >>\n> >> > > >>  .../devicetree/bindings/mfd/sun4i-gpadc.txt        | 30\n> >> > > >++++++++++++++++++++--\n> >> > > >>  1 file changed, 28 insertions(+), 2 deletions(-)\n> >> > > >>\n> >> > > >> diff --git\n> >a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n> >> > > >b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n> >> > > >> index badff3611a98..6c470d584bf9 100644\n> >> > > >> --- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n> >> > > >> +++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt\n> >> > > >> @@ -4,12 +4,26 @@ The Allwinner SoCs all have an ADC that can\n> >also\n> >> > > >act as a thermal sensor\n> >> > > >>  and sometimes as a touchscreen controller.\n> >> > > >>\n> >> > > >>  Required properties:\n> >> > > >> -  - compatible: \"allwinner,sun8i-a33-ths\",\n> >> > > >> +  - compatible: must contain one of the following\n> >compatibles:\n> >> > > >> +\t\t- \"allwinner,sun8i-a33-ths\"\n> >> > > >> +\t\t- \"allwinner,sun8i-h3-ths\"\n> >> > > >>    - reg: mmio address range of the chip,\n> >> > > >>    - #thermal-sensor-cells: shall be 0,\n> >> > > >>    - #io-channel-cells: shall be 0,\n> >> > > >>\n> >> > > >> -Example:\n> >> > > >> +Optional properties:\n> >> > > >> +  - nvmem-cells: A phandle to the calibration data provided\n> >by a\n> >> > > >nvmem device.\n> >> > > >> +                 If unspecified default values shall be used.\n> >> > > >> +  - nvmem-cell-names: Should be \"calibration-data\"\n> >> > > >\n> >> > > >I'd prefer to have which sensor it applies to here. It wouldn't\n> >change\n> >> > > >anything for the H3, but it definitely does for example for the\n> >A83t\n> >> > > >that has two sensors, one for each cluster, and one for the GPU,\n> >each\n> >> > > >with calibration data.\n> >> > > >\n> >> > > >What about cluster0-calibration?\n> >> \n> >> I prefer sensor0-calibration to sensor3-calibration now.\n> >> (Theortically the new generation THS can support up to 4 sensors)\n> >\n> >The mapping that explains what sensor0 means can change in the\n> >future. It's better to be explicit here, and just say upfront what\n> >it's about.\n> \n> I think for some SoC (e.g. A64) there's no clear explain on\n> the functions of the sensors.\n\nIt's documented in the user manual (\"sensor0 located in the CPU, sensor1 and\nsensor2 located in the GPU\"\n\n> In addition, in the THS controller the sensors has a explicit\n> sequence, and when referencing it in the DT the number is still\n> needed (in thermal zones).\n\nYes, but that's something that can be made easier through defines too.\n\nMaxime","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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version=3.4.0","Date":"Thu, 21 Sep 2017 21:32:11 +0200","From":"Maxime Ripard <maxime.ripard@free-electrons.com>","To":"Icenowy Zheng <icenowy@aosc.io>","Subject":"Re: [linux-sunxi] Re: [PATCH v4 1/6] dt-bindings: update the\n\tAllwinner GPADC device tree binding for H3","Message-ID":"<20170921193211.pjsikkez5by46mfh@flea>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-2-icenowy@aosc.io>\n\t<20170918073336.j7finend3g76chsu@flea.lan>\n\t<310CE549-B8CE-4C0C-95B1-B545E38BDAF5@aosc.io>\n\t<20170918083045.7bfiialtbm7w6i7j@flea.lan>\n\t<e73ead447af89031749e85207cac1e69@aosc.io>\n\t<20170920075223.jaeswlhcqgu4yhse@flea.home>\n\t<27449039-F0D4-4663-B596-C95D4408D471@aosc.io>","MIME-Version":"1.0","In-Reply-To":"<27449039-F0D4-4663-B596-C95D4408D471@aosc.io>","User-Agent":"NeoMutt/20170914 (1.9.0)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170921_123241_301465_BA125D17 ","X-CRM114-Status":"GOOD (  24.36  )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-1.9 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"devicetree@vger.kernel.org, linux-iio@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,\n\tQuentin Schulz <quentin.schulz@free-electrons.com>,\n\tChen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>,\n\tlinux-arm-kernel@lists.infradead.org, Lee Jones <lee.jones@linaro.org>,\n\tJonathan Cameron <jic23@kernel.org>","Content-Type":"multipart/mixed;\n\tboundary=\"===============6180443770884912552==\"","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1774214,"web_url":"http://patchwork.ozlabs.org/comment/1774214/","msgid":"<20170924152304.02551715@archlinux>","list_archive_url":null,"date":"2017-09-24T14:23:04","subject":"Re: [PATCH v4 6/6] ARM: sun8i: h3: add partial CPU thermal zone","submitter":{"id":10151,"url":"http://patchwork.ozlabs.org/api/people/10151/","name":"Jonathan Cameron","email":"jic23@kernel.org"},"content":"On Mon, 18 Sep 2017 10:27:03 +0200\nMaxime Ripard <maxime.ripard@free-electrons.com> wrote:\n\n> Hi Jonathan,\n> \n> On Sat, Sep 16, 2017 at 03:17:34PM -0700, Jonathan Cameron wrote:\n> > On Sat, 16 Sep 2017 12:05:49 +0200\n> > Quentin Schulz <quentin.schulz@free-electrons.com> wrote:\n> >   \n> > > Hi Icenowy,\n> > > \n> > > On 14/09/2017 16:52, Icenowy Zheng wrote:  \n> > > > Because of the restriction of the OF thermal framework, the thermal\n> > > > sensor will fail to probe if the thermal zone doesn't exist.\n> > > >     \n> > > \n> > > Oh no, that's not good.\n> > > \n> > > We discussed about it on IRC and I even proposed a patch for it, telling\n> > > you I would post it on the mailing list soon after. Of course, I forgot\n> > > and you definitely should have yelled at me for not doing it :)\n> > > \n> > > I won't be able to test the patch soon. I can send it to you so that you\n> > > can test it and integrate it in your patch series so it won't block you.\n> > > Otherwise, we'll have to wait for a week or two for me to test it.\n> > > \n> > > Thanks and sorry for forgetting to post the patch you need,\n> > > Quentin  \n> > \n> > Other this outstanding issue I'm happy with the series, so hopefully\n> > with Quentin's patch added we should be good to merge this one.  \n> \n> We will at least need a v5.\n> \n> Maxime\n> \nSure - I can see other issues are coming out of the woodwork!\n\nThanks,\n\nJonathan","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=7muxYxsUQlNwQWeEj1hPtnR6fMABOvpi+lxUtw1WCKg=;\n\tb=GBO2LP0a52k+zA\n\tIikdqIrpMY8WXl8qTwJvkV5ALKsOhDTmcqpguLorl0GLjadMw6BATqOzwErWjsyquhBJJSZ4KuPUn\n\tpj1RafG0SDX+20h4wwY7+sX9EN2RcwxMuq+MKFdynUb8xFes/clhKoaO3llI86A01lV/B5vgOMasX\n\t1Q1EFYb/Zy8m25iKNvf2+2zVmuIfJvsyfbnRNPMZLDDwj8BovfgFrUccUzlca1RodmCMP10MVgor1\n\tBmqOv6uMITQICSV0LgHogeQTaS8Ei5cPQAqdxRa/p6s0mARdATPW64w9q5d77rMSWzbgMIdtoEX8K\n\tvkEGXulfeiAX3vFyIFbg==;","DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org 16BCB217C3","Date":"Sun, 24 Sep 2017 15:23:04 +0100","From":"Jonathan Cameron <jic23@kernel.org>","To":"Maxime Ripard <maxime.ripard@free-electrons.com>","Subject":"Re: [PATCH v4 6/6] ARM: sun8i: h3: add partial CPU thermal zone","Message-ID":"<20170924152304.02551715@archlinux>","In-Reply-To":"<20170918082703.riqntqilakzhirc5@flea.lan>","References":"<20170914145251.21784-1-icenowy@aosc.io>\n\t<20170914145251.21784-7-icenowy@aosc.io>\n\t<b41a80ec-23d5-a614-f6cc-d09c5a459e03@free-electrons.com>\n\t<20170916151734.10968b7a@archlinux>\n\t<20170918082703.riqntqilakzhirc5@flea.lan>","X-Mailer":"Claws Mail 3.15.1-dirty (GTK+ 2.24.31; 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