[{"id":1769446,"web_url":"http://patchwork.ozlabs.org/comment/1769446/","msgid":"<20170915210347.GA1831@mai>","list_archive_url":null,"date":"2017-09-15T21:03:47","subject":"Re: [PATCH 2/2] arm: dts: stm32: remove useless clocksource nodes","submitter":{"id":13265,"url":"http://patchwork.ozlabs.org/api/people/13265/","name":"Daniel Lezcano","email":"daniel.lezcano@linaro.org"},"content":"On Thu, Sep 14, 2017 at 09:56:52AM +0200, Benjamin Gaignard wrote:\n> 16 bits timers aren't accurate enough to be used as\n> clocksource, remove them from stm32f4 and stm32f7 devicetree.\n\nDo you really want to remove the description? The timers are disabled, aren't they?","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"bt+BwFDH\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"bDN0Pzu3\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xv7Dz2v7Hz9s3w\n\tfor ;\n\tSat, 16 Sep 2017 07:04:19 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dsxma-0008RO-45; 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\n\tFri, 15 Sep 2017 14:03:51 -0700 (PDT)","Date":"Fri, 15 Sep 2017 23:03:47 +0200","From":"Daniel Lezcano ","To":"Benjamin Gaignard ","Subject":"Re: [PATCH 2/2] arm: dts: stm32: remove useless clocksource nodes","Message-ID":"<20170915210347.GA1831@mai>","References":"<1505375812-19037-1-git-send-email-benjamin.gaignard@linaro.org>\n\t<1505375812-19037-3-git-send-email-benjamin.gaignard@linaro.org>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<1505375812-19037-3-git-send-email-benjamin.gaignard@linaro.org>","User-Agent":"Mutt/1.5.24 (2015-08-30)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170915_140413_053819_A76B3242 ","X-CRM114-Status":"UNSURE ( 9.12 )","X-CRM114-Notice":"Please train this message.","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2607:f8b0:400e:c00:0:0:0:230 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, devicetree@vger.kernel.org, alexandre.torgue@st.com,\n\tlinux@armlinux.org.uk, linux-kernel@vger.kernel.org, robh+dt@kernel.org, \n\tlinux-arm-kernel@lists.infradead.org, mcoquelin.stm32@gmail.com,\n\ttglx@linutronix.de, ludovic.barre@st.com","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1769708,"web_url":"http://patchwork.ozlabs.org/comment/1769708/","msgid":"","list_archive_url":null,"date":"2017-09-17T13:34:23","subject":"Re: [PATCH 2/2] arm: dts: stm32: remove useless clocksource nodes","submitter":{"id":66874,"url":"http://patchwork.ozlabs.org/api/people/66874/","name":"Benjamin Gaignard","email":"benjamin.gaignard@linaro.org"},"content":"2017-09-15 23:03 GMT+02:00 Daniel Lezcano :\n> On Thu, Sep 14, 2017 at 09:56:52AM +0200, Benjamin Gaignard wrote:\n>> 16 bits timers aren't accurate enough to be used as\n>> clocksource, remove them from stm32f4 and stm32f7 devicetree.\n>\n> Do you really want to remove the description? The timers are disabled, aren't they?\n\nYes because they are 16 bits timers and they won't be accepted anymore in\ndriver's probe function.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"KGF9L1Ch\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"MQMYhv3K\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xw99Y63VXz9s81\n\tfor ;\n\tSun, 17 Sep 2017 23:34:57 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dtZio-0008Tl-7n; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1770534,"web_url":"http://patchwork.ozlabs.org/comment/1770534/","msgid":"<9e5cae53-0a57-f2e9-cbb1-dde484619fca@linaro.org>","list_archive_url":null,"date":"2017-09-18T21:30:41","subject":"Re: [PATCH 1/2] clocksource: stm32: rework driver to use only one\n\ttimer","submitter":{"id":13265,"url":"http://patchwork.ozlabs.org/api/people/13265/","name":"Daniel Lezcano","email":"daniel.lezcano@linaro.org"},"content":"On 14/09/2017 09:56, Benjamin Gaignard wrote:\n> Rework driver code to use only one timer for both clocksource\n> and clockevent.\n> This patch also forbids to use 16 bits timers because they are\n> not enough accurate.\n> Do some clean up in structures and functions names too.\n> \n> Signed-off-by: Ludovic Barre \n> Signed-off-by: Benjamin Gaignard \n\nHi Benjamin,\n\nI have a few comments below. Can you when reposting split this patch\ninto smaller changes ?\n\nAlso, can you consider using the timer-of API ?\n\nThanks.\n\n -- Daniel\n\n> ---\n> drivers/clocksource/timer-stm32.c | 259 +++++++++++++++++++++++---------------\n> 1 file changed, 155 insertions(+), 104 deletions(-)\n> \n> diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c\n> index 8f24237..648c10a 100644\n> --- a/drivers/clocksource/timer-stm32.c\n> +++ b/drivers/clocksource/timer-stm32.c\n> @@ -16,175 +16,226 @@\n> #include \n> #include \n> #include \n> +#include \n> +#include \n> \n> #define TIM_CR1\t\t0x00\n> #define TIM_DIER\t0x0c\n> #define TIM_SR\t\t0x10\n> #define TIM_EGR\t\t0x14\n> +#define TIM_CNT\t\t0x24\n> #define TIM_PSC\t\t0x28\n> #define TIM_ARR\t\t0x2c\n> +#define TIM_CCR1\t0x34\n> \n> #define TIM_CR1_CEN\tBIT(0)\n> -#define TIM_CR1_OPM\tBIT(3)\n> +#define TIM_CR1_UDIS\tBIT(1)\n> #define TIM_CR1_ARPE\tBIT(7)\n> \n> -#define TIM_DIER_UIE\tBIT(0)\n> -\n> -#define TIM_SR_UIF\tBIT(0)\n> +#define TIM_DIER_CC1IE\tBIT(1)\n> \n> #define TIM_EGR_UG\tBIT(0)\n> \n> -struct stm32_clock_event_ddata {\n> +struct stm32_clock_event {\n> \tstruct clock_event_device evtdev;\n> \tunsigned periodic_top;\n> -\tvoid __iomem *base;\n> +\tvoid __iomem *regs;\n> };\n> \n> static int stm32_clock_event_shutdown(struct clock_event_device *evtdev)\n> {\n> -\tstruct stm32_clock_event_ddata *data =\n> -\t\tcontainer_of(evtdev, struct stm32_clock_event_ddata, evtdev);\n> -\tvoid *base = data->base;\n> +\tstruct stm32_clock_event *ce =\n> +\t\tcontainer_of(evtdev, struct stm32_clock_event, evtdev);\n> +\n> +\twritel_relaxed(0, ce->regs + TIM_DIER);\n> \n> -\twritel_relaxed(0, base + TIM_CR1);\n\nWhy this change? TIM_CR1 -> TIM_DIER? A 16b to 32b change?\n\n> \treturn 0;\n> }\n> \n> -static int stm32_clock_event_set_periodic(struct clock_event_device *evtdev)\n> +static int stm32_clock_event_set_next_event(unsigned long evt,\n> +\t\t\t\t\t struct clock_event_device *evtdev)\n> {\n> -\tstruct stm32_clock_event_ddata *data =\n> -\t\tcontainer_of(evtdev, struct stm32_clock_event_ddata, evtdev);\n> -\tvoid *base = data->base;\n> +\tstruct stm32_clock_event *ce =\n> +\t\tcontainer_of(evtdev, struct stm32_clock_event, evtdev);\n> +\tunsigned long cnt;\n> +\n> +\tcnt = readl_relaxed(ce->regs + TIM_CNT);\n> +\twritel_relaxed(cnt + evt, ce->regs + TIM_CCR1);\n> +\twritel_relaxed(TIM_DIER_CC1IE, ce->regs + TIM_DIER);\n> \n> -\twritel_relaxed(data->periodic_top, base + TIM_ARR);\n> -\twritel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, base + TIM_CR1);\n> \treturn 0;\n> }\n> \n> -static int stm32_clock_event_set_next_event(unsigned long evt,\n> -\t\t\t\t\t struct clock_event_device *evtdev)\n> +static int stm32_clock_event_set_periodic(struct clock_event_device *evtdev)\n> {\n> -\tstruct stm32_clock_event_ddata *data =\n> -\t\tcontainer_of(evtdev, struct stm32_clock_event_ddata, evtdev);\n> +\tstruct stm32_clock_event *ce =\n> +\t\tcontainer_of(evtdev, struct stm32_clock_event, evtdev);\n> \n> -\twritel_relaxed(evt, data->base + TIM_ARR);\n> -\twritel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN,\n> -\t\t data->base + TIM_CR1);\n> +\treturn stm32_clock_event_set_next_event(ce->periodic_top, evtdev);\n> +}\n> \n> -\treturn 0;\n> +static int stm32_clock_event_set_oneshot(struct clock_event_device *evtdev)\n> +{\n> +\treturn stm32_clock_event_set_next_event(0, evtdev);\n> }\n> \n> static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id)\n> {\n> -\tstruct stm32_clock_event_ddata *data = dev_id;\n> +\tstruct stm32_clock_event *ce = dev_id;\n> +\n> +\twritel_relaxed(0, ce->regs + TIM_SR);\n> \n> -\twritel_relaxed(0, data->base + TIM_SR);\n> +\tif (clockevent_state_periodic(&ce->evtdev))\n> +\t\tstm32_clock_event_set_periodic(&ce->evtdev);\n\nnit: else condition to prevent an extra check\n\n> -\tdata->evtdev.event_handler(&data->evtdev);\n> +\tif (clockevent_state_oneshot(&ce->evtdev))\n> +\t\tstm32_clock_event_shutdown(&ce->evtdev);\n> +\n> +\tce->evtdev.event_handler(&ce->evtdev);\n> \n> \treturn IRQ_HANDLED;\n> }\n> \n> -static struct stm32_clock_event_ddata clock_event_ddata = {\n> -\t.evtdev = {\n> -\t\t.name = \"stm32 clockevent\",\n> -\t\t.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,\n> -\t\t.set_state_shutdown = stm32_clock_event_shutdown,\n> -\t\t.set_state_periodic = stm32_clock_event_set_periodic,\n> -\t\t.set_state_oneshot = stm32_clock_event_shutdown,\n> -\t\t.tick_resume = stm32_clock_event_shutdown,\n> -\t\t.set_next_event = stm32_clock_event_set_next_event,\n> -\t\t.rating = 200,\n> -\t},\n> -};\n> +static int __init stm32_clockevent_init(struct device_node *np,\n> +\t\t\t\t\tvoid __iomem *base,\n> +\t\t\t\t\tstruct clk *clk, int irq)\n> +{\n> +\tstruct stm32_clock_event *ce;\n> +\tunsigned long rate;\n> +\tint err;\n> +\n> +\tce = kzalloc(sizeof(*ce), GFP_KERNEL);\n> +\tif (!ce)\n> +\t\treturn -ENOMEM;\n> +\n> +\tce->regs = base;\n> +\tce->evtdev.name = \"stm32_clockevent\";\n> +\tce->evtdev.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC;\n> +\tce->evtdev.set_state_shutdown = stm32_clock_event_shutdown;\n> +\tce->evtdev.set_state_periodic = stm32_clock_event_set_periodic;\n> +\tce->evtdev.set_state_oneshot = stm32_clock_event_set_oneshot;\n> +\tce->evtdev.tick_resume = stm32_clock_event_shutdown;\n> +\tce->evtdev.set_next_event = stm32_clock_event_set_next_event;\n> +\tce->evtdev.rating = 200;\n> \n> -static int __init stm32_clockevent_init(struct device_node *np)\n> +\trate = clk_get_rate(clk);\n> +\tce->periodic_top = DIV_ROUND_CLOSEST(rate, HZ);\n> +\n> +\twritel_relaxed(0, ce->regs + TIM_DIER);\n> +\twritel_relaxed(0, ce->regs + TIM_SR);\n> +\n> +\terr = request_irq(irq, stm32_clock_event_handler, IRQF_TIMER,\n> +\t\t\t \"stm32 clockevent\", ce);\n> +\tif (err) {\n> +\t\tkfree(ce);\n> +\t\treturn err;\n> +\t}\n> +\n> +\tclockevents_config_and_register(&ce->evtdev, rate, 0x60, ~0U);\n> +\n> +\treturn 0;\n> +}\n> +\n> +static void __iomem *stm32_timer_cnt __read_mostly;\n> +static u64 notrace stm32_read_sched_clock(void)\n> +{\n> +\treturn readl_relaxed(stm32_timer_cnt);\n> +}\n> +\n> +static int __init stm32_clocksource_init(struct device_node *node,\n> +\t\t\t\t\t void __iomem *regs,\n> +\t\t\t\t\t struct clk *clk)\n> +{\n> +\tunsigned long rate;\n> +\n> +\trate = clk_get_rate(clk);\n> +\n> +\twritel_relaxed(~0U, regs + TIM_ARR);\n> +\twritel_relaxed(0, regs + TIM_PSC);\n> +\twritel_relaxed(0, regs + TIM_SR);\n> +\twritel_relaxed(0, regs + TIM_DIER);\n> +\twritel_relaxed(0, regs + TIM_SR);\n> +\twritel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS, regs + TIM_CR1);\n> +\n> +\t/* Make sure that registers are updated */\n> +\twritel_relaxed(TIM_EGR_UG, regs + TIM_EGR);\n> +\n> +\t/* Enable controller */\n> +\twritel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS | TIM_CR1_CEN,\n> +\t\t regs + TIM_CR1);\n> +\n> +\tstm32_timer_cnt = regs + TIM_CNT;\n> +\tsched_clock_register(stm32_read_sched_clock, 32, rate);\n> +\n> +\treturn clocksource_mmio_init(stm32_timer_cnt, \"stm32_timer\",\n> +\t\t\t\t rate, 250, 32, clocksource_mmio_readl_up);\n> +}\n> +\n> +static int __init stm32_timer_init(struct device_node *node)\n> {\n> -\tstruct stm32_clock_event_ddata *data = &clock_event_ddata;\n> -\tstruct clk *clk;\n> \tstruct reset_control *rstc;\n> -\tunsigned long rate, max_delta;\n> -\tint irq, ret, bits, prescaler = 1;\n> +\tvoid __iomem *timer_base;\n> +\tunsigned long max_arr;\n> +\tstruct clk *clk;\n> +\tint irq, err;\n> \n> -\tclk = of_clk_get(np, 0);\n> -\tif (IS_ERR(clk)) {\n> -\t\tret = PTR_ERR(clk);\n> -\t\tpr_err(\"failed to get clock for clockevent (%d)\\n\", ret);\n> -\t\tgoto err_clk_get;\n> +\ttimer_base = of_io_request_and_map(node, 0, of_node_full_name(node));\n> +\tif (IS_ERR(timer_base)) {\n> +\t\tpr_err(\"Can't map registers\\n\");\n> +\t\tgoto out;\n> \t}\n> \n> -\tret = clk_prepare_enable(clk);\n> -\tif (ret) {\n> -\t\tpr_err(\"failed to enable timer clock for clockevent (%d)\\n\",\n> -\t\t ret);\n> -\t\tgoto err_clk_enable;\n> +\tirq = irq_of_parse_and_map(node, 0);\n> +\tif (irq <= 0) {\n> +\t\tpr_err(\"Can't parse IRQ\\n\");\n> +\t\tgoto out_unmap;\n> \t}\n> \n> -\trate = clk_get_rate(clk);\n\nWhy not pass the rate to clkevt_init and clksrc_init instead of clk? So\nclk_get_rate() is not called twice.\n\n> +\tclk = of_clk_get(node, 0);\n> +\tif (IS_ERR(clk)) {\n> +\t\tpr_err(\"Can't get timer clock\\n\");\n> +\t\tgoto out_unmap;\n> +\t}\n> \n> -\trstc = of_reset_control_get(np, NULL);\n> +\trstc = of_reset_control_get(node, NULL);\n> \tif (!IS_ERR(rstc)) {\n> \t\treset_control_assert(rstc);\n> \t\treset_control_deassert(rstc);\n> \t}\n> \n> -\tdata->base = of_iomap(np, 0);\n> -\tif (!data->base) {\n> -\t\tret = -ENXIO;\n> -\t\tpr_err(\"failed to map registers for clockevent\\n\");\n> -\t\tgoto err_iomap;\n> -\t}\n> -\n> -\tirq = irq_of_parse_and_map(np, 0);\n> -\tif (!irq) {\n> -\t\tret = -EINVAL;\n> -\t\tpr_err(\"%pOF: failed to get irq.\\n\", np);\n> -\t\tgoto err_get_irq;\n> +\terr = clk_prepare_enable(clk);\n> +\tif (err) {\n> +\t\tpr_err(\"Couldn't enable parent clock\\n\");\n> +\t\tgoto out_clk;\n> \t}\n> \n> \t/* Detect whether the timer is 16 or 32 bits */\n> -\twritel_relaxed(~0U, data->base + TIM_ARR);\n> -\tmax_delta = readl_relaxed(data->base + TIM_ARR);\n> -\tif (max_delta == ~0U) {\n> -\t\tprescaler = 1;\n> -\t\tbits = 32;\n> -\t} else {\n> -\t\tprescaler = 1024;\n> -\t\tbits = 16;\n> +\twritel_relaxed(~0U, timer_base + TIM_ARR);\n> +\tmax_arr = readl_relaxed(timer_base + TIM_ARR);\n> +\tif (max_arr != ~0U) {\n> +\t\terr = -EINVAL;\n> +\t\tpr_err(\"32 bits timer is needed\\n\");\n> +\t\tgoto out_unprepare;\n> \t}\n> -\twritel_relaxed(0, data->base + TIM_ARR);\n> -\n> -\twritel_relaxed(prescaler - 1, data->base + TIM_PSC);\n> -\twritel_relaxed(TIM_EGR_UG, data->base + TIM_EGR);\n> -\twritel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER);\n> -\twritel_relaxed(0, data->base + TIM_SR);\n> -\n> -\tdata->periodic_top = DIV_ROUND_CLOSEST(rate, prescaler * HZ);\n> \n> -\tclockevents_config_and_register(&data->evtdev,\n> -\t\t\t\t\tDIV_ROUND_CLOSEST(rate, prescaler),\n> -\t\t\t\t\t0x1, max_delta);\n> +\terr = stm32_clocksource_init(node, timer_base, clk);\n> +\tif (err)\n> +\t\tgoto out_unprepare;\n> \n> -\tret = request_irq(irq, stm32_clock_event_handler, IRQF_TIMER,\n> -\t\t\t\"stm32 clockevent\", data);\n> -\tif (ret) {\n> -\t\tpr_err(\"%pOF: failed to request irq.\\n\", np);\n> -\t\tgoto err_get_irq;\n> -\t}\n> -\n> -\tpr_info(\"%pOF: STM32 clockevent driver initialized (%d bits)\\n\",\n> -\t\t\tnp, bits);\n> +\terr = stm32_clockevent_init(node, timer_base, clk, irq);\n> +\tif (err)\n> +\t\tgoto out_unprepare;\n> \n> -\treturn ret;\n> +\treturn 0;\n> \n> -err_get_irq:\n> -\tiounmap(data->base);\n> -err_iomap:\n> +out_unprepare:\n> \tclk_disable_unprepare(clk);\n> -err_clk_enable:\n> +out_clk:\n> \tclk_put(clk);\n> -err_clk_get:\n> -\treturn ret;\n> +out_unmap:\n> +\tiounmap(timer_base);\n> +out:\n> +\treturn err;\n> }\n> \n> -TIMER_OF_DECLARE(stm32, \"st,stm32-timer\", stm32_clockevent_init);\n> +CLOCKSOURCE_OF_DECLARE(stm32, \"st,stm32-timer\", stm32_timer_init);\n\nCLOCKSOURCE_OF_DECLARE is deprecated, keep using TIMER_OF_DECLARE.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"PUgdpeSW\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"YxXKWRkf\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xx0CY3jsJz9s7G\n\tfor ;\n\tTue, 19 Sep 2017 07:54:33 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1du3zr-0001ba-Be; Mon, 18 Sep 2017 21:54:31 +0000","from mail-pg0-x232.google.com ([2607:f8b0:400e:c05::232])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1du3dA-0001OA-UO for linux-arm-kernel@lists.infradead.org;\n\tMon, 18 Sep 2017 21:31:12 +0000","by mail-pg0-x232.google.com with SMTP id 188so864060pgb.2\n\tfor ;\n\tMon, 18 Sep 2017 14:30:43 -0700 (PDT)","from [192.168.0.5] (cpe-66-75-63-57.san.res.rr.com. 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1770718,"web_url":"http://patchwork.ozlabs.org/comment/1770718/","msgid":"","list_archive_url":null,"date":"2017-09-19T07:59:03","subject":"Re: [PATCH 1/2] clocksource: stm32: rework driver to use only one\n\ttimer","submitter":{"id":66874,"url":"http://patchwork.ozlabs.org/api/people/66874/","name":"Benjamin Gaignard","email":"benjamin.gaignard@linaro.org"},"content":"2017-09-18 23:30 GMT+02:00 Daniel Lezcano :\n> On 14/09/2017 09:56, Benjamin Gaignard wrote:\n>> Rework driver code to use only one timer for both clocksource\n>> and clockevent.\n>> This patch also forbids to use 16 bits timers because they are\n>> not enough accurate.\n>> Do some clean up in structures and functions names too.\n>>\n>> Signed-off-by: Ludovic Barre \n>> Signed-off-by: Benjamin Gaignard \n>\n> Hi Benjamin,\n>\n> I have a few comments below. Can you when reposting split this patch\n> into smaller changes ?\n\nNot so easy because I change the way of how the hardware is used to be able\nto provide clocksource and clockevent on the same hardware block.\n\n>\n> Also, can you consider using the timer-of API ?\n\nIs it just about using TIMER_OF_DECLARE ? or do you have something\nelse in mind ?\n\n>\n> Thanks.\n>\n> -- Daniel\n>\n>> ---\n>> drivers/clocksource/timer-stm32.c | 259 +++++++++++++++++++++++---------------\n>> 1 file changed, 155 insertions(+), 104 deletions(-)\n>>\n>> diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c\n>> index 8f24237..648c10a 100644\n>> --- a/drivers/clocksource/timer-stm32.c\n>> +++ b/drivers/clocksource/timer-stm32.c\n>> @@ -16,175 +16,226 @@\n>> #include \n>> #include \n>> #include \n>> +#include \n>> +#include \n>>\n>> #define TIM_CR1 0x00\n>> #define TIM_DIER 0x0c\n>> #define TIM_SR 0x10\n>> #define TIM_EGR 0x14\n>> +#define TIM_CNT 0x24\n>> #define TIM_PSC 0x28\n>> #define TIM_ARR 0x2c\n>> +#define TIM_CCR1 0x34\n>>\n>> #define TIM_CR1_CEN BIT(0)\n>> -#define TIM_CR1_OPM BIT(3)\n>> +#define TIM_CR1_UDIS BIT(1)\n>> #define TIM_CR1_ARPE BIT(7)\n>>\n>> -#define TIM_DIER_UIE BIT(0)\n>> -\n>> -#define TIM_SR_UIF BIT(0)\n>> +#define TIM_DIER_CC1IE BIT(1)\n>>\n>> #define TIM_EGR_UG BIT(0)\n>>\n>> -struct stm32_clock_event_ddata {\n>> +struct stm32_clock_event {\n>> struct clock_event_device evtdev;\n>> unsigned periodic_top;\n>> - void __iomem *base;\n>> + void __iomem *regs;\n>> };\n>>\n>> static int stm32_clock_event_shutdown(struct clock_event_device *evtdev)\n>> {\n>> - struct stm32_clock_event_ddata *data =\n>> - container_of(evtdev, struct stm32_clock_event_ddata, evtdev);\n>> - void *base = data->base;\n>> + struct stm32_clock_event *ce =\n>> + container_of(evtdev, struct stm32_clock_event, evtdev);\n>> +\n>> + writel_relaxed(0, ce->regs + TIM_DIER);\n>>\n>> - writel_relaxed(0, base + TIM_CR1);\n>\n> Why this change? TIM_CR1 -> TIM_DIER? A 16b to 32b change?\n\nNo it is because I use the interrupt from the comparator instead of the counter.\nWith this patch clocksource will use the 32 bits counter of the hardware block\nto provide the clock and comparator is generate interrupt for the event.\nThat change quite a lot the code, sorry.\n\n\n>\n>> return 0;\n>> }\n>>\n>> -static int stm32_clock_event_set_periodic(struct clock_event_device *evtdev)\n>> +static int stm32_clock_event_set_next_event(unsigned long evt,\n>> + struct clock_event_device *evtdev)\n>> {\n>> - struct stm32_clock_event_ddata *data =\n>> - container_of(evtdev, struct stm32_clock_event_ddata, evtdev);\n>> - void *base = data->base;\n>> + struct stm32_clock_event *ce =\n>> + container_of(evtdev, struct stm32_clock_event, evtdev);\n>> + unsigned long cnt;\n>> +\n>> + cnt = readl_relaxed(ce->regs + TIM_CNT);\n>> + writel_relaxed(cnt + evt, ce->regs + TIM_CCR1);\n>> + writel_relaxed(TIM_DIER_CC1IE, ce->regs + TIM_DIER);\n>>\n>> - writel_relaxed(data->periodic_top, base + TIM_ARR);\n>> - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, base + TIM_CR1);\n>> return 0;\n>> }\n>>\n>> -static int stm32_clock_event_set_next_event(unsigned long evt,\n>> - struct clock_event_device *evtdev)\n>> +static int stm32_clock_event_set_periodic(struct clock_event_device *evtdev)\n>> {\n>> - struct stm32_clock_event_ddata *data =\n>> - container_of(evtdev, struct stm32_clock_event_ddata, evtdev);\n>> + struct stm32_clock_event *ce =\n>> + container_of(evtdev, struct stm32_clock_event, evtdev);\n>>\n>> - writel_relaxed(evt, data->base + TIM_ARR);\n>> - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN,\n>> - data->base + TIM_CR1);\n>> + return stm32_clock_event_set_next_event(ce->periodic_top, evtdev);\n>> +}\n>>\n>> - return 0;\n>> +static int stm32_clock_event_set_oneshot(struct clock_event_device *evtdev)\n>> +{\n>> + return stm32_clock_event_set_next_event(0, evtdev);\n>> }\n>>\n>> static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id)\n>> {\n>> - struct stm32_clock_event_ddata *data = dev_id;\n>> + struct stm32_clock_event *ce = dev_id;\n>> +\n>> + writel_relaxed(0, ce->regs + TIM_SR);\n>>\n>> - writel_relaxed(0, data->base + TIM_SR);\n>> + if (clockevent_state_periodic(&ce->evtdev))\n>> + stm32_clock_event_set_periodic(&ce->evtdev);\n>\n> nit: else condition to prevent an extra check\n\nOK\n\n>\n>> - data->evtdev.event_handler(&data->evtdev);\n>> + if (clockevent_state_oneshot(&ce->evtdev))\n>> + stm32_clock_event_shutdown(&ce->evtdev);\n>> +\n>> + ce->evtdev.event_handler(&ce->evtdev);\n>>\n>> return IRQ_HANDLED;\n>> }\n>>\n>> -static struct stm32_clock_event_ddata clock_event_ddata = {\n>> - .evtdev = {\n>> - .name = \"stm32 clockevent\",\n>> - .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,\n>> - .set_state_shutdown = stm32_clock_event_shutdown,\n>> - .set_state_periodic = stm32_clock_event_set_periodic,\n>> - .set_state_oneshot = stm32_clock_event_shutdown,\n>> - .tick_resume = stm32_clock_event_shutdown,\n>> - .set_next_event = stm32_clock_event_set_next_event,\n>> - .rating = 200,\n>> - },\n>> -};\n>> +static int __init stm32_clockevent_init(struct device_node *np,\n>> + void __iomem *base,\n>> + struct clk *clk, int irq)\n>> +{\n>> + struct stm32_clock_event *ce;\n>> + unsigned long rate;\n>> + int err;\n>> +\n>> + ce = kzalloc(sizeof(*ce), GFP_KERNEL);\n>> + if (!ce)\n>> + return -ENOMEM;\n>> +\n>> + ce->regs = base;\n>> + ce->evtdev.name = \"stm32_clockevent\";\n>> + ce->evtdev.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC;\n>> + ce->evtdev.set_state_shutdown = stm32_clock_event_shutdown;\n>> + ce->evtdev.set_state_periodic = stm32_clock_event_set_periodic;\n>> + ce->evtdev.set_state_oneshot = stm32_clock_event_set_oneshot;\n>> + ce->evtdev.tick_resume = stm32_clock_event_shutdown;\n>> + ce->evtdev.set_next_event = stm32_clock_event_set_next_event;\n>> + ce->evtdev.rating = 200;\n>>\n>> -static int __init stm32_clockevent_init(struct device_node *np)\n>> + rate = clk_get_rate(clk);\n>> + ce->periodic_top = DIV_ROUND_CLOSEST(rate, HZ);\n>> +\n>> + writel_relaxed(0, ce->regs + TIM_DIER);\n>> + writel_relaxed(0, ce->regs + TIM_SR);\n>> +\n>> + err = request_irq(irq, stm32_clock_event_handler, IRQF_TIMER,\n>> + \"stm32 clockevent\", ce);\n>> + if (err) {\n>> + kfree(ce);\n>> + return err;\n>> + }\n>> +\n>> + clockevents_config_and_register(&ce->evtdev, rate, 0x60, ~0U);\n>> +\n>> + return 0;\n>> +}\n>> +\n>> +static void __iomem *stm32_timer_cnt __read_mostly;\n>> +static u64 notrace stm32_read_sched_clock(void)\n>> +{\n>> + return readl_relaxed(stm32_timer_cnt);\n>> +}\n>> +\n>> +static int __init stm32_clocksource_init(struct device_node *node,\n>> + void __iomem *regs,\n>> + struct clk *clk)\n>> +{\n>> + unsigned long rate;\n>> +\n>> + rate = clk_get_rate(clk);\n>> +\n>> + writel_relaxed(~0U, regs + TIM_ARR);\n>> + writel_relaxed(0, regs + TIM_PSC);\n>> + writel_relaxed(0, regs + TIM_SR);\n>> + writel_relaxed(0, regs + TIM_DIER);\n>> + writel_relaxed(0, regs + TIM_SR);\n>> + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS, regs + TIM_CR1);\n>> +\n>> + /* Make sure that registers are updated */\n>> + writel_relaxed(TIM_EGR_UG, regs + TIM_EGR);\n>> +\n>> + /* Enable controller */\n>> + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS | TIM_CR1_CEN,\n>> + regs + TIM_CR1);\n>> +\n>> + stm32_timer_cnt = regs + TIM_CNT;\n>> + sched_clock_register(stm32_read_sched_clock, 32, rate);\n>> +\n>> + return clocksource_mmio_init(stm32_timer_cnt, \"stm32_timer\",\n>> + rate, 250, 32, clocksource_mmio_readl_up);\n>> +}\n>> +\n>> +static int __init stm32_timer_init(struct device_node *node)\n>> {\n>> - struct stm32_clock_event_ddata *data = &clock_event_ddata;\n>> - struct clk *clk;\n>> struct reset_control *rstc;\n>> - unsigned long rate, max_delta;\n>> - int irq, ret, bits, prescaler = 1;\n>> + void __iomem *timer_base;\n>> + unsigned long max_arr;\n>> + struct clk *clk;\n>> + int irq, err;\n>>\n>> - clk = of_clk_get(np, 0);\n>> - if (IS_ERR(clk)) {\n>> - ret = PTR_ERR(clk);\n>> - pr_err(\"failed to get clock for clockevent (%d)\\n\", ret);\n>> - goto err_clk_get;\n>> + timer_base = of_io_request_and_map(node, 0, of_node_full_name(node));\n>> + if (IS_ERR(timer_base)) {\n>> + pr_err(\"Can't map registers\\n\");\n>> + goto out;\n>> }\n>>\n>> - ret = clk_prepare_enable(clk);\n>> - if (ret) {\n>> - pr_err(\"failed to enable timer clock for clockevent (%d)\\n\",\n>> - ret);\n>> - goto err_clk_enable;\n>> + irq = irq_of_parse_and_map(node, 0);\n>> + if (irq <= 0) {\n>> + pr_err(\"Can't parse IRQ\\n\");\n>> + goto out_unmap;\n>> }\n>>\n>> - rate = clk_get_rate(clk);\n>\n> Why not pass the rate to clkevt_init and clksrc_init instead of clk? So\n> clk_get_rate() is not called twice.\n\nI will change that in v3\n\n>\n>> + clk = of_clk_get(node, 0);\n>> + if (IS_ERR(clk)) {\n>> + pr_err(\"Can't get timer clock\\n\");\n>> + goto out_unmap;\n>> + }\n>>\n>> - rstc = of_reset_control_get(np, NULL);\n>> + rstc = of_reset_control_get(node, NULL);\n>> if (!IS_ERR(rstc)) {\n>> reset_control_assert(rstc);\n>> reset_control_deassert(rstc);\n>> }\n>>\n>> - data->base = of_iomap(np, 0);\n>> - if (!data->base) {\n>> - ret = -ENXIO;\n>> - pr_err(\"failed to map registers for clockevent\\n\");\n>> - goto err_iomap;\n>> - }\n>> -\n>> - irq = irq_of_parse_and_map(np, 0);\n>> - if (!irq) {\n>> - ret = -EINVAL;\n>> - pr_err(\"%pOF: failed to get irq.\\n\", np);\n>> - goto err_get_irq;\n>> + err = clk_prepare_enable(clk);\n>> + if (err) {\n>> + pr_err(\"Couldn't enable parent clock\\n\");\n>> + goto out_clk;\n>> }\n>>\n>> /* Detect whether the timer is 16 or 32 bits */\n>> - writel_relaxed(~0U, data->base + TIM_ARR);\n>> - max_delta = readl_relaxed(data->base + TIM_ARR);\n>> - if (max_delta == ~0U) {\n>> - prescaler = 1;\n>> - bits = 32;\n>> - } else {\n>> - prescaler = 1024;\n>> - bits = 16;\n>> + writel_relaxed(~0U, timer_base + TIM_ARR);\n>> + max_arr = readl_relaxed(timer_base + TIM_ARR);\n>> + if (max_arr != ~0U) {\n>> + err = -EINVAL;\n>> + pr_err(\"32 bits timer is needed\\n\");\n>> + goto out_unprepare;\n>> }\n>> - writel_relaxed(0, data->base + TIM_ARR);\n>> -\n>> - writel_relaxed(prescaler - 1, data->base + TIM_PSC);\n>> - writel_relaxed(TIM_EGR_UG, data->base + TIM_EGR);\n>> - writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER);\n>> - writel_relaxed(0, data->base + TIM_SR);\n>> -\n>> - data->periodic_top = DIV_ROUND_CLOSEST(rate, prescaler * HZ);\n>>\n>> - clockevents_config_and_register(&data->evtdev,\n>> - DIV_ROUND_CLOSEST(rate, prescaler),\n>> - 0x1, max_delta);\n>> + err = stm32_clocksource_init(node, timer_base, clk);\n>> + if (err)\n>> + goto out_unprepare;\n>>\n>> - ret = request_irq(irq, stm32_clock_event_handler, IRQF_TIMER,\n>> - \"stm32 clockevent\", data);\n>> - if (ret) {\n>> - pr_err(\"%pOF: failed to request irq.\\n\", np);\n>> - goto err_get_irq;\n>> - }\n>> -\n>> - pr_info(\"%pOF: STM32 clockevent driver initialized (%d bits)\\n\",\n>> - np, bits);\n>> + err = stm32_clockevent_init(node, timer_base, clk, irq);\n>> + if (err)\n>> + goto out_unprepare;\n>>\n>> - return ret;\n>> + return 0;\n>>\n>> -err_get_irq:\n>> - iounmap(data->base);\n>> -err_iomap:\n>> +out_unprepare:\n>> clk_disable_unprepare(clk);\n>> -err_clk_enable:\n>> +out_clk:\n>> clk_put(clk);\n>> -err_clk_get:\n>> - return ret;\n>> +out_unmap:\n>> + iounmap(timer_base);\n>> +out:\n>> + return err;\n>> }\n>>\n>> -TIMER_OF_DECLARE(stm32, \"st,stm32-timer\", stm32_clockevent_init);\n>> +CLOCKSOURCE_OF_DECLARE(stm32, \"st,stm32-timer\", stm32_timer_init);\n>\n> CLOCKSOURCE_OF_DECLARE is deprecated, keep using TIMER_OF_DECLARE.\n\nOK\n>\n>\n> --\n> Linaro.org │ Open source software for ARM SoCs\n>\n> Follow Linaro: Facebook |\n> Twitter |\n> Blog\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1771175,"web_url":"http://patchwork.ozlabs.org/comment/1771175/","msgid":"","list_archive_url":null,"date":"2017-09-19T15:54:37","subject":"Re: [PATCH 1/2] clocksource: stm32: rework driver to use only one\n\ttimer","submitter":{"id":13265,"url":"http://patchwork.ozlabs.org/api/people/13265/","name":"Daniel Lezcano","email":"daniel.lezcano@linaro.org"},"content":"On 19/09/2017 09:59, Benjamin Gaignard wrote:\n> 2017-09-18 23:30 GMT+02:00 Daniel Lezcano :\n>> On 14/09/2017 09:56, Benjamin Gaignard wrote:\n>>> Rework driver code to use only one timer for both clocksource\n>>> and clockevent.\n>>> This patch also forbids to use 16 bits timers because they are\n>>> not enough accurate.\n>>> Do some clean up in structures and functions names too.\n>>>\n>>> Signed-off-by: Ludovic Barre \n>>> Signed-off-by: Benjamin Gaignard \n>>\n>> Hi Benjamin,\n>>\n>> I have a few comments below. Can you when reposting split this patch\n>> into smaller changes ?\n> \n> Not so easy because I change the way of how the hardware is used to be able\n> to provide clocksource and clockevent on the same hardware block.\n> \n>>\n>> Also, can you consider using the timer-of API ?\n> \n> Is it just about using TIMER_OF_DECLARE ? or do you have something\n> else in mind ?\n\nIt is something else, see commit dc11bae785.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"SNMXbCbw\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"OtiPv+Nt\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxSBf2qF9z9s7h\n\tfor ;\n\tWed, 20 Sep 2017 01:55:22 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1duKrm-0003PP-B6; Tue, 19 Sep 2017 15:55:18 +0000","from mail-pf0-x235.google.com ([2607:f8b0:400e:c00::235])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1duKrV-0002PG-PV for linux-arm-kernel@lists.infradead.org;\n\tTue, 19 Sep 2017 15:55:04 +0000","by mail-pf0-x235.google.com with SMTP id z84so32718pfi.2\n\tfor ;\n\tTue, 19 Sep 2017 08:54:40 -0700 (PDT)","from [192.168.0.5] (cpe-66-75-63-57.san.res.rr.com. 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