[{"id":1773432,"web_url":"http://patchwork.ozlabs.org/comment/1773432/","msgid":"<20170922120844.6cc692e6@bbrezillon>","list_archive_url":null,"date":"2017-09-22T10:08:44","subject":"Re: [PATCH v2 0/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag and\n\timprove Denali driver","submitter":{"id":63120,"url":"http://patchwork.ozlabs.org/api/people/63120/","name":"Boris Brezillon","email":"boris.brezillon@free-electrons.com"},"content":"On Wed, 13 Sep 2017 11:05:49 +0900\nMasahiro Yamada wrote:\n\n> Currently, Denali NAND driver always expects 3 row address cycle\n> devices because the driver init code hard-code the register setting.\n> I will fix it in 2/2.\n> \n> Many drivers check chip->chipsize if the third row address cycle\n> is needed or not. This is not nice because 32MB, 128MB are\n> magic numbers. nand_scan_ident can decide it and provide a\n> driver-friendly flag.\n> \n> 1/2 is touching verious drivers.\n> I hope Acked-by from driver maintainers if this change looks good.\n> \n\nApplied.\n\nThanks,\n\nBoris\n\n> \n> Changes in v2:\n> - Fix build error\n> \n> Masahiro Yamada (2):\n> mtd: nand: introduce NAND_ROW_ADDR_3 flag\n> mtd: nand: denali: support two row address cycle devices\n> \n> drivers/mtd/nand/atmel/nand-controller.c | 3 +--\n> drivers/mtd/nand/au1550nd.c | 3 +--\n> drivers/mtd/nand/denali.c | 4 ++--\n> drivers/mtd/nand/diskonchip.c | 3 +--\n> drivers/mtd/nand/hisi504_nand.c | 3 +--\n> drivers/mtd/nand/mxc_nand.c | 3 +--\n> drivers/mtd/nand/nand_base.c | 9 +++++----\n> drivers/mtd/nand/nuc900_nand.c | 2 +-\n> include/linux/mtd/rawnand.h | 3 +++\n> 9 files changed, 16 insertions(+), 17 deletions(-)\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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