[{"id":1767493,"web_url":"http://patchwork.ozlabs.org/comment/1767493/","msgid":"","list_archive_url":null,"date":"2017-09-13T02:45:36","subject":"Re: [PATCH v2 1/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag","submitter":{"id":69532,"url":"http://patchwork.ozlabs.org/api/people/69532/","name":"Wenyou Yang","email":"Wenyou.Yang@microchip.com"},"content":"On 2017/9/13 10:05, Masahiro Yamada wrote:\n> Several drivers check ->chipsize to see if the third row address cycle\n> is needed. Instead of embedding magic sizes such as 32MB, 128MB in\n> drivers, introduce a new flag NAND_ROW_ADDR_3 for clean-up. Since\n> nand_scan_ident() knows well about the device, it can handle this\n> properly. The flag is set if the row address bit width is greater\n> than 16.\n>\n> Delete comments such as \"One more address cycle for ...\" because\n> intention is now clear enough from the code.\n>\n> Signed-off-by: Masahiro Yamada \n\nFor atmel/nand-controller,\nAcked-by: Wenyou Yang \n\n> ---\n>\n> Changes in v2:\n> - Fix build error\n>\n> drivers/mtd/nand/atmel/nand-controller.c | 3 +--\n> drivers/mtd/nand/au1550nd.c | 3 +--\n> drivers/mtd/nand/diskonchip.c | 3 +--\n> drivers/mtd/nand/hisi504_nand.c | 3 +--\n> drivers/mtd/nand/mxc_nand.c | 3 +--\n> drivers/mtd/nand/nand_base.c | 9 +++++----\n> drivers/mtd/nand/nuc900_nand.c | 2 +-\n> include/linux/mtd/rawnand.h | 3 +++\n> 8 files changed, 14 insertions(+), 15 deletions(-)\n>\n> diff --git a/drivers/mtd/nand/atmel/nand-controller.c b/drivers/mtd/nand/atmel/nand-controller.c\n> index f25eca7..7bc8d20 100644\n> --- a/drivers/mtd/nand/atmel/nand-controller.c\n> +++ b/drivers/mtd/nand/atmel/nand-controller.c\n> @@ -718,8 +718,7 @@ static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)\n> \t\tnc->op.addrs[nc->op.naddrs++] = page;\n> \t\tnc->op.addrs[nc->op.naddrs++] = page >> 8;\n> \n> -\t\tif ((mtd->writesize > 512 && chip->chipsize > SZ_128M) ||\n> -\t\t (mtd->writesize <= 512 && chip->chipsize > SZ_32M))\n> +\t\tif (chip->options & NAND_ROW_ADDR_3)\n> \t\t\tnc->op.addrs[nc->op.naddrs++] = page >> 16;\n> \t}\n> }\n> diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c\n> index 9d4a28f..8ab827e 100644\n> --- a/drivers/mtd/nand/au1550nd.c\n> +++ b/drivers/mtd/nand/au1550nd.c\n> @@ -331,8 +331,7 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i\n> \n> \t\t\tctx->write_byte(mtd, (u8)(page_addr >> 8));\n> \n> -\t\t\t/* One more address cycle for devices > 32MiB */\n> -\t\t\tif (this->chipsize > (32 << 20))\n> +\t\t\tif (this->options & NAND_ROW_ADDR_3)\n> \t\t\t\tctx->write_byte(mtd,\n> \t\t\t\t\t\t((page_addr >> 16) & 0x0f));\n> \t\t}\n> diff --git a/drivers/mtd/nand/diskonchip.c b/drivers/mtd/nand/diskonchip.c\n> index c3aa53c..72671dc 100644\n> --- a/drivers/mtd/nand/diskonchip.c\n> +++ b/drivers/mtd/nand/diskonchip.c\n> @@ -705,8 +705,7 @@ static void doc2001plus_command(struct mtd_info *mtd, unsigned command, int colu\n> \t\tif (page_addr != -1) {\n> \t\t\tWriteDOC((unsigned char)(page_addr & 0xff), docptr, Mplus_FlashAddress);\n> \t\t\tWriteDOC((unsigned char)((page_addr >> 8) & 0xff), docptr, Mplus_FlashAddress);\n> -\t\t\t/* One more address cycle for higher density devices */\n> -\t\t\tif (this->chipsize & 0x0c000000) {\n> +\t\t\tif (this->options & NAND_ROW_ADDR_3) {\n> \t\t\t\tWriteDOC((unsigned char)((page_addr >> 16) & 0x0f), docptr, Mplus_FlashAddress);\n> \t\t\t\tprintk(\"high density\\n\");\n> \t\t\t}\n> diff --git a/drivers/mtd/nand/hisi504_nand.c b/drivers/mtd/nand/hisi504_nand.c\n> index d9ee1a7..0897261 100644\n> --- a/drivers/mtd/nand/hisi504_nand.c\n> +++ b/drivers/mtd/nand/hisi504_nand.c\n> @@ -432,8 +432,7 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr)\n> \t\thost->addr_value[0] |= (page_addr & 0xffff)\n> \t\t\t<< (host->addr_cycle * 8);\n> \t\thost->addr_cycle += 2;\n> -\t\t/* One more address cycle for devices > 128MiB */\n> -\t\tif (chip->chipsize > (128 << 20)) {\n> +\t\tif (chip->options & NAND_ROW_ADDR_3) {\n> \t\t\thost->addr_cycle += 1;\n> \t\t\tif (host->command == NAND_CMD_ERASE1)\n> \t\t\t\thost->addr_value[0] |= ((page_addr >> 16) & 0xff) << 16;\n> diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c\n> index 53e5e03..bacdd04 100644\n> --- a/drivers/mtd/nand/mxc_nand.c\n> +++ b/drivers/mtd/nand/mxc_nand.c\n> @@ -859,8 +859,7 @@ static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)\n> \t\t\t\thost->devtype_data->send_addr(host,\n> \t\t\t\t\t\t(page_addr >> 8) & 0xff, true);\n> \t\t} else {\n> -\t\t\t/* One more address cycle for higher density devices */\n> -\t\t\tif (mtd->size >= 0x4000000) {\n> +\t\t\tif (nand_chip->options & NAND_ROW_ADDR_3) {\n> \t\t\t\t/* paddr_8 - paddr_15 */\n> \t\t\t\thost->devtype_data->send_addr(host,\n> \t\t\t\t\t\t(page_addr >> 8) & 0xff,\n> diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c\n> index bcc8cef1..3bc4404 100644\n> --- a/drivers/mtd/nand/nand_base.c\n> +++ b/drivers/mtd/nand/nand_base.c\n> @@ -727,8 +727,7 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,\n> \t\tchip->cmd_ctrl(mtd, page_addr, ctrl);\n> \t\tctrl &= ~NAND_CTRL_CHANGE;\n> \t\tchip->cmd_ctrl(mtd, page_addr >> 8, ctrl);\n> -\t\t/* One more address cycle for devices > 32MiB */\n> -\t\tif (chip->chipsize > (32 << 20))\n> +\t\tif (chip->options & NAND_ROW_ADDR_3)\n> \t\t\tchip->cmd_ctrl(mtd, page_addr >> 16, ctrl);\n> \t}\n> \tchip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);\n> @@ -854,8 +853,7 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command,\n> \t\t\tchip->cmd_ctrl(mtd, page_addr, ctrl);\n> \t\t\tchip->cmd_ctrl(mtd, page_addr >> 8,\n> \t\t\t\t NAND_NCE | NAND_ALE);\n> -\t\t\t/* One more address cycle for devices > 128MiB */\n> -\t\t\tif (chip->chipsize > (128 << 20))\n> +\t\t\tif (chip->options & NAND_ROW_ADDR_3)\n> \t\t\t\tchip->cmd_ctrl(mtd, page_addr >> 16,\n> \t\t\t\t\t NAND_NCE | NAND_ALE);\n> \t\t}\n> @@ -4000,6 +3998,9 @@ static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)\n> \t\tchip->chip_shift += 32 - 1;\n> \t}\n> \n> +\tif (chip->chip_shift - chip->page_shift > 16)\n> +\t\tchip->options |= NAND_ROW_ADDR_3;\n> +\n> \tchip->badblockbits = 8;\n> \tchip->erase = single_erase;\n> \n> diff --git a/drivers/mtd/nand/nuc900_nand.c b/drivers/mtd/nand/nuc900_nand.c\n> index 7bb4d2e..af5b32c9 100644\n> --- a/drivers/mtd/nand/nuc900_nand.c\n> +++ b/drivers/mtd/nand/nuc900_nand.c\n> @@ -154,7 +154,7 @@ static void nuc900_nand_command_lp(struct mtd_info *mtd, unsigned int command,\n> \t\tif (page_addr != -1) {\n> \t\t\twrite_addr_reg(nand, page_addr);\n> \n> -\t\t\tif (chip->chipsize > (128 << 20)) {\n> +\t\t\tif (chip->options & NAND_ROW_ADDR_3) {\n> \t\t\t\twrite_addr_reg(nand, page_addr >> 8);\n> \t\t\t\twrite_addr_reg(nand, page_addr >> 16 | ENDADDR);\n> \t\t\t} else {\n> diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h\n> index 2b05f42..749bb08 100644\n> --- a/include/linux/mtd/rawnand.h\n> +++ b/include/linux/mtd/rawnand.h\n> @@ -177,6 +177,9 @@ enum nand_ecc_algo {\n> */\n> #define NAND_NEED_SCRAMBLING\t0x00002000\n> \n> +/* Device needs 3rd row address cycle */\n> +#define NAND_ROW_ADDR_3\t\t0x00004000\n> +\n> /* Options valid for Samsung large page devices */\n> #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG\n> \n\nRegards,\nWenyou Yang","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) 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,\n\t","References":"<1505268351-31941-1-git-send-email-yamada.masahiro@socionext.com>\n\t<1505268351-31941-2-git-send-email-yamada.masahiro@socionext.com>","From":"\"Yang, Wenyou\" ","Message-ID":"","Date":"Wed, 13 Sep 2017 10:45:36 +0800","User-Agent":"Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1505268351-31941-2-git-send-email-yamada.masahiro@socionext.com>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170912_194606_191063_27C7D1C9 ","X-CRM114-Status":"GOOD ( 14.37 )","X-Spam-Score":"-2.6 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.6 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow trust [68.232.149.84 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Boris Brezillon ,\n\tRichard Weinberger , Wan ZongShun , \n\tJosh Wu , linux-kernel@vger.kernel.org,\n\tWenyou Yang ,\n\tMarek Vasut , \n\tCyrille Pitchen ,\n\tBrian Norris ,\n\tDavid Woodhouse ,\n\tlinux-arm-kernel@lists.infradead.org","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1773431,"web_url":"http://patchwork.ozlabs.org/comment/1773431/","msgid":"<20170922120844.6cc692e6@bbrezillon>","list_archive_url":null,"date":"2017-09-22T10:08:44","subject":"Re: [PATCH v2 0/2] mtd: nand: introduce NAND_ROW_ADDR_3 flag and\n\timprove Denali driver","submitter":{"id":63120,"url":"http://patchwork.ozlabs.org/api/people/63120/","name":"Boris Brezillon","email":"boris.brezillon@free-electrons.com"},"content":"On Wed, 13 Sep 2017 11:05:49 +0900\nMasahiro Yamada wrote:\n\n> Currently, Denali NAND driver always expects 3 row address cycle\n> devices because the driver init code hard-code the register setting.\n> I will fix it in 2/2.\n> \n> Many drivers check chip->chipsize if the third row address cycle\n> is needed or not. This is not nice because 32MB, 128MB are\n> magic numbers. nand_scan_ident can decide it and provide a\n> driver-friendly flag.\n> \n> 1/2 is touching verious drivers.\n> I hope Acked-by from driver maintainers if this change looks good.\n> \n\nApplied.\n\nThanks,\n\nBoris\n\n> \n> Changes in v2:\n> - Fix build error\n> \n> Masahiro Yamada (2):\n> mtd: nand: introduce NAND_ROW_ADDR_3 flag\n> mtd: nand: denali: support two row address cycle devices\n> \n> drivers/mtd/nand/atmel/nand-controller.c | 3 +--\n> drivers/mtd/nand/au1550nd.c | 3 +--\n> drivers/mtd/nand/denali.c | 4 ++--\n> drivers/mtd/nand/diskonchip.c | 3 +--\n> drivers/mtd/nand/hisi504_nand.c | 3 +--\n> drivers/mtd/nand/mxc_nand.c | 3 +--\n> drivers/mtd/nand/nand_base.c | 9 +++++----\n> drivers/mtd/nand/nuc900_nand.c | 2 +-\n> include/linux/mtd/rawnand.h | 3 +++\n> 9 files changed, 16 insertions(+), 17 deletions(-)\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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