[{"id":1766422,"web_url":"http://patchwork.ozlabs.org/comment/1766422/","msgid":"<1505151868.31322.98.camel@infinera.com>","list_archive_url":null,"date":"2017-09-11T17:44:31","subject":"Re: [PATCH v2 00/10] spi-nor: intel-spi: Various fixes and\n\tenhancements","submitter":{"id":67550,"url":"http://patchwork.ozlabs.org/api/people/67550/","name":"Joakim Tjernlund","email":"Joakim.Tjernlund@infinera.com"},"content":"On Mon, 2017-09-11 at 02:41 -0700, Bin Meng wrote:\n> This series does several bug fixes and clean ups against the intel-spi\n> spi-nor driver, as well as enhancements to make the driver independent\n> on the underlying BIOS/bootloader.\n> \n> At present the driver uses the HW sequencer for the read/write/erase on\n> all supported platforms, read_reg/write_reg for BXT, and the SW sequencer\n> for read_reg/write_reg for BYT/LPT. The way the driver uses the HW and SW\n> sequencer relies on some programmed register settings and hence creates\n> unneeded dependencies with the underlying BIOS/bootloader. For example,\n> the driver unfortunately does not work as expected when booting from\n> Intel Baytrail FSP based bootloaders like U-Boot, as the Baytrail FSP\n> does not set up some SPI controller settings to make the driver happy.\n> Now such limitation has been removed with this series.\n\nHi Bin\n\nJust starting to test these on Rangeley and got a question: We have two SPI flashes on CS0 resp. CS1 \nand the mtd driver seems to only map the first of those flashes. Is this intentional or\nare we missing something?\n\n Jocke\n\n> \n> Changes in v2:\n> - Add stable kernel tags in the commit message (patch [03/10])\n> - Fix typo of 'operatoin' (patch [10/10])\n> - Add Mika Westerberg's 'Acked-by' tag\n> \n> Bin Meng (10):\n> spi-nor: intel-spi: Fix number of protected range registers for\n> BYT/LPT\n> spi-nor: intel-spi: Remove useless 'buf' parameter in the HW/SW cycle\n> spi-nor: intel-spi: Fix broken software sequencing codes\n> spi-nor: intel-spi: Check transfer length in the HW/SW cycle\n> spi-nor: intel-spi: Use SW sequencer for BYT/LPT\n> spi-nor: intel-spi: Remove 'Atomic Cycle Sequence' in\n> intel_spi_write()\n> spi-nor: intel-spi: Don't assume OPMENU0/1 to be programmed by BIOS\n> spi-nor: intel-spi: Remove the unnecessary HSFSTS register RW\n> spi-nor: intel-spi: Rename swseq to swseq_reg in 'struct intel_spi'\n> spi-nor: intel-spi: Fall back to use SW sequencer to erase\n> \n> drivers/mtd/spi-nor/intel-spi.c | 209 +++++++++++++++++++++++++++++-----------\n> 1 file changed, 151 insertions(+), 58 deletions(-)\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":1767454,"web_url":"http://patchwork.ozlabs.org/comment/1767454/","msgid":"","list_archive_url":null,"date":"2017-09-13T02:11:21","subject":"Re: [PATCH v2 00/10] spi-nor: intel-spi: Various fixes and\n\tenhancements","submitter":{"id":64981,"url":"http://patchwork.ozlabs.org/api/people/64981/","name":"Bin Meng","email":"bmeng.cn@gmail.com"},"content":"Hi Joakim,\n\nOn Tue, Sep 12, 2017 at 1:44 AM, Joakim Tjernlund\n wrote:\n> On Mon, 2017-09-11 at 02:41 -0700, Bin Meng wrote:\n>> This series does several bug fixes and clean ups against the intel-spi\n>> spi-nor driver, as well as enhancements to make the driver independent\n>> on the underlying BIOS/bootloader.\n>>\n>> At present the driver uses the HW sequencer for the read/write/erase on\n>> all supported platforms, read_reg/write_reg for BXT, and the SW sequencer\n>> for read_reg/write_reg for BYT/LPT. The way the driver uses the HW and SW\n>> sequencer relies on some programmed register settings and hence creates\n>> unneeded dependencies with the underlying BIOS/bootloader. For example,\n>> the driver unfortunately does not work as expected when booting from\n>> Intel Baytrail FSP based bootloaders like U-Boot, as the Baytrail FSP\n>> does not set up some SPI controller settings to make the driver happy.\n>> Now such limitation has been removed with this series.\n>\n> Hi Bin\n>\n> Just starting to test these on Rangeley and got a question: We have two SPI flashes on CS0 resp. CS1\n> and the mtd driver seems to only map the first of those flashes. Is this intentional or\n> are we missing something?\n>\n\nAll the boards I have tested only have one SPI flash. Mika, any comments?\n\nRegards,\nBin","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; spf=none (mailfrom)\n\tsmtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133;\n\thelo=bombadil.infradead.org;\n\tenvelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"ZLNjaSYM\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"VAAzYUO2\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsQCF0lVvz9rvt\n\tfor ;\n\tWed, 13 Sep 2017 12:11:53 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1drx9Z-0003wm-II; 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\n\tTue, 12 Sep 2017 19:11:22 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<1505151868.31322.98.camel@infinera.com>","References":"<1505122921-5534-1-git-send-email-bmeng.cn@gmail.com>\n\t<1505151868.31322.98.camel@infinera.com>","From":"Bin Meng ","Date":"Wed, 13 Sep 2017 10:11:21 +0800","Message-ID":"","Subject":"Re: [PATCH v2 00/10] spi-nor: intel-spi: Various fixes and\n\tenhancements","To":"Joakim Tjernlund ","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170912_191145_388586_50055BD0 ","X-CRM114-Status":"GOOD ( 13.88 )","X-Spam-Score":"-2.7 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.7 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow\n\ttrust [2a00:1450:400c:c09:0:0:0:22c listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (bmeng.cn[at]gmail.com)\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"boris.brezillon@free-electrons.com\"\n\t, \n\t\"sr@denx.de\" , \"richard@nod.at\" ,\n\t\"dwmw2@infradead.org\" ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\t\"marek.vasut@gmail.com\" ,\n\t\"linux-mtd@lists.infradead.org\" ,\n\t\"cyrille.pitchen@wedev4u.fr\" ,\n\t\"computersforpeace@gmail.com\" ,\n\t\"mika.westerberg@linux.intel.com\" ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":1767724,"web_url":"http://patchwork.ozlabs.org/comment/1767724/","msgid":"<20170913094702.GW2477@lahna.fi.intel.com>","list_archive_url":null,"date":"2017-09-13T09:47:02","subject":"Re: [PATCH v2 00/10] spi-nor: intel-spi: Various fixes and\n\tenhancements","submitter":{"id":14534,"url":"http://patchwork.ozlabs.org/api/people/14534/","name":"Mika Westerberg","email":"mika.westerberg@linux.intel.com"},"content":"On Wed, Sep 13, 2017 at 10:11:21AM +0800, Bin Meng wrote:\n> Hi Joakim,\n> \n> On Tue, Sep 12, 2017 at 1:44 AM, Joakim Tjernlund\n> wrote:\n> > On Mon, 2017-09-11 at 02:41 -0700, Bin Meng wrote:\n> >> This series does several bug fixes and clean ups against the intel-spi\n> >> spi-nor driver, as well as enhancements to make the driver independent\n> >> on the underlying BIOS/bootloader.\n> >>\n> >> At present the driver uses the HW sequencer for the read/write/erase on\n> >> all supported platforms, read_reg/write_reg for BXT, and the SW sequencer\n> >> for read_reg/write_reg for BYT/LPT. The way the driver uses the HW and SW\n> >> sequencer relies on some programmed register settings and hence creates\n> >> unneeded dependencies with the underlying BIOS/bootloader. For example,\n> >> the driver unfortunately does not work as expected when booting from\n> >> Intel Baytrail FSP based bootloaders like U-Boot, as the Baytrail FSP\n> >> does not set up some SPI controller settings to make the driver happy.\n> >> Now such limitation has been removed with this series.\n> >\n> > Hi Bin\n> >\n> > Just starting to test these on Rangeley and got a question: We have two SPI flashes on CS0 resp. CS1\n> > and the mtd driver seems to only map the first of those flashes. Is this intentional or\n> > are we missing something?\n> >\n> \n> All the boards I have tested only have one SPI flash. Mika, any comments?\n\nSo I don't have such boards either.\n\nHowever, I think the other CS is mapped to bit 24 of the flash address.\nSo once you try to address higher than 16MB it should activate the other\nCS instead. Not 100% sure, though but for example Intel C620 chipset\ndatasheet [1] seems to have additional bits in address register (there is\nalso another CS for TPM).\n\n[1] https://www.intel.com/content/www/us/en/chipsets/c620-series-chipset-datasheet.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; spf=none (mailfrom)\n\tsmtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133;\n\thelo=bombadil.infradead.org;\n\tenvelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"sxwvnLk5\"; \n\tdkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xscKB0YmLz9sPm\n\tfor ;\n\tWed, 13 Sep 2017 19:47:42 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1ds4Gc-0004i3-Q3; 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bh=NlYKbU7M8uBloqFG7K9Kdi9l6XuuvnhhO6XlRZgzYnQ=;\n\tb=sxwvnLk5eE8ptK\n\tVcaqCDVHDs/xxvxPlyyWw7JAPBlPKwN+TwvkJ6twK1JcC6VLAfiTpNOZZkD+NQ0hm+D84ePoJge51\n\tTBLTFNDQBOy5uGBjHtz68fElDmFyOS9IZ5ACLA8ghjymy00fSZU/k6lasbDulHPOHTgq3VUqhAy09\n\tTdQB5ccERqItEQzfLNoq0VaVVTKkJ5XuB/Qw48xVOrHLrzydukbk/KzGMAqtjN4E1iDJSBjUMzqFm\n\tf7asMpsU1CTwDmOSWKj/DmVQ7q3wT5tWCPN5aQV8GYeg9YPZtfQbhtO9LlkU6ZNxslDhJ9FDjuLEI\n\tbSYCuTjmapYCTlz0dW5g==;","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos; i=\"5.42,387,1500966000\"; d=\"scan'208\";\n\ta=\"1171791636\"","Date":"Wed, 13 Sep 2017 12:47:02 +0300","From":"\"mika.westerberg@linux.intel.com\" ","To":"Bin Meng ","Subject":"Re: [PATCH v2 00/10] spi-nor: intel-spi: Various fixes and\n\tenhancements","Message-ID":"<20170913094702.GW2477@lahna.fi.intel.com>","References":"<1505122921-5534-1-git-send-email-bmeng.cn@gmail.com>\n\t<1505151868.31322.98.camel@infinera.com>\n\t","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"","Organization":"Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo","User-Agent":"Mutt/1.8.3 (2017-05-23)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170913_024730_676621_D80415C4 ","X-CRM114-Status":"GOOD ( 17.94 )","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [192.55.52.43 listed in list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"boris.brezillon@free-electrons.com\"\n\t, \"sr@denx.de\" ,\n\t\"marek.vasut@gmail.com\" , \n\t\"richard@nod.at\" ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\tJoakim Tjernlund ,\n\t\"linux-mtd@lists.infradead.org\" ,\n\t\"cyrille.pitchen@wedev4u.fr\" ,\n\t\"computersforpeace@gmail.com\" ,\n\t\"dwmw2@infradead.org\" ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":1784388,"web_url":"http://patchwork.ozlabs.org/comment/1784388/","msgid":"","list_archive_url":null,"date":"2017-10-11T08:06:44","subject":"Re: [PATCH v2 00/10] spi-nor: intel-spi: Various fixes and\n\tenhancements","submitter":{"id":70551,"url":"http://patchwork.ozlabs.org/api/people/70551/","name":"Cyrille Pitchen","email":"cyrille.pitchen@wedev4u.fr"},"content":"Le 11/09/2017 à 11:41, Bin Meng a écrit :\n> This series does several bug fixes and clean ups against the intel-spi\n> spi-nor driver, as well as enhancements to make the driver independent\n> on the underlying BIOS/bootloader.\n> \n> At present the driver uses the HW sequencer for the read/write/erase on\n> all supported platforms, read_reg/write_reg for BXT, and the SW sequencer\n> for read_reg/write_reg for BYT/LPT. The way the driver uses the HW and SW\n> sequencer relies on some programmed register settings and hence creates\n> unneeded dependencies with the underlying BIOS/bootloader. For example,\n> the driver unfortunately does not work as expected when booting from\n> Intel Baytrail FSP based bootloaders like U-Boot, as the Baytrail FSP\n> does not set up some SPI controller settings to make the driver happy.\n> Now such limitation has been removed with this series.\n> \n> Changes in v2:\n> - Add stable kernel tags in the commit message (patch [03/10])\n> - Fix typo of 'operatoin' (patch [10/10])\n> - Add Mika Westerberg's 'Acked-by' tag\n> \n> Bin Meng (10):\n> spi-nor: intel-spi: Fix number of protected range registers for\n> BYT/LPT\n> spi-nor: intel-spi: Remove useless 'buf' parameter in the HW/SW cycle\n> spi-nor: intel-spi: Fix broken software sequencing codes\n> spi-nor: intel-spi: Check transfer length in the HW/SW cycle\n> spi-nor: intel-spi: Use SW sequencer for BYT/LPT\n> spi-nor: intel-spi: Remove 'Atomic Cycle Sequence' in\n> intel_spi_write()\n> spi-nor: intel-spi: Don't assume OPMENU0/1 to be programmed by BIOS\n> spi-nor: intel-spi: Remove the unnecessary HSFSTS register RW\n> spi-nor: intel-spi: Rename swseq to swseq_reg in 'struct intel_spi'\n> spi-nor: intel-spi: Fall back to use SW sequencer to erase\n> \n> drivers/mtd/spi-nor/intel-spi.c | 209 +++++++++++++++++++++++++++++-----------\n> 1 file changed, 151 insertions(+), 58 deletions(-)\n> \nSeries applied to the spi-nor/next branch of l2-mtd\n\nThanks!","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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