[{"id":1765918,"web_url":"http://patchwork.ozlabs.org/comment/1765918/","msgid":"","list_archive_url":null,"date":"2017-09-10T08:36:30","subject":"Re: [PATCH v5 1/3] arm: npcm: add basic support for Nuvoton BMCs","submitter":{"id":72291,"url":"http://patchwork.ozlabs.org/api/people/72291/","name":"Tomer Maimon","email":"tmaimon77@gmail.com"},"content":"On 9 September 2017 at 04:53, Brendan Higgins wrote:\n> Adds basic support for the Nuvoton NPCM750 BMC.\n>\n> Signed-off-by: Brendan Higgins \n> ---\n> arch/arm/Kconfig | 2 +\n> arch/arm/Makefile | 1 +\n> arch/arm/mach-npcm/Kconfig | 48 ++++++++++++++++++++++++\n> arch/arm/mach-npcm/Makefile | 3 ++\n> arch/arm/mach-npcm/headsmp.S | 17 +++++++++\n> arch/arm/mach-npcm/npcm7xx.c | 34 +++++++++++++++++\n> arch/arm/mach-npcm/platsmp.c | 88 ++++++++++++++++++++++++++++++++++++++++++++\n> 7 files changed, 193 insertions(+)\n> create mode 100644 arch/arm/mach-npcm/Kconfig\n> create mode 100644 arch/arm/mach-npcm/Makefile\n> create mode 100644 arch/arm/mach-npcm/headsmp.S\n> create mode 100644 arch/arm/mach-npcm/npcm7xx.c\n> create mode 100644 arch/arm/mach-npcm/platsmp.c\n>\n> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\n> index 61a0cb15067e..05543f1cfbde 100644\n> --- a/arch/arm/Kconfig\n> +++ b/arch/arm/Kconfig\n> @@ -782,6 +782,8 @@ source \"arch/arm/mach-netx/Kconfig\"\n>\n> source \"arch/arm/mach-nomadik/Kconfig\"\n>\n> +source \"arch/arm/mach-npcm/Kconfig\"\n> +\n> source \"arch/arm/mach-nspire/Kconfig\"\n>\n> source \"arch/arm/plat-omap/Kconfig\"\n> diff --git a/arch/arm/Makefile b/arch/arm/Makefile\n> index 47d3a1ab08d2..60ca50c7d762 100644\n> --- a/arch/arm/Makefile\n> +++ b/arch/arm/Makefile\n> @@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MEDIATEK) += mediatek\n> machine-$(CONFIG_ARCH_MXS) += mxs\n> machine-$(CONFIG_ARCH_NETX) += netx\n> machine-$(CONFIG_ARCH_NOMADIK) += nomadik\n> +machine-$(CONFIG_ARCH_NPCM) += npcm\n> machine-$(CONFIG_ARCH_NSPIRE) += nspire\n> machine-$(CONFIG_ARCH_OXNAS) += oxnas\n> machine-$(CONFIG_ARCH_OMAP1) += omap1\n> diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig\n> new file mode 100644\n> index 000000000000..21dfa8ce828f\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/Kconfig\n> @@ -0,0 +1,48 @@\n> +menuconfig ARCH_NPCM\n> + bool \"Nuvoton NPCM Architecture\"\n> + select ARCH_REQUIRE_GPIOLIB\n> + select USE_OF\n> + select PINCTRL\n> + select PINCTRL_NPCM7XX\n> +\n> +if ARCH_NPCM\n> +\n> +comment \"NPCMX50 CPU type\"\n> +\n> +config CPU_NPCM750\n> + depends on ARCH_NPCM && ARCH_MULTI_V7\n> + bool \"Support for NPCM750 BMC CPU (Poleg)\"\n> + select CACHE_L2X0\n> + select CPU_V7\n> + select ARM_GIC\n> + select HAVE_SMP\n> + select SMP\n> + select SMP_ON_UP\n> + select HAVE_ARM_SCU\n> + select HAVE_ARM_TWD if SMP\n> + select ARM_ERRATA_720789\n> + select ARM_ERRATA_754322\n> + select ARM_ERRATA_764369\n> + select ARM_ERRATA_794072\n> + select PL310_ERRATA_588369\n> + select PL310_ERRATA_727915\n> + select USB_EHCI_ROOT_HUB_TT\n> + select USB_ARCH_HAS_HCD\n> + select USB_ARCH_HAS_EHCI\n> + select USB_EHCI_HCD\n> + select USB_ARCH_HAS_OHCI\n> + select USB_OHCI_HCD\n> + select USB\n> + select FIQ\n> + select CPU_USE_DOMAINS\n> + select GENERIC_CLOCKEVENTS\n> + select CLKDEV_LOOKUP\n> + select COMMON_CLK if OF\n> + select NPCM750_TIMER\n> + select MFD_SYSCON\n> + help\n> + Support for NPCM750 BMC CPU (Poleg).\n> +\n> + Nuvoton NPCM750 BMC based on the Cortex A9.\n> +\n> +endif\n> diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile\n> new file mode 100644\n> index 000000000000..78416055b854\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/Makefile\n> @@ -0,0 +1,3 @@\n> +AFLAGS_headsmp.o += -march=armv7-a\n> +\n> +obj-$(CONFIG_CPU_NPCM750) += npcm7xx.o platsmp.o headsmp.o\n> diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S\n> new file mode 100644\n> index 000000000000..9fccbbd49ed4\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/headsmp.S\n> @@ -0,0 +1,17 @@\n> +/*\n> + * Copyright 2017 Google, Inc.\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation.\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +\n> +ENTRY(npcm7xx_secondary_startup)\n> + safe_svcmode_maskall r0\n> +\n> + b secondary_startup\n> +ENDPROC(npcm7xx_secondary_startup)\n> diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c\n> new file mode 100644\n> index 000000000000..132e9d587857\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/npcm7xx.c\n> @@ -0,0 +1,34 @@\n> +/*\n> + * Copyright (c) 2017 Nuvoton Technology corporation.\n> + * Copyright 2017 Google, Inc.\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation.\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#define NPCM7XX_AUX_VAL (L310_AUX_CTRL_INSTR_PREFETCH | \\\n> + L310_AUX_CTRL_DATA_PREFETCH | \\\n> + L310_AUX_CTRL_NS_LOCKDOWN | \\\n> + L310_AUX_CTRL_CACHE_REPLACE_RR | \\\n> + L2C_AUX_CTRL_SHARED_OVERRIDE | \\\n> + L310_AUX_CTRL_FULL_LINE_ZERO)\n> +\n> +static const char *const npcm7xx_dt_match[] = {\n> + \"nuvoton,npcm750\",\n> + NULL\n> +};\n> +\n> +DT_MACHINE_START(NPCM7XX_DT, \"NPCMX50 Chip family\")\n> + .atag_offset = 0x100,\n> + .dt_compat = npcm7xx_dt_match,\n> + .l2c_aux_val = NPCM7XX_AUX_VAL,\n> + .l2c_aux_mask = ~NPCM7XX_AUX_VAL,\n> +MACHINE_END\n> diff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c\n> new file mode 100644\n> index 000000000000..450e83c3c531\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/platsmp.c\n> @@ -0,0 +1,88 @@\n> +/*\n> + * Copyright 2017 Google, Inc.\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation.\n> + */\n> +\n> +#define pr_fmt(fmt) \"PLATSMP: \" fmt\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#define NPCM7XX_SCRPAD_REG 0x13c\n> +\n> +extern void npcm7xx_secondary_startup(void);\n> +\n> +static int npcm7xx_smp_boot_secondary(unsigned int cpu,\n> + struct task_struct *idle)\n> +{\n> + struct device_node *gcr_np;\n> + void __iomem *gcr_base;\n> + int ret = 0;\n> +\n> + gcr_np = of_find_compatible_node(NULL, NULL, \"nuvoton,npcm750-gcr\");\n> + if (!gcr_np) {\n> + pr_err(\"no gcr device node\\n\");\n> + ret = -EFAULT;\n> + goto out;\n> + }\n> + gcr_base = of_iomap(gcr_np, 0);\n> + if (!gcr_base) {\n> + pr_err(\"could not iomap gcr at: 0x%p\\n\", gcr_base);\n> + ret = -EFAULT;\n> + goto out;\n> + }\n> +\n> + /* give boot ROM kernel start address. */\n> + iowrite32(__pa_symbol(npcm7xx_secondary_startup), gcr_base +\n> + NPCM7XX_SCRPAD_REG);\n> + /* make sure npcm7xx_secondary_startup is seen by all observers. */\n> + smp_wmb();\n> + dsb_sev();\n> + /* make sure write buffer is drained */\n> + mb();\n> +\n> + iounmap(gcr_base);\n> +out:\n> + return ret;\n> +}\n> +\n> +static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)\n> +{\n> + struct device_node *scu_np;\n> + void __iomem *scu_base;\n> +\n> + scu_np = of_find_compatible_node(NULL, NULL, \"arm,cortex-a9-scu\");\n> + if (!scu_np) {\n> + pr_err(\"no scu device node\\n\");\n> + return;\n> + }\n> + scu_base = of_iomap(scu_np, 0);\n> + if (!scu_base) {\n> + pr_err(\"could not iomap scu at: 0x%p\\n\", scu_base);\n> + return;\n> + }\n> +\n> + scu_enable(scu_base);\n> +\n> + iounmap(scu_base);\n> +}\n> +\n> +static struct smp_operations npcm7xx_smp_ops __initdata = {\n> + .smp_prepare_cpus = npcm7xx_smp_prepare_cpus,\n> + .smp_boot_secondary = npcm7xx_smp_boot_secondary,\n> +};\n> +\n> +CPU_METHOD_OF_DECLARE(npcm7xx_smp, \"nuvoton,npcm7xx-smp\", &npcm7xx_smp_ops);\n> --\n> 2.14.1.581.gf28d330327-goog\n>\n\nReviewed-by: Tomer Maimon \nReviewed-by: Avi Fishman \nTested-by: Tomer Maimon \nTested-by: Avi Fishman ","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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Sun,\n\t10 Sep 2017 01:36:31 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170909015308.30001-2-brendanhiggins@google.com>","References":"<20170909015308.30001-1-brendanhiggins@google.com>\n\t<20170909015308.30001-2-brendanhiggins@google.com>","From":"Tomer Maimon ","Date":"Sun, 10 Sep 2017 11:36:30 +0300","Message-ID":"","Subject":"Re: [PATCH v5 1/3] arm: npcm: add basic support for Nuvoton BMCs","To":"Brendan Higgins ","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170910_013655_079006_781919F0 ","X-CRM114-Status":"GOOD ( 17.26 )","X-Spam-Score":"-1.8 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.8 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2607:f8b0:400c:c05:0:0:0:244 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends\n\tin digit (tmaimon77[at]gmail.com)\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (tmaimon77[at]gmail.com)\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, devicetree@vger.kernel.org, f.fainelli@gmail.com, \n\tavifishman70@gmail.com, openbmc@lists.ozlabs.org, linux@armlinux.org.uk, \n\tlinux-kernel@vger.kernel.org, robh+dt@kernel.org,\n\tRick Altherr , linux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1770451,"web_url":"http://patchwork.ozlabs.org/comment/1770451/","msgid":"<20170918194625.xz5y7tkemjnbwunh@rob-hp-laptop>","list_archive_url":null,"date":"2017-09-18T19:46:25","subject":"Re: [PATCH v5 2/3] arm: dts: add Nuvoton NPCM750 device tree","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Fri, Sep 08, 2017 at 06:53:07PM -0700, Brendan Higgins wrote:\n> Add a common device tree for all Nuvoton NPCM750 BMCs and a board\n> specific device tree for the NPCM750 (Poleg) evaluation board.\n> \n> Signed-off-by: Brendan Higgins \n> Reviewed-by: Tomer Maimon \n> Reviewed-by: Avi Fishman \n> Reviewed-by: Joel Stanley \n> Tested-by: Tomer Maimon \n> Tested-by: Avi Fishman \n> ---\n> .../arm/cpu-enable-method/nuvoton,npcm7xx-smp | 42 +++++\n> .../devicetree/bindings/arm/npcm/npcm.txt | 6 +\n> arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 57 +++++++\n> arch/arm/boot/dts/nuvoton-npcm750.dtsi | 177 +++++++++++++++++++++\n> include/dt-bindings/clock/nuvoton,npcm7xx-clks.h | 39 +++++\n> 5 files changed, 321 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n> create mode 100644 Documentation/devicetree/bindings/arm/npcm/npcm.txt\n> create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n> create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi\n> create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clks.h\n> \n> diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n> new file mode 100644\n> index 000000000000..e81f85b400cf\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n> @@ -0,0 +1,42 @@\n> +=========================================================\n> +Secondary CPU enable-method \"nuvoton,npcm7xx-smp\" binding\n> +=========================================================\n> +\n> +To apply to all CPUs, a single \"nuvoton,npcm7xx-smp\" enable method should be\n> +defined in the \"cpus\" node.\n> +\n> +Enable method name:\t\"nuvoton,npcm7xx-smp\"\n> +Compatible machines:\t\"nuvoton,npcm750\"\n> +Compatible CPUs:\t\"arm,cortex-a9\"\n> +Related properties:\t(none)\n> +\n> +Note:\n> +This enable method needs valid nodes compatible with \"arm,cortex-a9-scu\" and\n> +\"nuvoton,npcm750-gcr\".\n> +\n> +Example:\n> +\n> +\tcpus {\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\t\tenable-method = \"nuvoton,npcm7xx-smp\";\n> +\n> +\t\tcpu@0 {\n> +\t\t\tdevice_type = \"cpu\";\n> +\t\t\tcompatible = \"arm,cortex-a9\";\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_CPU>;\n> +\t\t\tclock-names = \"clk_cpu\";\n> +\t\t\treg = <0>;\n> +\t\t\tnext-level-cache = <&L2>;\n> +\t\t};\n> +\n> +\t\tcpu@1 {\n> +\t\t\tdevice_type = \"cpu\";\n> +\t\t\tcompatible = \"arm,cortex-a9\";\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_CPU>;\n> +\t\t\tclock-names = \"clk_cpu\";\n> +\t\t\treg = <1>;\n> +\t\t\tnext-level-cache = <&L2>;\n> +\t\t};\n> +\t};\n> +\n> diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt\n> new file mode 100644\n> index 000000000000..2d87d9ecea85\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt\n> @@ -0,0 +1,6 @@\n> +NPCM Platforms Device Tree Bindings\n> +-----------------------------------\n> +NPCM750 SoC\n> +Required root node properties:\n> +\t- compatible = \"nuvoton,npcm750\";\n> +\n> diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n> new file mode 100644\n> index 000000000000..e54a870d3ee0\n> --- /dev/null\n> +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n> @@ -0,0 +1,57 @@\n> +/*\n> + * DTS file for all NPCM750 SoCs\n> + *\n> + * Copyright 2012 Tomer Maimon \n> + *\n> + * The code contained herein is licensed under the GNU General Public\n> + * License. You may obtain a copy of the GNU General Public License\n> + * Version 2 or later at the following locations:\n> + *\n> + * http://www.opensource.org/licenses/gpl-license.html\n> + * http://www.gnu.org/copyleft/gpl.html\n> + */\n> +\n> +/dts-v1/;\n> +#include \"nuvoton-npcm750.dtsi\"\n> +\n> +/ {\n> +\tmodel = \"Nuvoton npcm750 Development Board (Device Tree)\";\n> +\tcompatible = \"nuvoton,npcm750\";\n> +\n> +\tchosen {\n> +\t\tstdout-path = &serial3;\n\nstdout-path is a path string, not a phandle.\n\n> +\t\tbootargs = \"earlyprintk=serial,serial3,115200\";\n\nThat's not valid bootargs with mainline.\n\n> +\t};\n> +\n> +\tmemory {\n> +\t\treg = <0 0x40000000>;\n> +\t};\n> +\n> +\tcpus {\n> +\t\tenable-method = \"nuvoton,npcm7xx-smp\";\n\nThis is not a board specific property. Belongs in the SoC dtsi.\n\n> +\t};\n> +};\n> +\n> +&clk {\n> +\tstatus = \"okay\";\n\nPretty sure you'd always want the clock controller enabled.\n\n> +};\n> +\n> +&watchdog1 {\n> +\tstatus = \"okay\";\n> +};\n> +\n> +&serial0 {\n> +\tstatus = \"okay\";\n> +};\n> +\n> +&serial1 {\n> +\tstatus = \"okay\";\n> +};\n> +\n> +&serial2 {\n> +\tstatus = \"okay\";\n> +};\n> +\n> +&serial3 {\n> +\tstatus = \"okay\";\n> +};\n> diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi\n> new file mode 100644\n> index 000000000000..bca96b3ae9d3\n> --- /dev/null\n> +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi\n> @@ -0,0 +1,177 @@\n> +/*\n> + * DTSi file for the NPCM750 SoC\n> + *\n> + * Copyright 2012 Tomer Maimon \n> + *\n> + * The code contained herein is licensed under the GNU General Public\n> + * License. You may obtain a copy of the GNU General Public License\n> + * Version 2 or later at the following locations:\n> + *\n> + * http://www.opensource.org/licenses/gpl-license.html\n> + * http://www.gnu.org/copyleft/gpl.html\n> + */\n> +\n> +#include \"skeleton.dtsi\"\n\nDon't use skeleton.dtsi. We want to remove it.\n\n> +#include \n> +#include \n> +\n> +/ {\n> +\t#address-cells = <1>;\n> +\t#size-cells = <1>;\n> +\tinterrupt-parent = <&gic>;\n> +\n> +\tcpus {\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\n> +\t\tcpu@0 {\n> +\t\t\tdevice_type = \"cpu\";\n> +\t\t\tcompatible = \"arm,cortex-a9\";\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_CPU>;\n> +\t\t\tclock-names = \"clk_cpu\";\n> +\t\t\treg = <0>;\n> +\t\t\tnext-level-cache = <&l2>;\n> +\t\t};\n> +\n> +\t\tcpu@1 {\n> +\t\t\tdevice_type = \"cpu\";\n> +\t\t\tcompatible = \"arm,cortex-a9\";\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_CPU>;\n> +\t\t\tclock-names = \"clk_cpu\";\n> +\t\t\treg = <1>;\n> +\t\t\tnext-level-cache = <&l2>;\n> +\t\t};\n> +\t};\n> +\n> +\tgcr: gcr@f0800000 {\n> +\t\tcompatible = \"nuvoton,npcm750-gcr\", \"syscon\",\n> +\t\t\t\"simple-mfd\";\n> +\t\treg = <0xf0800000 0x1000>;\n> +\t};\n> +\n> +\tscu: scu@f03fe000 {\n> +\t\tcompatible = \"arm,cortex-a9-scu\";\n> +\t\treg = <0xf03fe000 0x1000>;\n> +\t};\n> +\n> +\tl2: l2-cache@f03fc000 {\n\ncache-controller@...\n\n> +\t\tcompatible = \"arm,pl310-cache\";\n> +\t\treg = <0xf03fc000 0x1000>;\n> +\t\tinterrupts = <0 21 4>;\n> +\t\tcache-unified;\n> +\t\tcache-level = <2>;\n> +\t\tclocks = <&clk NPCM7XX_CLK_AXI>;\n> +\t};\n> +\n> +\tgic: interrupt-controller@f03ff000 {\n> +\t\tcompatible = \"arm,cortex-a9-gic\";\n> +\t\tinterrupt-controller;\n> +\t\t#interrupt-cells = <3>;\n> +\t\treg = <0xf03ff000 0x1000>,\n> +\t\t <0xf03fe100 0x100>;\n> +\t};\n> +\n> +\tclk: clock-controller@f0801000 {\n> +\t\tcompatible = \"nuvoton,npcm750-clk\";\n> +\t\t#clock-cells = <1>;\n> +\t\treg = <0xf0801000 0x1000>;\n> +\t};\n\nAll these memory mapped peripherals should be under a bus/soc node\n\n> +\n> +\t/* external clock signal rg1refck, supplied by the phy */\n> +\tclk-rg1refck {\n> +\t\tcompatible = \"fixed-clock\";\n> +\t\t#clock-cells = <0>;\n> +\t\tclock-frequency = <125000000>;\n> +\t};\n> +\n> +\t/* external clock signal rg2refck, supplied by the phy */\n> +\tclk-rg2refck {\n> +\t\tcompatible = \"fixed-clock\";\n> +\t\t#clock-cells = <0>;\n> +\t\tclock-frequency = <125000000>;\n> +\t};\n> +\n> +\tclk-xin {\n> +\t\tcompatible = \"fixed-clock\";\n> +\t\t#clock-cells = <0>;\n> +\t\tclock-frequency = <50000000>;\n> +\t};\n> +\n> +\ttimer@f03fe600 {\n> +\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n> +\t\treg = <0xf03fe600 0x20>;\n> +\t\tinterrupts = <1 13 0x304>;\n> +\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n> +\t};\n> +\n> +\tapb {\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <1>;\n> +\t\tcompatible = \"simple-bus\";\n> +\t\tinterrupt-parent = <&gic>;\n> +\t\tranges;\n\nIt's preferred to have actual values here and limit the address range of \nthe bus.\n\n> +\n> +\t\ttimer0: timer@f0000000 {\n> +\t\t\tcompatible = \"nuvoton,npcm750-timer\";\n> +\t\t\tinterrupts = <0 32 4>;\n> +\t\t\treg = <0xf0000000 0x1000>;\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n> +\t\t};\n> +\n> +\t\twatchdog0: watchdog@f0008000 {\n> +\t\t\tcompatible = \"nuvoton,npcm750-wdt\";\n> +\t\t\tinterrupts = <0 47 4>;\n> +\t\t\treg = <0xf0008000 0x1000>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n> +\t\t};\n> +\n> +\t\twatchdog1: watchdog@f0009000 {\n> +\t\t\tcompatible = \"nuvoton,npcm750-wdt\";\n> +\t\t\tinterrupts = <0 48 4>;\n> +\t\t\treg = <0xf0009000 0x1000>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n> +\t\t};\n> +\n> +\t\twatchdog2: watchdog@f000a000 {\n> +\t\t\tcompatible = \"nuvoton,npcm750-wdt\";\n> +\t\t\tinterrupts = <0 49 4>;\n> +\t\t\treg = <0xf000a000 0x1000>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n> +\t\t};\n> +\n> +\t\tserial0: serial0@f0001000 {\n> +\t\t\tcompatible = \"nuvoton,npcm750-uart\";\n> +\t\t\treg = <0xf0001000 0x1000>;\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_UART_CORE>;\n> +\t\t\tinterrupts = <0 2 4>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tserial1: serial1@f0002000 {\n> +\t\t\tcompatible = \"nuvoton,npcm750-uart\";\n> +\t\t\treg = <0xf0002000 0x1000>;\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_UART_CORE>;\n> +\t\t\tinterrupts = <0 3 4>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tserial2: serial2@f0003000 {\n> +\t\t\tcompatible = \"nuvoton,npcm750-uart\";\n> +\t\t\treg = <0xf0003000 0x1000>;\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_UART_CORE>;\n> +\t\t\tinterrupts = <0 4 4>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tserial3: serial3@f0004000 {\n> +\t\t\tcompatible = \"nuvoton,npcm750-uart\";\n> +\t\t\treg = <0xf0004000 0x1000>;\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_UART_CORE>;\n> +\t\t\tinterrupts = <0 5 4>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\t};\n> +};\n> diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h\n> new file mode 100644\n> index 000000000000..c69d3bbf7e42\n> --- /dev/null\n> +++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h\n> @@ -0,0 +1,39 @@\n> +/*\n> + * Copyright (C) 2016 Nuvoton Technologies, tali.perry@nuvoton.com\n> + *\n> + * This software is licensed under the terms of the GNU General Public\n> + * License version 2, as published by the Free Software Foundation, and\n> + * may be copied, distributed, and modified under those terms.\n> + */\n> +\n> +#ifndef _DT_BINDINGS_CLK_NPCM7XX_H\n> +#define _DT_BINDINGS_CLK_NPCM7XX_H\n> +\n> +#define NPCM7XX_CLK_PLL0\t0\n> +#define NPCM7XX_CLK_PLL1\t1\n> +#define NPCM7XX_CLK_PLL2\t2\n> +#define NPCM7XX_CLK_GFX\t\t3\n> +#define NPCM7XX_CLK_APB1\t4\n> +#define NPCM7XX_CLK_APB2\t5\n> +#define NPCM7XX_CLK_APB3\t6\n> +#define NPCM7XX_CLK_APB4\t7\n> +#define NPCM7XX_CLK_APB5\t8\n> +#define NPCM7XX_CLK_MC\t\t9\n> +#define NPCM7XX_CLK_CPU\t\t10\n> +#define NPCM7XX_CLK_SPI0\t11\n> +#define NPCM7XX_CLK_SPI3\t12\n> +#define NPCM7XX_CLK_SPIX\t13\n> +#define NPCM7XX_CLK_UART_CORE\t14\n> +#define NPCM7XX_CLK_TIMER\t15\n> +#define NPCM7XX_CLK_HOST_UART\t16\n> +#define NPCM7XX_CLK_MMC\t\t17\n> +#define NPCM7XX_CLK_SDHC\t18\n> +#define NPCM7XX_CLK_ADC\t\t19\n> +#define NPCM7XX_CLK_GFX_MEM\t20\n> +#define NPCM7XX_CLK_USB_BRIDGE\t21\n> +#define NPCM7XX_CLK_AXI\t\t22\n> +#define NPCM7XX_CLK_AHB\t\t23\n> +#define NPCM7XX_CLK_EMC\t\t24\n> +#define NPCM7XX_CLK_GMAC\t25\n> +\n> +#endif\n> -- \n> 2.14.1.581.gf28d330327-goog\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"SZNgY3Wn\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org 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","To":"Brendan Higgins ","Subject":"Re: [PATCH v5 2/3] arm: dts: add Nuvoton NPCM750 device tree","Message-ID":"<20170918194625.xz5y7tkemjnbwunh@rob-hp-laptop>","References":"<20170909015308.30001-1-brendanhiggins@google.com>\n\t<20170909015308.30001-3-brendanhiggins@google.com>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<20170909015308.30001-3-brendanhiggins@google.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170918_124648_075818_EA0DA978 ","X-CRM114-Status":"GOOD ( 19.95 )","X-Spam-Score":"-3.8 (---)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-3.8 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t0.5 RCVD_IN_SORBS_SPAM RBL: SORBS: sender is a spam source\n\t[209.85.223.193 listed in dnsbl.sorbs.net]\n\t-2.8 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2)\n\t[209.85.223.193 listed in wl.mailspike.net]\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [209.85.223.193 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends\n\tin digit (robherring2[at]gmail.com)\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (robherring2[at]gmail.com)\n\t0.0 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level\n\tmail domains are different\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t0.2 FREEMAIL_FORGED_FROMDOMAIN 2nd level domains in From and\n\tEnvelopeFrom freemail headers are different","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, devicetree@vger.kernel.org, f.fainelli@gmail.com, \n\ttmaimon77@gmail.com, avifishman70@gmail.com, openbmc@lists.ozlabs.org,\n\tlinux@armlinux.org.uk, linux-kernel@vger.kernel.org,\n\traltherr@google.com, linux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1770477,"web_url":"http://patchwork.ozlabs.org/comment/1770477/","msgid":"","list_archive_url":null,"date":"2017-09-18T20:37:33","subject":"Re: [PATCH v5 2/3] arm: dts: add Nuvoton NPCM750 device tree","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Mon, Sep 18, 2017 at 2:46 PM, Rob Herring wrote:\n> On Fri, Sep 08, 2017 at 06:53:07PM -0700, Brendan Higgins wrote:\n>> Add a common device tree for all Nuvoton NPCM750 BMCs and a board\n>> specific device tree for the NPCM750 (Poleg) evaluation board.\n\n[...]\n\n>> +/ {\n>> + model = \"Nuvoton npcm750 Development Board (Device Tree)\";\n>> + compatible = \"nuvoton,npcm750\";\n>> +\n>> + chosen {\n>> + stdout-path = &serial3;\n>\n> stdout-path is a path string, not a phandle.\n\nSorry, it's Monday and my brain is not working. This is fine.\n\nRob","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"IRyNoljb\"; dkim-atps=neutral","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=robh@kernel.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwyWf4r3xz9s78\n\tfor ;\n\tTue, 19 Sep 2017 06:38:22 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1du2o7-0000zM-Kg; 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