[{"id":1768143,"web_url":"http://patchwork.ozlabs.org/comment/1768143/","msgid":"<20170913202534.vf4r7dmuyfectbmv@rob-hp-laptop>","list_archive_url":null,"date":"2017-09-13T20:25:34","subject":"Re: [PATCH v2 5/5] devicetree: zynqmp_ps_pcie: Devicetree binding\n\tfor Root DMA","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Fri, Sep 08, 2017 at 05:53:08PM +0530, Ravi Shankar Jonnalagadda wrote:\n> Binding explaining devicetree usage for enabling Root DMA capability\n> \n> Signed-off-by: Ravi Shankar Jonnalagadda \n> Signed-off-by: RaviKiran Gummaluri \n> ---\n> .../devicetree/bindings/dma/xilinx/ps-pcie-dma.txt | 67 ++++++++++++++++++++++\n> 1 file changed, 67 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt\n> \n> diff --git a/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt b/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt\n> new file mode 100644\n> index 0000000..1522a49\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt\n> @@ -0,0 +1,67 @@\n> +* Xilinx PS PCIe Root DMA\n> +\n> +Required properties:\n> +- compatible: Should be \"xlnx,ps_pcie_dma-1.00.a\"\n> +- reg: Register offset for Root DMA channels\n> +- reg-names: Name for the register. Should be \"xlnx,ps_pcie_regbase\"\n\n*-names for a single entry is pointless.\n\n> +- interrupts: Interrupt pin for Root DMA\n> +- interrupt-names: Name for the interrupt. Should be \"xlnx,ps_pcie_rootdma_intr\"\n\nditto\n\n> +- interrupt-parent: Should be gic in case of zynqmp\n> +- xlnx,rootdma: Indicates this platform device is root dma.\n> +\tThis is required as the same platform driver will be invoked by pcie end points too\n\nplatform device and driver are Linux terms.\n\n> +- xlnx,dma_vendorid: 16 bit PCIe device vendor id.\n> +\tThis can be later used by dma client for matching while using dma_request_channel\n> +- xlnx,dma_deviceid: 16 bit PCIe device id\n> +\tThis can be later used by dma client for matching while using dma_request_channel\n\nThis is the id's of the client? Sounds like you should use the DMA \nbinding.\n\n> +- xlnx,numchannels: Indicates number of channels to be enabled for the device.\n> +\tValid values are from 1 to 4 for zynqmp\n\nDMA binding has a similar property.\n\n> +- xlnx,ps_pcie_channel : One for each channel to be enabled.\n\ns/_/-/\n\n> +\tThis array contains channel specific properties.\n> +\tIndex 0: Direction of channel\n> +\t\tDirection of channel can be either PCIe Memory to AXI memory i.e., Host to Card or\n> +\t\tAXI Memory to PCIe memory i.e., Card to Host\n> +\t\tPCIe to AXI Channel Direction is represented as 0x1\n> +\t\tAXI to PCIe Channel Direction is represented as 0x0\n> +\tIndex 1: Number of Buffer Descriptors\n> +\t\tThis number describes number of buffer descriptors to be allocated for a channel\n> +\tIndex 2: Number of Queues\n> +\t\tEach Channel has four DMA Buffer Descriptor Queues.\n> +\t\tBy default All four Queues will be managed by Root DMA driver.\n> +\t\tUser may choose to have only two queues either Source and it's Status Queue or\n> +\t\t\tDestination and it's Status Queue to be handled by Driver.\n> +\t\tThe other two queues need to be handled by user logic which will not be part of this driver.\n> +\t\tAll Queues on Host is represented by 0x4\n> +\t\tTwo Queues on Host is represented by 0x2\n> +\tIndex 3: Coaelse Count\n> +\t\tThis number indicates the number of transfers after which interrupt needs to\n> +\t\tbe raised for the particular channel. The allowed range is from 0 to 255\n> +\tIndex 4: Coaelse Count Timer frequency\n> +\t\tThis property is used to control the frequency of poll timer. Poll timer is\n> +\t\tcreated for a channel whenever coalesce count value (>= 1) is programmed for the particular\n> +\t\tchannel. This timer is helpful in draining out completed transactions even though interrupt is\n> +\t\tnot generated.\n> +\n> +Client Usage:\n> +\tDMA clients can request for these channels using dma_request_channel API\n> +\n> +\n> +Xilinx PS PCIe Root DMA node Example\n> +++++++++++++++++++++++++++++++++++++\n> +\n> +\tpci_rootdma: rootdma@fd0f0000 {\n\ndma-controller@...\n\n> +\t\tcompatible = \"xlnx,ps_pcie_dma-1.00.a\";\n> +\t\treg = <0x0 0xfd0f0000 0x0 0x1000>;\n> +\t\treg-names = \"xlnx,ps_pcie_regbase\";\n> +\t\tinterrupts = <0 117 4>;\n> +\t\tinterrupt-names = \"xlnx,ps_pcie_rootdma_intr\";\n> +\t\tinterrupt-parent = <&gic>;\n> +\t\txlnx,rootdma;\n> +\t\txlnx,dma_vendorid = /bits/ 16 <0x10EE>;\n> +\t\txlnx,dma_deviceid = /bits/ 16 <0xD021>;\n> +\t\txlnx,numchannels = <0x4>;\n> +\t\t#size-cells = <0x5>;\n> +\t\txlnx,ps_pcie_channel0 = <0x1 0x7CF 0x4 0x0 0x3E8>;\n> +\t\txlnx,ps_pcie_channel1 = <0x0 0x7CF 0x4 0x0 0x3E8>;\n> +\t\txlnx,ps_pcie_channel2 = <0x1 0x7CF 0x4 0x0 0x3E8>;\n> +\t\txlnx,ps_pcie_channel3 = <0x0 0x7CF 0x4 0x0 0x3E8>;\n> + };\n> -- \n> 2.7.4\n> \n> --\n> To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n> the body of a message to majordomo@vger.kernel.org\n> More majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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\n\tWed, 13 Sep 2017 13:25:35 -0700 (PDT)","Date":"Wed, 13 Sep 2017 15:25:34 -0500","From":"Rob Herring ","To":"Ravi Shankar Jonnalagadda ","Subject":"Re: [PATCH v2 5/5] devicetree: zynqmp_ps_pcie: Devicetree binding\n\tfor Root DMA","Message-ID":"<20170913202534.vf4r7dmuyfectbmv@rob-hp-laptop>","References":"<1504873388-29195-1-git-send-email-vjonnal@xilinx.com>\n\t<1504873388-29195-7-git-send-email-vjonnal@xilinx.com>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<1504873388-29195-7-git-send-email-vjonnal@xilinx.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170913_132557_642595_EFF125B1 ","X-CRM114-Status":"GOOD ( 23.52 )","X-Spam-Score":"-3.8 (---)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-3.8 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [209.85.223.193 listed in list.dnswl.org]\n\t0.5 RCVD_IN_SORBS_SPAM RBL: SORBS: sender is a spam source\n\t[209.85.223.193 listed in dnsbl.sorbs.net]\n\t-2.8 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2)\n\t[209.85.223.193 listed in wl.mailspike.net]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends\n\tin digit (robherring2[at]gmail.com)\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (robherring2[at]gmail.com)\n\t0.0 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level\n\tmail domains are different\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t0.2 FREEMAIL_FORGED_FROMDOMAIN 2nd level domains in From and\n\tEnvelopeFrom freemail headers are different","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, devicetree@vger.kernel.org,\n\tlorenzo.pieralisi@arm.com, \n\tdmaengine@vger.kernel.org, vinod.koul@intel.com,\n\tlinux-pci@vger.kernel.org, \n\tmichal.simek@xilinx.com, linux-kernel@vger.kernel.org,\n\tvjonnal@xilinx.com, \n\trgummal@xilinx.com, linux-arm-kernel@lists.infradead.org,\n\tbhelgaas@google.com, \n\tdan.j.williams@intel.com, bharat.kumar.gogada@xilinx.com,\n\tsoren.brinkmann@xilinx.com","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1771321,"web_url":"http://patchwork.ozlabs.org/comment/1771321/","msgid":"<20170919193635.GE22312@bhelgaas-glaptop.roam.corp.google.com>","list_archive_url":null,"date":"2017-09-19T19:36:35","subject":"Re: [PATCH v2 1/5] PCI:xilinx-nwl: Enable Root DMA","submitter":{"id":67298,"url":"http://patchwork.ozlabs.org/api/people/67298/","name":"Bjorn Helgaas","email":"helgaas@kernel.org"},"content":"Hi Ravi,\n\nPlease make the subject line follow the existing convention, i.e., run\n\n $ git log --oneline drivers/pci/host/pcie-xilinx-nwl.c\n\nand make yours match spacing, capitalization, and style (imperative\nsentence).\n\nAlso waiting for ack from Michal.\n\nOn Fri, Sep 08, 2017 at 05:53:03PM +0530, Ravi Shankar Jonnalagadda wrote:\n> Enabling Root DMA interrupts\n> \n> Adding Root DMA translations to bridge for Register Access\n> \n> Signed-off-by: Ravi Shankar Jonnalagadda \n> Signed-off-by: RaviKiran Gummaluri \n> ---\n> drivers/pci/host/pcie-xilinx-nwl.c | 15 +++++++++++++++\n> 1 file changed, 15 insertions(+)\n> \n> diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c\n> index eec641a..5766582 100644\n> --- a/drivers/pci/host/pcie-xilinx-nwl.c\n> +++ b/drivers/pci/host/pcie-xilinx-nwl.c\n> @@ -39,6 +39,11 @@\n> #define E_ECAM_CONTROL\t\t\t0x00000228\n> #define E_ECAM_BASE_LO\t\t\t0x00000230\n> #define E_ECAM_BASE_HI\t\t\t0x00000234\n> +#define E_DREG_CTRL\t\t\t0x00000288\n> +#define E_DREG_BASE_LO\t\t\t0x00000290\n> +\n> +#define DREG_DMA_EN\t\t\tBIT(0)\n> +#define DREG_DMA_BASE_LO\t\t0xFD0F0000\n> \n> /* Ingress - address translations */\n> #define I_MSII_CAPABILITIES\t\t0x00000300\n> @@ -57,6 +62,10 @@\n> #define MSGF_MSI_STATUS_HI\t\t0x00000444\n> #define MSGF_MSI_MASK_LO\t\t0x00000448\n> #define MSGF_MSI_MASK_HI\t\t0x0000044C\n> +/* Root DMA Interrupt register */\n> +#define MSGF_DMA_MASK\t\t\t0x00000464\n> +\n> +#define MSGF_INTR_EN\t\t\tBIT(0)\n> \n> /* Msg filter mask bits */\n> #define CFG_ENABLE_PM_MSG_FWD\t\tBIT(1)\n> @@ -766,6 +775,12 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)\n> \tnwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &\n> \t\t\t MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);\n> \n> +\t/* Enabling DREG translations */\n> +\tnwl_bridge_writel(pcie, DREG_DMA_EN, E_DREG_CTRL);\n> +\tnwl_bridge_writel(pcie, DREG_DMA_BASE_LO, E_DREG_BASE_LO);\n> +\t/* Enabling Root DMA interrupts */\n> +\tnwl_bridge_writel(pcie, MSGF_INTR_EN, MSGF_DMA_MASK);\n> +\n> \t/* Enable all legacy interrupts */\n> \tnwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);\n> \n> -- \n> 2.7.4\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1771586,"web_url":"http://patchwork.ozlabs.org/comment/1771586/","msgid":"<1e17381d-0e60-e563-4f74-96245fe00aaf@monstr.eu>","list_archive_url":null,"date":"2017-09-20T05:49:19","subject":"Re: [PATCH v2 3/5] dmaengine: zynqmp_ps_pcie: Adding PS PCIe DMA\n\tdriver","submitter":{"id":2237,"url":"http://patchwork.ozlabs.org/api/people/2237/","name":"Michal Simek","email":"monstr@monstr.eu"},"content":"On 8.9.2017 14:23, Ravi Shankar Jonnalagadda wrote:\n> Adding support for ZynqmMP PS PCIe EP driver.\n> Adding support for ZynqmMP PS PCIe Root DMA driver.\n> Modifying Kconfig and Makefile to add the support.\n> \n> Signed-off-by: Ravi Shankar Jonnalagadda \n> Signed-off-by: RaviKiran Gummaluri \n> ---\n> drivers/dma/Kconfig | 12 +++\n> drivers/dma/xilinx/Makefile | 2 +\n> drivers/dma/xilinx/ps_pcie.h | 44 +++++++++\n> drivers/dma/xilinx/ps_pcie_main.c | 200 ++++++++++++++++++++++++++++++++++++++\n> include/linux/dma/ps_pcie_dma.h | 69 +++++++++++++\n> 5 files changed, 327 insertions(+)\n> create mode 100644 drivers/dma/xilinx/ps_pcie.h\n> create mode 100644 drivers/dma/xilinx/ps_pcie_main.c\n> create mode 100644 include/linux/dma/ps_pcie_dma.h\n> \n> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig\n> index fa8f9c0..e2fe4e5 100644\n> --- a/drivers/dma/Kconfig\n> +++ b/drivers/dma/Kconfig\n> @@ -586,6 +586,18 @@ config XILINX_ZYNQMP_DMA\n> \thelp\n> \t Enable support for Xilinx ZynqMP DMA controller.\n> \n> +config XILINX_PS_PCIE_DMA\n> +\ttristate \"Xilinx PS PCIe DMA support\"\n> +\tdepends on (PCI && X86_64 || ARM64)\n> +\tselect DMA_ENGINE\n> +\thelp\n> +\t Enable support for the Xilinx PS PCIe DMA engine present\n> +\t in recent Xilinx ZynqMP chipsets.\n> +\n> +\t Say Y here if you have such a chipset.\n> +\n> +\t If unsure, say N.\n> +\n> config ZX_DMA\n> \ttristate \"ZTE ZX DMA support\"\n> \tdepends on ARCH_ZX || COMPILE_TEST\n> diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile\n> index 9e91f8f..04f6f99 100644\n> --- a/drivers/dma/xilinx/Makefile\n> +++ b/drivers/dma/xilinx/Makefile\n> @@ -1,2 +1,4 @@\n> obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o\n> obj-$(CONFIG_XILINX_ZYNQMP_DMA) += zynqmp_dma.o\n> +ps_pcie_dma-objs := ps_pcie_main.o ps_pcie_platform.o\n> +obj-$(CONFIG_XILINX_PS_PCIE_DMA) += ps_pcie_dma.o\n> diff --git a/drivers/dma/xilinx/ps_pcie.h b/drivers/dma/xilinx/ps_pcie.h\n> new file mode 100644\n> index 0000000..351f051\n> --- /dev/null\n> +++ b/drivers/dma/xilinx/ps_pcie.h\n> @@ -0,0 +1,44 @@\n> +/*\n> + * Xilinx PS PCIe DMA Engine platform header file\n> + *\n> + * Copyright (C) 2010-2017 Xilinx, Inc. All rights reserved.\n> + *\n> + * This program is free software: you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation\n> + */\n> +\n> +#ifndef __XILINX_PS_PCIE_H\n> +#define __XILINX_PS_PCIE_H\n> +\n> +#include \n> +#include \n\nthis is included via dma-mapping.h below.\n\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n\nthis is already include via of.h\n\n> +#include \n> +#include \n> +#include \n\nDon't we have any script for checking this?\n\n> +\n> +/**\n> + * dma_platform_driver_register - This will be invoked by module init\n> + *\n> + * Return: returns status of platform_driver_register\n> + */\n> +int dma_platform_driver_register(void);\n\n\nput empty line here.\n\n> +/**\n> + * dma_platform_driver_unregister - This will be invoked by module exit\n> + *\n> + * Return: returns void after unregustering platform driver\n> + */\n> +void dma_platform_driver_unregister(void);\n> +\n> +#endif\n> diff --git a/drivers/dma/xilinx/ps_pcie_main.c b/drivers/dma/xilinx/ps_pcie_main.c\n> new file mode 100644\n> index 0000000..4ccd8ef\n> --- /dev/null\n> +++ b/drivers/dma/xilinx/ps_pcie_main.c\n> @@ -0,0 +1,200 @@\n> +/*\n> + * XILINX PS PCIe driver\n> + *\n> + * Copyright (C) 2017 Xilinx, Inc. All rights reserved.\n> + *\n> + * Description\n> + * PS PCIe DMA is memory mapped DMA used to execute PS to PL transfers\n> + * on ZynqMP UltraScale+ Devices.\n> + * This PCIe driver creates a platform device with specific platform\n> + * info enabling creation of DMA device corresponding to the channel\n> + * information provided in the properties\n> + *\n> + * This program is free software: you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation\n> + */\n> +\n> +#include \"ps_pcie.h\"\n> +#include \"../dmaengine.h\"\n> +\n> +#define DRV_MODULE_NAME\t\t \"ps_pcie_dma\"\n> +\n> +static int ps_pcie_dma_probe(struct pci_dev *pdev,\n> +\t\t\t const struct pci_device_id *ent);\n> +static void ps_pcie_dma_remove(struct pci_dev *pdev);\n> +\n> +static u32 channel_properties_pcie_axi[] = {\n> +\t(u32)(PCIE_AXI_DIRECTION), (u32)(NUMBER_OF_BUFFER_DESCRIPTORS),\n> +\t(u32)(DEFAULT_DMA_QUEUES), (u32)(CHANNEL_COAELSE_COUNT),\n> +\t(u32)(CHANNEL_POLL_TIMER_FREQUENCY) };\n> +\n> +static u32 channel_properties_axi_pcie[] = {\n> +\t(u32)(AXI_PCIE_DIRECTION), (u32)(NUMBER_OF_BUFFER_DESCRIPTORS),\n> +\t(u32)(DEFAULT_DMA_QUEUES), (u32)(CHANNEL_COAELSE_COUNT),\n> +\t(u32)(CHANNEL_POLL_TIMER_FREQUENCY) };\n> +\n> +static struct property_entry generic_pcie_ep_property[] = {\n> +\tPROPERTY_ENTRY_U32(\"numchannels\", (u32)MAX_NUMBER_OF_CHANNELS),\n> +\tPROPERTY_ENTRY_U32_ARRAY(\"ps_pcie_channel0\",\n> +\t\t\t\t channel_properties_pcie_axi),\n> +\tPROPERTY_ENTRY_U32_ARRAY(\"ps_pcie_channel1\",\n> +\t\t\t\t channel_properties_axi_pcie),\n> +\tPROPERTY_ENTRY_U32_ARRAY(\"ps_pcie_channel2\",\n> +\t\t\t\t channel_properties_pcie_axi),\n> +\tPROPERTY_ENTRY_U32_ARRAY(\"ps_pcie_channel3\",\n> +\t\t\t\t channel_properties_axi_pcie),\n> +\t{ },\n> +};\n> +\n> +static const struct platform_device_info xlnx_std_platform_dev_info = {\n> +\t.name = XLNX_PLATFORM_DRIVER_NAME,\n> +\t.properties = generic_pcie_ep_property,\n> +};\n> +\n> +/**\n> + * ps_pcie_dma_probe - Driver probe function\n> + * @pdev: Pointer to the pci_dev structure\n> + * @ent: pci device id\n> + *\n> + * Return: '0' on success and failure value on error\n> + */\n> +static int ps_pcie_dma_probe(struct pci_dev *pdev,\n> +\t\t\t const struct pci_device_id *ent)\n> +{\n> +\tint err;\n> +\tstruct platform_device *platform_dev;\n> +\tstruct platform_device_info platform_dev_info;\n> +\n> +\tdev_info(&pdev->dev, \"PS PCIe DMA Driver probe\\n\");\n> +\n> +\terr = pcim_enable_device(pdev);\n> +\tif (err) {\n> +\t\tdev_err(&pdev->dev, \"Cannot enable PCI device, aborting\\n\");\n> +\t\treturn err;\n> +\t}\n> +\n> +\terr = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));\n> +\tif (err) {\n> +\t\tdev_info(&pdev->dev, \"Cannot set 64 bit DMA mask\\n\");\n> +\t\terr = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));\n> +\t\tif (err) {\n> +\t\t\tdev_err(&pdev->dev, \"DMA mask set error\\n\");\n> +\t\t\treturn err;\n> +\t\t}\n> +\t}\n> +\n> +\terr = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));\n> +\tif (err) {\n> +\t\tdev_info(&pdev->dev, \"Cannot set 64 bit consistent DMA mask\\n\");\n> +\t\terr = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));\n> +\t\tif (err) {\n> +\t\t\tdev_err(&pdev->dev, \"Cannot set consistent DMA mask\\n\");\n> +\t\t\treturn err;\n> +\t\t}\n> +\t}\n> +\n> +\tpci_set_master(pdev);\n> +\n> +\t/* For Root DMA platform device will be created through device tree */\n> +\tif (pdev->vendor == PCI_VENDOR_ID_XILINX &&\n> +\t pdev->device == ZYNQMP_RC_DMA_DEVID)\n> +\t\treturn 0;\n> +\n> +\tmemcpy(&platform_dev_info, &xlnx_std_platform_dev_info,\n> +\t sizeof(xlnx_std_platform_dev_info));\n> +\n> +\t/* Do device specific channel configuration changes to\n> +\t * platform_dev_info.properties if required\n> +\t * More information on channel properties can be found\n> +\t * at Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt\n> +\t */\n> +\n> +\tplatform_dev_info.parent = &pdev->dev;\n> +\tplatform_dev_info.data = &pdev;\n> +\tplatform_dev_info.size_data = sizeof(struct pci_dev **);\n> +\n> +\tplatform_dev = platform_device_register_full(&platform_dev_info);\n> +\tif (IS_ERR(platform_dev)) {\n> +\t\tdev_err(&pdev->dev,\n> +\t\t\t\"Cannot create platform device, aborting\\n\");\n> +\t\treturn PTR_ERR(platform_dev);\n> +\t}\n> +\n> +\tpci_set_drvdata(pdev, platform_dev);\n> +\n> +\tdev_info(&pdev->dev, \"PS PCIe DMA driver successfully probed\\n\");\n> +\n> +\treturn 0;\n> +}\n> +\n> +static struct pci_device_id ps_pcie_dma_tbl[] = {\n> +\t{ PCI_DEVICE(PCI_VENDOR_ID_XILINX, ZYNQMP_DMA_DEVID) },\n> +\t{ PCI_DEVICE(PCI_VENDOR_ID_XILINX, ZYNQMP_RC_DMA_DEVID) },\n> +\t{ }\n> +};\n> +\n> +static struct pci_driver ps_pcie_dma_driver = {\n> +\t.name = DRV_MODULE_NAME,\n> +\t.id_table = ps_pcie_dma_tbl,\n> +\t.probe = ps_pcie_dma_probe,\n> +\t.remove = ps_pcie_dma_remove,\n> +};\n> +\n> +/**\n> + * ps_pcie_init - Driver init function\n> + *\n> + * Return: 0 on success. Non zero on failure\n> + */\n> +static int __init ps_pcie_init(void)\n> +{\n> +\tint ret;\n> +\n> +\tpr_info(\"%s init()\\n\", DRV_MODULE_NAME);\n> +\n> +\tret = pci_register_driver(&ps_pcie_dma_driver);\n> +\tif (ret)\n> +\t\treturn ret;\n> +\n> +\tret = dma_platform_driver_register();\n> +\tif (ret)\n> +\t\tpci_unregister_driver(&ps_pcie_dma_driver);\n> +\n> +\treturn ret;\n> +}\n> +\n> +/**\n> + * ps_pcie_dma_remove - Driver remove function\n> + * @pdev: Pointer to the pci_dev structure\n> + *\n> + * Return: void\n> + */\n> +static void ps_pcie_dma_remove(struct pci_dev *pdev)\n> +{\n> +\tstruct platform_device *platform_dev;\n> +\n> +\tplatform_dev = (struct platform_device *)pci_get_drvdata(pdev);\n> +\n> +\tif (platform_dev)\n> +\t\tplatform_device_unregister(platform_dev);\n> +}\n> +\n> +/**\n> + * ps_pcie_exit - Driver exit function\n> + *\n> + * Return: void\n> + */\n> +static void __exit ps_pcie_exit(void)\n> +{\n> +\tpr_info(\"%s exit()\\n\", DRV_MODULE_NAME);\n> +\n> +\tdma_platform_driver_unregister();\n> +\tpci_unregister_driver(&ps_pcie_dma_driver);\n> +}\n> +\n> +module_init(ps_pcie_init);\n> +module_exit(ps_pcie_exit);\n> +\n> +MODULE_AUTHOR(\"Xilinx Inc\");\n> +MODULE_DESCRIPTION(\"Xilinx PS PCIe DMA Driver\");\n> +MODULE_LICENSE(\"GPL v2\");\n> diff --git a/include/linux/dma/ps_pcie_dma.h b/include/linux/dma/ps_pcie_dma.h\n> new file mode 100644\n> index 0000000..d11323a\n> --- /dev/null\n> +++ b/include/linux/dma/ps_pcie_dma.h\n> @@ -0,0 +1,69 @@\n> +/*\n> + * Xilinx PS PCIe DMA Engine support header file\n> + *\n> + * Copyright (C) 2017 Xilinx, Inc. All rights reserved.\n> + *\n> + * This program is free software: you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation\n> + */\n> +\n> +#ifndef __DMA_XILINX_PS_PCIE_H\n> +#define __DMA_XILINX_PS_PCIE_H\n> +\n> +#include \n> +#include \n> +\n> +#define XLNX_PLATFORM_DRIVER_NAME \"xlnx-platform-dma-driver\"\n> +\n> +#define ZYNQMP_DMA_DEVID\t(0xD024)\n> +#define ZYNQMP_RC_DMA_DEVID\t(0xD021)\n\n\nAre these hardcoded? If yes, maybe we have better location where these\nshould be put.\n\n\n> +\n> +#define MAX_ALLOWED_CHANNELS_IN_HW\t4\n> +\n> +#define MAX_NUMBER_OF_CHANNELS\tMAX_ALLOWED_CHANNELS_IN_HW\n> +\n> +#define DEFAULT_DMA_QUEUES\t4\n> +#define TWO_DMA_QUEUES\t\t2\n> +\n> +#define NUMBER_OF_BUFFER_DESCRIPTORS\t1999\n> +#define MAX_DESCRIPTORS\t\t\t65536\n> +\n> +#define CHANNEL_COAELSE_COUNT\t\t0\n> +\n> +#define CHANNEL_POLL_TIMER_FREQUENCY\t1000 /* in milli seconds */\n> +\n> +#define PCIE_AXI_DIRECTION\tDMA_TO_DEVICE\n> +#define AXI_PCIE_DIRECTION\tDMA_FROM_DEVICE\n> +\n> +/**\n> + * struct BAR_PARAMS - PCIe Bar Parameters\n> + * @BAR_PHYS_ADDR: PCIe BAR Physical address\n> + * @BAR_LENGTH: Length of PCIe BAR\n> + * @BAR_VIRT_ADDR: Virtual Address to access PCIe BAR\n> + */\n> +struct BAR_PARAMS {\n> +\tdma_addr_t BAR_PHYS_ADDR; /**< Base physical address of BAR memory */\n> +\tunsigned long BAR_LENGTH; /**< Length of BAR memory window */\n> +\tvoid *BAR_VIRT_ADDR; /**< Virtual Address of mapped BAR memory */\n> +};\n> +\n> +/**\n> + * struct ps_pcie_dma_channel_match - Match structure for dma clients\n> + * @pci_vendorid: PCIe Vendor id of PS PCIe DMA device\n> + * @pci_deviceid: PCIe Device id of PS PCIe DMA device\n> + * @board_number: Unique id to identify individual device in a system\n> + * @channel_number: Unique channel number of the device\n> + * @direction: DMA channel direction\n> + * @bar_params: Pointer to BAR_PARAMS for accessing application specific data\n> + */\n> +struct ps_pcie_dma_channel_match {\n> +\tu16 pci_vendorid;\n> +\tu16 pci_deviceid;\n> +\tu16 board_number;\n> +\tu16 channel_number;\n> +\tenum dma_data_direction direction;\n> +\tstruct BAR_PARAMS *bar_params;\n> +};\n> +\n> +#endif\n> \n\nThanks,\nMichal","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1504873388-29195-4-git-send-email-vjonnal@xilinx.com>","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170919_224955_643088_29B4CC61 ","X-CRM114-Status":"GOOD ( 26.63 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2a00:1450:400c:c0c:0:0:0:243 listed in] [list.dnswl.org]\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Reply-To":"monstr@monstr.eu","Content-Type":"multipart/mixed;\n\tboundary=\"===============5313353175574641248==\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1775729,"web_url":"http://patchwork.ozlabs.org/comment/1775729/","msgid":"<20170926173207.GR30097@localhost>","list_archive_url":null,"date":"2017-09-26T17:32:07","subject":"Re: [PATCH v2 3/5] dmaengine: zynqmp_ps_pcie: Adding PS PCIe DMA\n\tdriver","submitter":{"id":8232,"url":"http://patchwork.ozlabs.org/api/people/8232/","name":"Vinod Koul","email":"vinod.koul@intel.com"},"content":"On Fri, Sep 08, 2017 at 05:53:05PM +0530, Ravi Shankar Jonnalagadda wrote:\n\n> Adding support for ZynqmMP PS PCIe EP driver.\n> Adding support for ZynqmMP PS PCIe Root DMA driver.\n\n/s/Adding/Add/\n\nPlease descibe the dmaengines here so people can know what to expect.\n\n> Modifying Kconfig and Makefile to add the support.\n\nYou can remobe this\n\n> \n> Signed-off-by: Ravi Shankar Jonnalagadda \n> Signed-off-by: RaviKiran Gummaluri \n> ---\n> drivers/dma/Kconfig | 12 +++\n> drivers/dma/xilinx/Makefile | 2 +\n> drivers/dma/xilinx/ps_pcie.h | 44 +++++++++\n> drivers/dma/xilinx/ps_pcie_main.c | 200 ++++++++++++++++++++++++++++++++++++++\n> include/linux/dma/ps_pcie_dma.h | 69 +++++++++++++\n> 5 files changed, 327 insertions(+)\n> create mode 100644 drivers/dma/xilinx/ps_pcie.h\n> create mode 100644 drivers/dma/xilinx/ps_pcie_main.c\n> create mode 100644 include/linux/dma/ps_pcie_dma.h\n> \n> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig\n> index fa8f9c0..e2fe4e5 100644\n> --- a/drivers/dma/Kconfig\n> +++ b/drivers/dma/Kconfig\n> @@ -586,6 +586,18 @@ config XILINX_ZYNQMP_DMA\n> \thelp\n> \t Enable support for Xilinx ZynqMP DMA controller.\n> \n> +config XILINX_PS_PCIE_DMA\n> +\ttristate \"Xilinx PS PCIe DMA support\"\n> +\tdepends on (PCI && X86_64 || ARM64)\n> +\tselect DMA_ENGINE\n> +\thelp\n> +\t Enable support for the Xilinx PS PCIe DMA engine present\n> +\t in recent Xilinx ZynqMP chipsets.\n> +\n> +\t Say Y here if you have such a chipset.\n> +\n> +\t If unsure, say N.\n\nCan you remove last two lines, they dont convey anything useful\n\n> +\n> config ZX_DMA\n> \ttristate \"ZTE ZX DMA support\"\n> \tdepends on ARCH_ZX || COMPILE_TEST\n> diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile\n> index 9e91f8f..04f6f99 100644\n> --- a/drivers/dma/xilinx/Makefile\n> +++ b/drivers/dma/xilinx/Makefile\n> @@ -1,2 +1,4 @@\n> obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o\n> obj-$(CONFIG_XILINX_ZYNQMP_DMA) += zynqmp_dma.o\n> +ps_pcie_dma-objs := ps_pcie_main.o ps_pcie_platform.o\n> +obj-$(CONFIG_XILINX_PS_PCIE_DMA) += ps_pcie_dma.o\n> diff --git a/drivers/dma/xilinx/ps_pcie.h b/drivers/dma/xilinx/ps_pcie.h\n> new file mode 100644\n> index 0000000..351f051\n> --- /dev/null\n> +++ b/drivers/dma/xilinx/ps_pcie.h\n> @@ -0,0 +1,44 @@\n> +/*\n> + * Xilinx PS PCIe DMA Engine platform header file\n> + *\n> + * Copyright (C) 2010-2017 Xilinx, Inc. All rights reserved.\n> + *\n> + * This program is free software: you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation\n> + */\n> +\n> +#ifndef __XILINX_PS_PCIE_H\n> +#define __XILINX_PS_PCIE_H\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n\nDo you really need all these headers\n\n> +\n> +/**\n> + * dma_platform_driver_register - This will be invoked by module init\n> + *\n> + * Return: returns status of platform_driver_register\n> + */\n> +int dma_platform_driver_register(void);\n> +/**\n> + * dma_platform_driver_unregister - This will be invoked by module exit\n> + *\n> + * Return: returns void after unregustering platform driver\n\ntypo, please run spell checker & checkpatch on your patches\n\n> + */\n> +void dma_platform_driver_unregister(void);\n> +\n> +#endif\n> diff --git a/drivers/dma/xilinx/ps_pcie_main.c b/drivers/dma/xilinx/ps_pcie_main.c\n> new file mode 100644\n> index 0000000..4ccd8ef\n> --- /dev/null\n> +++ b/drivers/dma/xilinx/ps_pcie_main.c\n> @@ -0,0 +1,200 @@\n> +/*\n> + * XILINX PS PCIe driver\n> + *\n> + * Copyright (C) 2017 Xilinx, Inc. All rights reserved.\n> + *\n> + * Description\n> + * PS PCIe DMA is memory mapped DMA used to execute PS to PL transfers\n> + * on ZynqMP UltraScale+ Devices.\n> + * This PCIe driver creates a platform device with specific platform\n> + * info enabling creation of DMA device corresponding to the channel\n> + * information provided in the properties\n> + *\n> + * This program is free software: you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation\n> + */\n> +\n> +#include \"ps_pcie.h\"\n> +#include \"../dmaengine.h\"\n> +\n> +#define DRV_MODULE_NAME\t\t \"ps_pcie_dma\"\n> +\n> +static int ps_pcie_dma_probe(struct pci_dev *pdev,\n> +\t\t\t const struct pci_device_id *ent);\n> +static void ps_pcie_dma_remove(struct pci_dev *pdev);\n\nwhy do you need fwd declarations of these?\n\n> +\n> +static u32 channel_properties_pcie_axi[] = {\n> +\t(u32)(PCIE_AXI_DIRECTION), (u32)(NUMBER_OF_BUFFER_DESCRIPTORS),\n> +\t(u32)(DEFAULT_DMA_QUEUES), (u32)(CHANNEL_COAELSE_COUNT),\n> +\t(u32)(CHANNEL_POLL_TIMER_FREQUENCY) };\n\nwhy the casts?\n\n> +\n> +static u32 channel_properties_axi_pcie[] = {\n> +\t(u32)(AXI_PCIE_DIRECTION), (u32)(NUMBER_OF_BUFFER_DESCRIPTORS),\n> +\t(u32)(DEFAULT_DMA_QUEUES), (u32)(CHANNEL_COAELSE_COUNT),\n> +\t(u32)(CHANNEL_POLL_TIMER_FREQUENCY) };\n> +\n> +static struct property_entry generic_pcie_ep_property[] = {\n> +\tPROPERTY_ENTRY_U32(\"numchannels\", (u32)MAX_NUMBER_OF_CHANNELS),\n> +\tPROPERTY_ENTRY_U32_ARRAY(\"ps_pcie_channel0\",\n> +\t\t\t\t channel_properties_pcie_axi),\n> +\tPROPERTY_ENTRY_U32_ARRAY(\"ps_pcie_channel1\",\n> +\t\t\t\t channel_properties_axi_pcie),\n> +\tPROPERTY_ENTRY_U32_ARRAY(\"ps_pcie_channel2\",\n> +\t\t\t\t channel_properties_pcie_axi),\n> +\tPROPERTY_ENTRY_U32_ARRAY(\"ps_pcie_channel3\",\n> +\t\t\t\t channel_properties_axi_pcie),\n> +\t{ },\n> +};\n> +\n> +static const struct platform_device_info xlnx_std_platform_dev_info = {\n> +\t.name = XLNX_PLATFORM_DRIVER_NAME,\n> +\t.properties = generic_pcie_ep_property,\n> +};\n> +\n> +/**\n> + * ps_pcie_dma_probe - Driver probe function\n> + * @pdev: Pointer to the pci_dev structure\n> + * @ent: pci device id\n> + *\n> + * Return: '0' on success and failure value on error\n> + */\n\nI didnt get any useful info from this, pls get rid of these where they dont\nhelp anyone...\n\n> +static int ps_pcie_dma_probe(struct pci_dev *pdev,\n> +\t\t\t const struct pci_device_id *ent)\n> +{\n> +\tint err;\n> +\tstruct platform_device *platform_dev;\n> +\tstruct platform_device_info platform_dev_info;\n\nhelps reading if these are reverse christmas tree!\n\n> +\n> +\tdev_info(&pdev->dev, \"PS PCIe DMA Driver probe\\n\");\n\nuseless, pls remove\n\n> +\n> +\terr = pcim_enable_device(pdev);\n> +\tif (err) {\n> +\t\tdev_err(&pdev->dev, \"Cannot enable PCI device, aborting\\n\");\n> +\t\treturn err;\n> +\t}\n> +\n> +\terr = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));\n> +\tif (err) {\n> +\t\tdev_info(&pdev->dev, \"Cannot set 64 bit DMA mask\\n\");\n> +\t\terr = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));\n> +\t\tif (err) {\n> +\t\t\tdev_err(&pdev->dev, \"DMA mask set error\\n\");\n\nno disable device on err?\n\n> +\t\t\treturn err;\n> +\t\t}\n> +\t}\n> +\n> +\terr = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));\n> +\tif (err) {\n> +\t\tdev_info(&pdev->dev, \"Cannot set 64 bit consistent DMA mask\\n\");\n> +\t\terr = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));\n> +\t\tif (err) {\n> +\t\t\tdev_err(&pdev->dev, \"Cannot set consistent DMA mask\\n\");\n> +\t\t\treturn err;\n> +\t\t}\n> +\t}\n> +\n> +\tpci_set_master(pdev);\n> +\n> +\t/* For Root DMA platform device will be created through device tree */\n> +\tif (pdev->vendor == PCI_VENDOR_ID_XILINX &&\n> +\t pdev->device == ZYNQMP_RC_DMA_DEVID)\n> +\t\treturn 0;\n\nthe indentations are terrible!\n\nWhy regiser for this ID then? Return 0 would be success, so not sure what\nyou are trying to do here?\n\n\n> +\n> +\tmemcpy(&platform_dev_info, &xlnx_std_platform_dev_info,\n> +\t sizeof(xlnx_std_platform_dev_info));\n> +\n> +\t/* Do device specific channel configuration changes to\n> +\t * platform_dev_info.properties if required\n> +\t * More information on channel properties can be found\n> +\t * at Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt\n> +\t */\n\n/*\n * kernel code expects multiline\n * comments like this\n */\n\n> +\n> +\tplatform_dev_info.parent = &pdev->dev;\n> +\tplatform_dev_info.data = &pdev;\n> +\tplatform_dev_info.size_data = sizeof(struct pci_dev **);\n\n??\n\n> +\n> +\tplatform_dev = platform_device_register_full(&platform_dev_info);\n> +\tif (IS_ERR(platform_dev)) {\n> +\t\tdev_err(&pdev->dev,\n> +\t\t\t\"Cannot create platform device, aborting\\n\");\n> +\t\treturn PTR_ERR(platform_dev);\n> +\t}\n> +\n> +\tpci_set_drvdata(pdev, platform_dev);\n> +\n> +\tdev_info(&pdev->dev, \"PS PCIe DMA driver successfully probed\\n\");\n> +\n> +\treturn 0;\n> +}\n> +\n> +static struct pci_device_id ps_pcie_dma_tbl[] = {\n> +\t{ PCI_DEVICE(PCI_VENDOR_ID_XILINX, ZYNQMP_DMA_DEVID) },\n> +\t{ PCI_DEVICE(PCI_VENDOR_ID_XILINX, ZYNQMP_RC_DMA_DEVID) },\n> +\t{ }\n> +};\n> +\n> +static struct pci_driver ps_pcie_dma_driver = {\n> +\t.name = DRV_MODULE_NAME,\n> +\t.id_table = ps_pcie_dma_tbl,\n> +\t.probe = ps_pcie_dma_probe,\n> +\t.remove = ps_pcie_dma_remove,\n> +};\n> +\n> +/**\n> + * ps_pcie_init - Driver init function\n> + *\n> + * Return: 0 on success. Non zero on failure\n> + */\n> +static int __init ps_pcie_init(void)\n> +{\n> +\tint ret;\n> +\n> +\tpr_info(\"%s init()\\n\", DRV_MODULE_NAME);\n> +\n> +\tret = pci_register_driver(&ps_pcie_dma_driver);\n> +\tif (ret)\n> +\t\treturn ret;\n> +\n> +\tret = dma_platform_driver_register();\n> +\tif (ret)\n> +\t\tpci_unregister_driver(&ps_pcie_dma_driver);\n> +\n> +\treturn ret;\n> +}\n> +\n> +/**\n> + * ps_pcie_dma_remove - Driver remove function\n> + * @pdev: Pointer to the pci_dev structure\n> + *\n> + * Return: void\n> + */\n> +static void ps_pcie_dma_remove(struct pci_dev *pdev)\n> +{\n> +\tstruct platform_device *platform_dev;\n> +\n> +\tplatform_dev = (struct platform_device *)pci_get_drvdata(pdev);\n\nno need to cast from void\n\n> +\n> +\tif (platform_dev)\n> +\t\tplatform_device_unregister(platform_dev);\n> +}\n> +\n> +/**\n> + * ps_pcie_exit - Driver exit function\n> + *\n> + * Return: void\n> + */\n> +static void __exit ps_pcie_exit(void)\n> +{\n> +\tpr_info(\"%s exit()\\n\", DRV_MODULE_NAME);\n> +\n> +\tdma_platform_driver_unregister();\n> +\tpci_unregister_driver(&ps_pcie_dma_driver);\n> +}\n> +\n> +module_init(ps_pcie_init);\n> +module_exit(ps_pcie_exit);\n> +\n> +MODULE_AUTHOR(\"Xilinx Inc\");\n> +MODULE_DESCRIPTION(\"Xilinx PS PCIe DMA Driver\");\n> +MODULE_LICENSE(\"GPL v2\");\n> diff --git a/include/linux/dma/ps_pcie_dma.h b/include/linux/dma/ps_pcie_dma.h\n> new file mode 100644\n> index 0000000..d11323a\n> --- /dev/null\n> +++ b/include/linux/dma/ps_pcie_dma.h\n> @@ -0,0 +1,69 @@\n> +/*\n> + * Xilinx PS PCIe DMA Engine support header file\n> + *\n> + * Copyright (C) 2017 Xilinx, Inc. All rights reserved.\n> + *\n> + * This program is free software: you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation\n> + */\n> +\n> +#ifndef __DMA_XILINX_PS_PCIE_H\n> +#define __DMA_XILINX_PS_PCIE_H\n> +\n> +#include \n> +#include \n> +\n> +#define XLNX_PLATFORM_DRIVER_NAME \"xlnx-platform-dma-driver\"\n> +\n> +#define ZYNQMP_DMA_DEVID\t(0xD024)\n> +#define ZYNQMP_RC_DMA_DEVID\t(0xD021)\n> +\n> +#define MAX_ALLOWED_CHANNELS_IN_HW\t4\n> +\n> +#define MAX_NUMBER_OF_CHANNELS\tMAX_ALLOWED_CHANNELS_IN_HW\n> +\n> +#define DEFAULT_DMA_QUEUES\t4\n> +#define TWO_DMA_QUEUES\t\t2\n> +\n> +#define NUMBER_OF_BUFFER_DESCRIPTORS\t1999\n> +#define MAX_DESCRIPTORS\t\t\t65536\n> +\n> +#define CHANNEL_COAELSE_COUNT\t\t0\n> +\n> +#define CHANNEL_POLL_TIMER_FREQUENCY\t1000 /* in milli seconds */\n> +\n> +#define PCIE_AXI_DIRECTION\tDMA_TO_DEVICE\n> +#define AXI_PCIE_DIRECTION\tDMA_FROM_DEVICE\n> +\n> +/**\n> + * struct BAR_PARAMS - PCIe Bar Parameters\n> + * @BAR_PHYS_ADDR: PCIe BAR Physical address\n> + * @BAR_LENGTH: Length of PCIe BAR\n> + * @BAR_VIRT_ADDR: Virtual Address to access PCIe BAR\n> + */\n> +struct BAR_PARAMS {\n> +\tdma_addr_t BAR_PHYS_ADDR; /**< Base physical address of BAR memory */\n> +\tunsigned long BAR_LENGTH; /**< Length of BAR memory window */\n> +\tvoid *BAR_VIRT_ADDR; /**< Virtual Address of mapped BAR memory */\n\nokay you have same comment twice. What is with DAMN UPPER CASE\n\nIf you cannot do basic checks for patches, I also refuse to waste my time\nand review this any further!","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"Wo1W6N70\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y1nxZ36D4z9sP1\n\tfor ;\n\tWed, 27 Sep 2017 03:29:06 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dwtfK-0000bm-FI; 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d=\"scan'208\";a=\"316448208\"","Date":"Tue, 26 Sep 2017 23:02:07 +0530","From":"Vinod Koul ","To":"Ravi Shankar Jonnalagadda ","Subject":"Re: [PATCH v2 3/5] dmaengine: zynqmp_ps_pcie: Adding PS PCIe DMA\n\tdriver","Message-ID":"<20170926173207.GR30097@localhost>","References":"<1504873388-29195-1-git-send-email-vjonnal@xilinx.com>\n\t<1504873388-29195-4-git-send-email-vjonnal@xilinx.com>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<1504873388-29195-4-git-send-email-vjonnal@xilinx.com>","User-Agent":"Mutt/1.5.24 (2015-08-30)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170926_102836_659240_1FC8E90E ","X-CRM114-Status":"GOOD ( 29.10 )","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [134.134.136.31 listed in list.dnswl.org]\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, devicetree@vger.kernel.org,\n\tlorenzo.pieralisi@arm.com, \n\tdmaengine@vger.kernel.org, bharat.kumar.gogada@xilinx.com,\n\tlinux-pci@vger.kernel.org, michal.simek@xilinx.com,\n\tlinux-kernel@vger.kernel.org, vjonnal@xilinx.com, robh+dt@kernel.org, \n\trgummal@xilinx.com, linux-arm-kernel@lists.infradead.org,\n\tbhelgaas@google.com, \n\tdan.j.williams@intel.com, soren.brinkmann@xilinx.com","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1775736,"web_url":"http://patchwork.ozlabs.org/comment/1775736/","msgid":"<20170926173435.GS30097@localhost>","list_archive_url":null,"date":"2017-09-26T17:34:35","subject":"Re: [PATCH v2 4/5] dmaengine: zynqmp_ps_pcie: Adding PS PCIe\n\tplatform DMA driver","submitter":{"id":8232,"url":"http://patchwork.ozlabs.org/api/people/8232/","name":"Vinod Koul","email":"vinod.koul@intel.com"},"content":"On Fri, Sep 08, 2017 at 05:53:07PM +0530, Ravi Shankar Jonnalagadda wrote:\n> Platform driver handles transactions for PCIe EP DMA and Root DMA\n> \n> Signed-off-by: Ravi Shankar Jonnalagadda \n> Signed-off-by: RaviKiran Gummaluri \n> ---\n> drivers/dma/xilinx/ps_pcie_platform.c | 3055 +++++++++++++++++++++++++++++++++\n\nI dont want to loose my sanity trying to review a 3k patch. If you don't put\nan effort to make your code easier to review, I dont want to see this...\n\nNacked-by: Vinod Koul ","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"XQpN9Yj4\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y1p0Q2P1Pz9sPr\n\tfor ;\n\tWed, 27 Sep 2017 03:31:34 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dwthi-0002q2-9w; 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d=\"scan'208\";a=\"139673241\"","Date":"Tue, 26 Sep 2017 23:04:35 +0530","From":"Vinod Koul ","To":"Ravi Shankar Jonnalagadda ","Subject":"Re: [PATCH v2 4/5] dmaengine: zynqmp_ps_pcie: Adding PS PCIe\n\tplatform DMA driver","Message-ID":"<20170926173435.GS30097@localhost>","References":"<1504873388-29195-1-git-send-email-vjonnal@xilinx.com>\n\t<1504873388-29195-6-git-send-email-vjonnal@xilinx.com>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<1504873388-29195-6-git-send-email-vjonnal@xilinx.com>","User-Agent":"Mutt/1.5.24 (2015-08-30)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170926_103105_237719_2AF254B5 ","X-CRM114-Status":"UNSURE ( 8.02 )","X-CRM114-Notice":"Please train this message.","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [192.55.52.88 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3)\n\t[192.55.52.88 listed in wl.mailspike.net]\n\t-0.0 RCVD_IN_MSPIKE_WL Mailspike good senders","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, devicetree@vger.kernel.org,\n\tlorenzo.pieralisi@arm.com, \n\tdmaengine@vger.kernel.org, bharat.kumar.gogada@xilinx.com,\n\tlinux-pci@vger.kernel.org, michal.simek@xilinx.com,\n\tlinux-kernel@vger.kernel.org, vjonnal@xilinx.com, robh+dt@kernel.org, \n\trgummal@xilinx.com, linux-arm-kernel@lists.infradead.org,\n\tbhelgaas@google.com, \n\tdan.j.williams@intel.com, soren.brinkmann@xilinx.com","Content-Type":"text/plain; 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