[{"id":1766826,"web_url":"http://patchwork.ozlabs.org/comment/1766826/","msgid":"<20170912094049.GA14111@localhost.localdomain>","list_archive_url":null,"date":"2017-09-12T09:40:49","subject":"Re: [v4,0/3] Workaround for bus/slot reset on Cavium cn8xxx root\n\tports","submitter":{"id":70764,"url":"http://patchwork.ozlabs.org/api/people/70764/","name":"Vadim Lomovtsev","email":"Vadim.Lomovtsev@caviumnetworks.com"},"content":"Hi all,\n\nAre there any updates on this ?\nComments/objections/acks/nacks ?\n\nWBBR,\nVadim\n\nOn Fri, Sep 08, 2017 at 10:10:30AM +0200, Jan Glauber wrote:\n> Using vfio-pci on a combination of cn8xxx and some PCI devices results in\n> a kernel panic. This is triggered by issuing a bus or a slot reset\n> on the PCI device.\n> \n> With this series both checks indicate that the reset is not possible\n> preventing the kernel panic.\n> \n> David Daney (2):\n> PCI: Allow PCI_DEV_FLAGS_NO_BUS_RESET to be used on bus device\n> PCI: Avoid bus reset for Cavium cn8xxx root ports\n> \n> Jan Glauber (1):\n> PCI: Avoid slot reset if bus reset is not possible\n> \n> drivers/pci/pci.c | 8 ++++++++\n> drivers/pci/quirks.c | 8 ++++++++\n> 2 files changed, 16 insertions(+)","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=CAVIUMNETWORKS.onmicrosoft.com\n\theader.i=@CAVIUMNETWORKS.onmicrosoft.com header.b=\"OVyytK91\"; \n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=Vadim.Lomovtsev@cavium.com; "],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xs0D91lSnz9sRg\n\tfor ;\n\tTue, 12 Sep 2017 19:41:13 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751364AbdILJk4 (ORCPT );\n\tTue, 12 Sep 2017 05:40:56 -0400","from mail-cys01nam02on0073.outbound.protection.outlook.com\n\t([104.47.37.73]:52304\n\t\"EHLO NAM02-CY1-obe.outbound.protection.outlook.com\"\n\trhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S1751214AbdILJkz (ORCPT );\n\tTue, 12 Sep 2017 05:40:55 -0400","from localhost.localdomain (50.233.148.156) by\n\tMWHPR07MB3008.namprd07.prod.outlook.com (10.172.96.14) with Microsoft\n\tSMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.35.12; Tue, 12 Sep 2017 09:40:52 +0000"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; 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SFP:1101; SCL:1; SRVR:MWHPR07MB3008;\n\tH:localhost.localdomain; FPR:; SPF:None; PTR:InfoNoRecords;\n\tA:1; MX:1; LANG:en; ","Received-SPF":"None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"caviumnetworks.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"12 Sep 2017 09:40:52.4778\n\t(UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"711e4ccf-2e9b-4bcf-a551-4094005b6194","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"MWHPR07MB3008","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1772117,"web_url":"http://patchwork.ozlabs.org/comment/1772117/","msgid":"","list_archive_url":null,"date":"2017-09-20T17:50:41","subject":"Re: [v4,0/3] Workaround for bus/slot reset on Cavium cn8xxx root\n\tports","submitter":{"id":1882,"url":"http://patchwork.ozlabs.org/api/people/1882/","name":"Jon Masters","email":"jcm@redhat.com"},"content":"On 09/12/2017 05:40 AM, Vadim Lomovtsev wrote:\n\n> Are there any updates on this ?\n> Comments/objections/acks/nacks ?\n\nAny more comments?\n\nJon.\n\n> On Fri, Sep 08, 2017 at 10:10:30AM +0200, Jan Glauber wrote:\n>> Using vfio-pci on a combination of cn8xxx and some PCI devices results in\n>> a kernel panic. This is triggered by issuing a bus or a slot reset\n>> on the PCI device.\n>>\n>> With this series both checks indicate that the reset is not possible\n>> preventing the kernel panic.\n>>\n>> David Daney (2):\n>> PCI: Allow PCI_DEV_FLAGS_NO_BUS_RESET to be used on bus device\n>> PCI: Avoid bus reset for Cavium cn8xxx root ports\n>>\n>> Jan Glauber (1):\n>> PCI: Avoid slot reset if bus reset is not possible\n>>\n>> drivers/pci/pci.c | 8 ++++++++\n>> drivers/pci/quirks.c | 8 ++++++++\n>> 2 files changed, 16 insertions(+)","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","ext-mx07.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx07.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=jcm@redhat.com"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xy6jg69skz9rxj\n\tfor ;\n\tThu, 21 Sep 2017 03:51:03 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751378AbdITRuq (ORCPT );\n\tWed, 20 Sep 2017 13:50:46 -0400","from mx1.redhat.com ([209.132.183.28]:59808 \"EHLO mx1.redhat.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751001AbdITRuo (ORCPT );\n\tWed, 20 Sep 2017 13:50:44 -0400","from smtp.corp.redhat.com\n\t(int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 5B449C0828B6;\n\tWed, 20 Sep 2017 17:50:44 +0000 (UTC)","from washington.bos.jonmasters.org (ovpn-124-34.rdu2.redhat.com\n\t[10.10.124.34])\n\tby smtp.corp.redhat.com (Postfix) with ESMTPS id 0EE5558841;\n\tWed, 20 Sep 2017 17:50:41 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 5B449C0828B6","Subject":"Re: [v4,0/3] Workaround for bus/slot reset on Cavium cn8xxx root\n\tports","To":"Vadim Lomovtsev ,\n\tJan Glauber ,\n\tBjorn Helgaas , kvm@vger.kernel.org,\n\tlinux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tAlex Williamson ,\n\tlinux-arm-kernel@lists.infradead.org","References":"<20170908081033.3025-1-jglauber@cavium.com>\n\t<20170912094049.GA14111@localhost.localdomain>","Cc":"david.daney@cavium.com, Robert Richter ","From":"Jon Masters ","Message-ID":"","Date":"Wed, 20 Sep 2017 13:50:41 -0400","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.0","MIME-Version":"1.0","In-Reply-To":"<20170912094049.GA14111@localhost.localdomain>","Content-Type":"text/plain; charset=windows-1252","Content-Transfer-Encoding":"7bit","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.16","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.31]);\n\tWed, 20 Sep 2017 17:50:44 +0000 (UTC)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1772136,"web_url":"http://patchwork.ozlabs.org/comment/1772136/","msgid":"<20170920120912.7544420d@t450s.home>","list_archive_url":null,"date":"2017-09-20T18:09:12","subject":"Re: [v4,0/3] Workaround for bus/slot reset on Cavium cn8xxx root\n\tports","submitter":{"id":4123,"url":"http://patchwork.ozlabs.org/api/people/4123/","name":"Alex Williamson","email":"alex.williamson@redhat.com"},"content":"On Tue, 12 Sep 2017 02:40:49 -0700\nVadim Lomovtsev wrote:\n\n> Hi all,\n> \n> Are there any updates on this ?\n> Comments/objections/acks/nacks ?\n> \n> WBBR,\n> Vadim\n> \n> On Fri, Sep 08, 2017 at 10:10:30AM +0200, Jan Glauber wrote:\n> > Using vfio-pci on a combination of cn8xxx and some PCI devices results in\n> > a kernel panic. This is triggered by issuing a bus or a slot reset\n> > on the PCI device.\n> > \n> > With this series both checks indicate that the reset is not possible\n> > preventing the kernel panic.\n> > \n> > David Daney (2):\n> > PCI: Allow PCI_DEV_FLAGS_NO_BUS_RESET to be used on bus device\n> > PCI: Avoid bus reset for Cavium cn8xxx root ports\n> > \n> > Jan Glauber (1):\n> > PCI: Avoid slot reset if bus reset is not possible\n> > \n> > drivers/pci/pci.c | 8 ++++++++\n> > drivers/pci/quirks.c | 8 ++++++++\n> > 2 files changed, 16 insertions(+) \n\n\nLooks ok to me, for series:\n\nReviewed-by: Alex Williamson \n\nI am curious why we're happy targeting this quirk at a single device ID\nwhile at the same time trying to expand the ACS quirk to a notable\nfraction of the Cavium PCI device ID address space. Thanks,\n\nAlex","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","ext-mx08.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx08.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=alex.williamson@redhat.com"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xy76Y5Pm2z9s8J\n\tfor ;\n\tThu, 21 Sep 2017 04:09:09 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751367AbdITSJH (ORCPT );\n\tWed, 20 Sep 2017 14:09:07 -0400","from mx1.redhat.com ([209.132.183.28]:53560 \"EHLO mx1.redhat.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751283AbdITSJH (ORCPT );\n\tWed, 20 Sep 2017 14:09:07 -0400","from smtp.corp.redhat.com\n\t(int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 17A01C0587F1;\n\tWed, 20 Sep 2017 18:09:07 +0000 (UTC)","from t450s.home (ovpn04.gateway.prod.ext.phx2.redhat.com\n\t[10.5.9.4])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 7FC985C8B2;\n\tWed, 20 Sep 2017 18:09:06 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 17A01C0587F1","Date":"Wed, 20 Sep 2017 12:09:12 -0600","From":"Alex Williamson ","To":"Vadim Lomovtsev ","Cc":"Jan Glauber ,\n\tBjorn Helgaas , kvm@vger.kernel.org,\n\tlinux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tJon Masters ,\n\tlinux-arm-kernel@lists.infradead.org, david.daney@cavium.com,\n\tRobert Richter ","Subject":"Re: [v4,0/3] Workaround for bus/slot reset on Cavium cn8xxx root\n\tports","Message-ID":"<20170920120912.7544420d@t450s.home>","In-Reply-To":"<20170912094049.GA14111@localhost.localdomain>","References":"<20170908081033.3025-1-jglauber@cavium.com>\n\t<20170912094049.GA14111@localhost.localdomain>","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.16","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.32]);\n\tWed, 20 Sep 2017 18:09:07 +0000 (UTC)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1772523,"web_url":"http://patchwork.ozlabs.org/comment/1772523/","msgid":"<20170921080659.GA12818@hc>","list_archive_url":null,"date":"2017-09-21T08:06:59","subject":"Re: [v4,0/3] Workaround for bus/slot reset on Cavium cn8xxx root\n\tports","submitter":{"id":68474,"url":"http://patchwork.ozlabs.org/api/people/68474/","name":"Jan Glauber","email":"jan.glauber@caviumnetworks.com"},"content":"On Wed, Sep 20, 2017 at 12:09:12PM -0600, Alex Williamson wrote:\n> On Tue, 12 Sep 2017 02:40:49 -0700\n> Vadim Lomovtsev wrote:\n> \n> > Hi all,\n> > \n> > Are there any updates on this ?\n> > Comments/objections/acks/nacks ?\n> > \n> > WBBR,\n> > Vadim\n> > \n> > On Fri, Sep 08, 2017 at 10:10:30AM +0200, Jan Glauber wrote:\n> > > Using vfio-pci on a combination of cn8xxx and some PCI devices results in\n> > > a kernel panic. This is triggered by issuing a bus or a slot reset\n> > > on the PCI device.\n> > > \n> > > With this series both checks indicate that the reset is not possible\n> > > preventing the kernel panic.\n> > > \n> > > David Daney (2):\n> > > PCI: Allow PCI_DEV_FLAGS_NO_BUS_RESET to be used on bus device\n> > > PCI: Avoid bus reset for Cavium cn8xxx root ports\n> > > \n> > > Jan Glauber (1):\n> > > PCI: Avoid slot reset if bus reset is not possible\n> > > \n> > > drivers/pci/pci.c | 8 ++++++++\n> > > drivers/pci/quirks.c | 8 ++++++++\n> > > 2 files changed, 16 insertions(+) \n> \n> \n> Looks ok to me, for series:\n> \n> Reviewed-by: Alex Williamson \n\nThanks for the review. And also for being patient with my iterations.\n\n> I am curious why we're happy targeting this quirk at a single device ID\n> while at the same time trying to expand the ACS quirk to a notable\n> fraction of the Cavium PCI device ID address space. Thanks,\n\nDavid, please correct me if I'm wrong but I think this problem only\nexists on cn88xx (device id 0xa100) but not on cn81xx/cn83xx (0xa200,\n0xa300). I've seen the bridge causing the problem only on cn88xx.\n\n--Jan","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=CAVIUMNETWORKS.onmicrosoft.com\n\theader.i=@CAVIUMNETWORKS.onmicrosoft.com header.b=\"aWUIjJgY\"; \n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=Jan.Glauber@cavium.com; "],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyTjz70Swz9t3C\n\tfor ;\n\tThu, 21 Sep 2017 18:07:35 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751649AbdIUIHT (ORCPT );\n\tThu, 21 Sep 2017 04:07:19 -0400","from mail-cys01nam02on0041.outbound.protection.outlook.com\n\t([104.47.37.41]:23616\n\t\"EHLO NAM02-CY1-obe.outbound.protection.outlook.com\"\n\trhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S1751693AbdIUIHQ (ORCPT );\n\tThu, 21 Sep 2017 04:07:16 -0400","from hc (88.67.130.225) by CO2PR07MB2582.namprd07.prod.outlook.com\n\t(10.166.201.21) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.77.7;\n\tThu, 21 Sep 2017 08:07:10 +0000"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=gcX+yJ5VGPIi9j/ESAR0roRJ5H725mBbjRJObPLBf7I=;\n\tb=aWUIjJgYhclnS949fEhzGenI9jO6Nf+/Uuswcqu2PX624ot6KGwN71idVX0H14Ex/yOMO6USbH6EPBm/41zrW2y0wxeWPdykoOeCmHYN+3zQgoHTDHK+iJ7IeOwXX2y/P7fjNghV8LPRrDzm/lJkwnXyWgfilIG/6LznaxFQoKQ=","Date":"Thu, 21 Sep 2017 10:06:59 +0200","From":"Jan Glauber ","To":"Alex Williamson ","Cc":"Vadim Lomovtsev ,\n\tBjorn Helgaas , kvm@vger.kernel.org,\n\tlinux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tJon Masters ,\n\tlinux-arm-kernel@lists.infradead.org, david.daney@cavium.com,\n\tRobert Richter ","Subject":"Re: [v4,0/3] Workaround for bus/slot reset on Cavium cn8xxx root\n\tports","Message-ID":"<20170921080659.GA12818@hc>","References":"<20170908081033.3025-1-jglauber@cavium.com>\n\t<20170912094049.GA14111@localhost.localdomain>\n\t<20170920120912.7544420d@t450s.home>","MIME-Version":"1.0","Content-Type":"text/plain; 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SFP:1101; SCL:1; SRVR:CO2PR07MB2582; H:hc; FPR:;\n\tSPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; ","Received-SPF":"None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"caviumnetworks.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"21 Sep 2017 08:07:10.5592\n\t(UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"711e4ccf-2e9b-4bcf-a551-4094005b6194","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CO2PR07MB2582","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1775399,"web_url":"http://patchwork.ozlabs.org/comment/1775399/","msgid":"<20170926120032.GA29861@hc>","list_archive_url":null,"date":"2017-09-26T12:00:32","subject":"Re: [v4,0/3] Workaround for bus/slot reset on Cavium cn8xxx root\n\tports","submitter":{"id":68474,"url":"http://patchwork.ozlabs.org/api/people/68474/","name":"Jan Glauber","email":"jan.glauber@caviumnetworks.com"},"content":"On Wed, Sep 20, 2017 at 12:09:12PM -0600, Alex Williamson wrote:\n> On Tue, 12 Sep 2017 02:40:49 -0700\n> Vadim Lomovtsev wrote:\n> \n> > Hi all,\n> > \n> > Are there any updates on this ?\n> > Comments/objections/acks/nacks ?\n> > \n> > WBBR,\n> > Vadim\n> > \n> > On Fri, Sep 08, 2017 at 10:10:30AM +0200, Jan Glauber wrote:\n> > > Using vfio-pci on a combination of cn8xxx and some PCI devices results in\n> > > a kernel panic. This is triggered by issuing a bus or a slot reset\n> > > on the PCI device.\n> > > \n> > > With this series both checks indicate that the reset is not possible\n> > > preventing the kernel panic.\n> > > \n> > > David Daney (2):\n> > > PCI: Allow PCI_DEV_FLAGS_NO_BUS_RESET to be used on bus device\n> > > PCI: Avoid bus reset for Cavium cn8xxx root ports\n> > > \n> > > Jan Glauber (1):\n> > > PCI: Avoid slot reset if bus reset is not possible\n> > > \n> > > drivers/pci/pci.c | 8 ++++++++\n> > > drivers/pci/quirks.c | 8 ++++++++\n> > > 2 files changed, 16 insertions(+) \n> \n> \n> Looks ok to me, for series:\n> \n> Reviewed-by: Alex Williamson \n> \n> I am curious why we're happy targeting this quirk at a single device ID\n> while at the same time trying to expand the ACS quirk to a notable\n> fraction of the Cavium PCI device ID address space. Thanks,\n> \n> Alex\n\nBjorn, would you take these patches? \n\nWe might need to extend the quirk to cover more cn8xxx variants,\nthis is not yet entirely clear on our side.\n\nTherefore I'd like to ask if we could merge this patches now to solve the\nlong-standing issue for cn88xx.\n\nthanks,\nJan","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=CAVIUMNETWORKS.onmicrosoft.com\n\theader.i=@CAVIUMNETWORKS.onmicrosoft.com header.b=\"Y4hEwc0H\"; \n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=Jan.Glauber@cavium.com; "],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1fg72H1sz9tXf\n\tfor ;\n\tTue, 26 Sep 2017 22:01:07 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S965486AbdIZMAu (ORCPT );\n\tTue, 26 Sep 2017 08:00:50 -0400","from mail-co1nam03on0086.outbound.protection.outlook.com\n\t([104.47.40.86]:15936\n\t\"EHLO NAM03-CO1-obe.outbound.protection.outlook.com\"\n\trhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S964827AbdIZMAs (ORCPT );\n\tTue, 26 Sep 2017 08:00:48 -0400","from hc (88.67.130.225) by CO2PR07MB2582.namprd07.prod.outlook.com\n\t(10.166.201.21) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.77.7;\n\tTue, 26 Sep 2017 12:00:43 +0000"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=4hsfPhFwQ2cyFmh7FfckDG5WyNuGJWuOTmAtrduXhms=;\n\tb=Y4hEwc0HoWOwL86ag8ugBRDfh5EwX4+9LcRFsAERmXDJeiTQX0J7cIBdWMFrmeQK7Kq+sbxeHuL3oQaDVCzFO8bK+aBgvchbRFqC/sNBwaO8RAllsFjWF2DPxCJ9kijBJUeOdmpdnu+3KzeWwWc6MM302pHZ0jN+oX4lKNqLzfE=","Date":"Tue, 26 Sep 2017 14:00:32 +0200","From":"Jan Glauber ","To":"Bjorn Helgaas ","Cc":"Vadim Lomovtsev ,\n\tkvm@vger.kernel.org, linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, Jon Masters ,\n\tlinux-arm-kernel@lists.infradead.org, david.daney@cavium.com,\n\tRobert Richter ,\n\tAlex Williamson ","Subject":"Re: [v4,0/3] Workaround for bus/slot reset on Cavium cn8xxx root\n\tports","Message-ID":"<20170926120032.GA29861@hc>","References":"<20170908081033.3025-1-jglauber@cavium.com>\n\t<20170912094049.GA14111@localhost.localdomain>\n\t<20170920120912.7544420d@t450s.home>","MIME-Version":"1.0","Content-Type":"text/plain; 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SFP:1101; SCL:1; SRVR:CO2PR07MB2582; H:hc; FPR:;\n\tSPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; ","Received-SPF":"None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"caviumnetworks.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"26 Sep 2017 12:00:43.8164\n\t(UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"711e4ccf-2e9b-4bcf-a551-4094005b6194","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CO2PR07MB2582","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1784744,"web_url":"http://patchwork.ozlabs.org/comment/1784744/","msgid":"<20171011153302.GN17961@rric.localdomain>","list_archive_url":null,"date":"2017-10-11T15:33:02","subject":"Re: [PATCH v4 0/3] Workaround for bus/slot reset on Cavium cn8xxx\n\troot ports","submitter":{"id":69637,"url":"http://patchwork.ozlabs.org/api/people/69637/","name":"Richter, Robert","email":"robert.richter@cavium.com"},"content":"Bjorn,\n\nOn 08.09.17 10:10:30, Jan Glauber wrote:\n> Using vfio-pci on a combination of cn8xxx and some PCI devices results in\n> a kernel panic. This is triggered by issuing a bus or a slot reset\n> on the PCI device.\n> \n> With this series both checks indicate that the reset is not possible\n> preventing the kernel panic.\n> \n> David Daney (2):\n> PCI: Allow PCI_DEV_FLAGS_NO_BUS_RESET to be used on bus device\n> PCI: Avoid bus reset for Cavium cn8xxx root ports\n> \n> Jan Glauber (1):\n> PCI: Avoid slot reset if bus reset is not possible\n> \n> drivers/pci/pci.c | 8 ++++++++\n> drivers/pci/quirks.c | 8 ++++++++\n> 2 files changed, 16 insertions(+)\n\nif you don't have any objections, please apply this series.\n\nThanks,\n\n-Robert","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=CAVIUMNETWORKS.onmicrosoft.com\n\theader.i=@CAVIUMNETWORKS.onmicrosoft.com header.b=\"foQDMaHl\"; \n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=Robert.Richter@cavium.com; "],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yBygG5MRHz9s7F\n\tfor ;\n\tThu, 12 Oct 2017 02:33:30 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1756899AbdJKPdU (ORCPT );\n\tWed, 11 Oct 2017 11:33:20 -0400","from mail-sn1nam02on0068.outbound.protection.outlook.com\n\t([104.47.36.68]:42336\n\t\"EHLO NAM02-SN1-obe.outbound.protection.outlook.com\"\n\trhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S1751846AbdJKPdS (ORCPT );\n\tWed, 11 Oct 2017 11:33:18 -0400","from rric.localdomain (78.53.143.187) by\n\tBL2PR07MB2337.namprd07.prod.outlook.com (2a01:111:e400:c753::15) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.77.7;\n\tWed, 11 Oct 2017 15:33:13 +0000"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=xWzfE9jBQjW+Z3FU/F2mGTqq8Uu4FjpzJ3deNEC8MkE=;\n\tb=foQDMaHlXSwKeBdDG1x8blRYK3y4uMt+uGRaCut0RKcFtqlJvgm4h56/D2efhu3zvPhVTKmeqZl+Ng+OoZAFM9Yk/h0dRZugbSsHKsxhDpZtl3Cqoq3qd0ybx6dAKslMOK3acznCUMmcBtNUykcu2lkSYMqLnCQSpue1Ip1mMm4=","Date":"Wed, 11 Oct 2017 17:33:02 +0200","From":"Robert Richter ","To":"Bjorn Helgaas ","Cc":"Jan Glauber , linux-pci@vger.kernel.org,\n\tAlex Williamson ,\n\tlinux-kernel@vger.kernel.org, david.daney@cavium.com,\n\tJon Masters ,\n\tlinux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org","Subject":"Re: [PATCH v4 0/3] Workaround for bus/slot reset on Cavium cn8xxx\n\troot ports","Message-ID":"<20171011153302.GN17961@rric.localdomain>","References":"<20170908081033.3025-1-jglauber@cavium.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170908081033.3025-1-jglauber@cavium.com>","User-Agent":"Mutt/1.5.23 (2014-03-12)","X-Originating-IP":"[78.53.143.187]","X-ClientProxiedBy":"HE1PR0202CA0018.eurprd02.prod.outlook.com\n\t(2603:10a6:3:8c::28) To BL2PR07MB2337.namprd07.prod.outlook.com\n\t(2a01:111:e400:c753::15)","X-MS-PublicTrafficType":"Email","X-MS-Office365-Filtering-Correlation-Id":"7d659342-2e85-496e-3f89-08d510bd6441","X-Microsoft-Antispam":"UriScan:; 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SFP:1101; SCL:1; SRVR:BL2PR07MB2337;\n\tH:rric.localdomain; FPR:; SPF:None; PTR:InfoNoRecords; A:1;\n\tMX:1; LANG:en; ","Received-SPF":"None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"cavium.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"11 Oct 2017 15:33:13.9497\n\t(UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"711e4ccf-2e9b-4bcf-a551-4094005b6194","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"BL2PR07MB2337","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1784880,"web_url":"http://patchwork.ozlabs.org/comment/1784880/","msgid":"<20171011183201.GK25517@bhelgaas-glaptop.roam.corp.google.com>","list_archive_url":null,"date":"2017-10-11T18:32:01","subject":"Re: [PATCH v4 0/3] Workaround for bus/slot reset on Cavium cn8xxx\n\troot ports","submitter":{"id":67298,"url":"http://patchwork.ozlabs.org/api/people/67298/","name":"Bjorn Helgaas","email":"helgaas@kernel.org"},"content":"On Fri, Sep 08, 2017 at 10:10:30AM +0200, Jan Glauber wrote:\n> Using vfio-pci on a combination of cn8xxx and some PCI devices results in\n> a kernel panic. This is triggered by issuing a bus or a slot reset\n> on the PCI device.\n> \n> With this series both checks indicate that the reset is not possible\n> preventing the kernel panic.\n> \n> David Daney (2):\n> PCI: Allow PCI_DEV_FLAGS_NO_BUS_RESET to be used on bus device\n> PCI: Avoid bus reset for Cavium cn8xxx root ports\n> \n> Jan Glauber (1):\n> PCI: Avoid slot reset if bus reset is not possible\n> \n> drivers/pci/pci.c | 8 ++++++++\n> drivers/pci/quirks.c | 8 ++++++++\n> 2 files changed, 16 insertions(+)\n\nApplied to pci/host-thunder for v4.15, thanks.\n\nI reordered and renamed them like this:\n\n PCI: Mark Cavium CN8xxx to avoid bus reset\n PCI: Avoid bus reset if bridge itself is broken\n PCI: Avoid slot reset if bridge itself is broken","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=helgaas@kernel.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yC2dl1T5Nz9t2W\n\tfor ;\n\tThu, 12 Oct 2017 05:32:27 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752077AbdJKScI (ORCPT );\n\tWed, 11 Oct 2017 14:32:08 -0400","from mail.kernel.org ([198.145.29.99]:55422 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751963AbdJKScH (ORCPT );\n\tWed, 11 Oct 2017 14:32:07 -0400","from localhost (unknown [69.71.4.159])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id E575A218D7;\n\tWed, 11 Oct 2017 18:32:06 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org E575A218D7","Date":"Wed, 11 Oct 2017 13:32:01 -0500","From":"Bjorn Helgaas ","To":"Jan Glauber ","Cc":"Bjorn Helgaas , kvm@vger.kernel.org,\n\tdavid.daney@cavium.com, linux-pci@vger.kernel.org,\n\tRobert Richter , linux-kernel@vger.kernel.org,\n\tAlex Williamson ,\n\tJon Masters , linux-arm-kernel@lists.infradead.org","Subject":"Re: [PATCH v4 0/3] Workaround for bus/slot reset on Cavium cn8xxx\n\troot ports","Message-ID":"<20171011183201.GK25517@bhelgaas-glaptop.roam.corp.google.com>","References":"<20170908081033.3025-1-jglauber@cavium.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170908081033.3025-1-jglauber@cavium.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}}]