[{"id":1765120,"web_url":"http://patchwork.ozlabs.org/comment/1765120/","msgid":"<20170908071954.j2bhtw4wqa27fald@flea.lan>","list_archive_url":null,"date":"2017-09-08T07:19:54","subject":"Re: [PATCH v5 01/10] arm64: dts: allwinner: Restore EMAC changes","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Fri, Sep 08, 2017 at 09:11:47AM +0200, Corentin Labbe wrote:\n> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts\n> index 1c2387bd5df6..968908761194 100644\n> --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts\n> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts\n> @@ -50,6 +50,7 @@\n> \tcompatible = \"friendlyarm,nanopi-neo2\", \"allwinner,sun50i-h5\";\n> \n> \taliases {\n> +\t\tethernet0 = &emac;\n> \t\tserial0 = &uart0;\n> \t};\n> \n> @@ -108,6 +109,22 @@\n> \tstatus = \"okay\";\n> };\n> \n> +&emac {\n> +\tpinctrl-names = \"default\";\n> +\tpinctrl-0 = <&emac_rgmii_pins>;\n> +\tphy-supply = <®_gmac_3v3>;\n> +\tphy-handle = <&ext_rgmii_phy>;\n> +\tphy-mode = \"rgmii\";\n> +\tstatus = \"okay\";\n> +};\n> +\n> +&mdio {\n> +\text_rgmii_phy: ethernet-phy@7 {\n> +\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n> +\t\treg = <7>;\n> +\t};\n> +};\n> +\n\nThis won't compile, you don't have that node in the H5 DTSI.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpTHN57Jzz9sBd\n\tfor ;\n\tFri, 8 Sep 2017 17:20:16 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755041AbdIHHT5 (ORCPT\n\t);\n\tFri, 8 Sep 2017 03:19:57 -0400","from mail.free-electrons.com ([62.4.15.54]:36458 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1753222AbdIHHT4 (ORCPT\n\t); Fri, 8 Sep 2017 03:19:56 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid CCDB92096B; Fri, 8 Sep 2017 09:19:53 +0200 (CEST)","from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id A59F42095E;\n\tFri, 8 Sep 2017 09:19:53 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Fri, 8 Sep 2017 09:19:54 +0200","From":"Maxime Ripard ","To":"Corentin Labbe ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com,\n\tnetdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v5 01/10] arm64: dts: allwinner: Restore EMAC changes","Message-ID":"<20170908071954.j2bhtw4wqa27fald@flea.lan>","References":"<20170908071156.5115-1-clabbe.montjoie@gmail.com>\n\t<20170908071156.5115-2-clabbe.montjoie@gmail.com>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\"; boundary=\"tsk3vhysft3ppq3p\"","Content-Disposition":"inline","In-Reply-To":"<20170908071156.5115-2-clabbe.montjoie@gmail.com>","User-Agent":"NeoMutt/20170714 (1.8.3)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1765130,"web_url":"http://patchwork.ozlabs.org/comment/1765130/","msgid":"<20170908073657.GA29999@Red>","list_archive_url":null,"date":"2017-09-08T07:36:57","subject":"Re: [PATCH v5 01/10] arm64: dts: allwinner: Restore EMAC changes","submitter":{"id":64152,"url":"http://patchwork.ozlabs.org/api/people/64152/","name":"Corentin Labbe","email":"clabbe.montjoie@gmail.com"},"content":"On Fri, Sep 08, 2017 at 09:19:54AM +0200, Maxime Ripard wrote:\n> On Fri, Sep 08, 2017 at 09:11:47AM +0200, Corentin Labbe wrote:\n> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts\n> > index 1c2387bd5df6..968908761194 100644\n> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts\n> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts\n> > @@ -50,6 +50,7 @@\n> > \tcompatible = \"friendlyarm,nanopi-neo2\", \"allwinner,sun50i-h5\";\n> > \n> > \taliases {\n> > +\t\tethernet0 = &emac;\n> > \t\tserial0 = &uart0;\n> > \t};\n> > \n> > @@ -108,6 +109,22 @@\n> > \tstatus = \"okay\";\n> > };\n> > \n> > +&emac {\n> > +\tpinctrl-names = \"default\";\n> > +\tpinctrl-0 = <&emac_rgmii_pins>;\n> > +\tphy-supply = <®_gmac_3v3>;\n> > +\tphy-handle = <&ext_rgmii_phy>;\n> > +\tphy-mode = \"rgmii\";\n> > +\tstatus = \"okay\";\n> > +};\n> > +\n> > +&mdio {\n> > +\text_rgmii_phy: ethernet-phy@7 {\n> > +\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n> > +\t\treg = <7>;\n> > +\t};\n> > +};\n> > +\n> \n> This won't compile, you don't have that node in the H5 DTSI.\n> \n\nSince H5 DTSI include arm/sunxi-h3-h5.dtsi it compiles.\nFurthermore, I restested just now and confirm, it compiles fine.\n\nRegards\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170908071954.j2bhtw4wqa27fald@flea.lan>","User-Agent":"Mutt/1.7.2 (2016-11-26)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1765134,"web_url":"http://patchwork.ozlabs.org/comment/1765134/","msgid":"","list_archive_url":null,"date":"2017-09-08T07:39:04","subject":"Re: [PATCH v5 01/10] arm64: dts: allwinner: Restore EMAC changes","submitter":{"id":47154,"url":"http://patchwork.ozlabs.org/api/people/47154/","name":"Chen-Yu Tsai","email":"wens@csie.org"},"content":"On Fri, Sep 8, 2017 at 3:36 PM, Corentin Labbe\n wrote:\n> On Fri, Sep 08, 2017 at 09:19:54AM +0200, Maxime Ripard wrote:\n>> On Fri, Sep 08, 2017 at 09:11:47AM +0200, Corentin Labbe wrote:\n>> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts\n>> > index 1c2387bd5df6..968908761194 100644\n>> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts\n>> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts\n>> > @@ -50,6 +50,7 @@\n>> > compatible = \"friendlyarm,nanopi-neo2\", \"allwinner,sun50i-h5\";\n>> >\n>> > aliases {\n>> > + ethernet0 = &emac;\n>> > serial0 = &uart0;\n>> > };\n>> >\n>> > @@ -108,6 +109,22 @@\n>> > status = \"okay\";\n>> > };\n>> >\n>> > +&emac {\n>> > + pinctrl-names = \"default\";\n>> > + pinctrl-0 = <&emac_rgmii_pins>;\n>> > + phy-supply = <®_gmac_3v3>;\n>> > + phy-handle = <&ext_rgmii_phy>;\n>> > + phy-mode = \"rgmii\";\n>> > + status = \"okay\";\n>> > +};\n>> > +\n>> > +&mdio {\n>> > + ext_rgmii_phy: ethernet-phy@7 {\n>> > + compatible = \"ethernet-phy-ieee802.3-c22\";\n>> > + reg = <7>;\n>> > + };\n>> > +};\n>> > +\n>>\n>> This won't compile, you don't have that node in the H5 DTSI.\n>>\n>\n> Since H5 DTSI include arm/sunxi-h3-h5.dtsi it compiles.\n> Furthermore, I restested just now and confirm, it compiles fine.\n\nThe order of your patches are wrong. No individual patch should\nintroduce build failures, not just the whole patch series.\n\nChenYu\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpTk12q9Bz9sBd\n\tfor ;\n\tFri, 8 Sep 2017 17:39:53 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754363AbdIHHje (ORCPT\n\t);\n\tFri, 8 Sep 2017 03:39:34 -0400","from smtp.csie.ntu.edu.tw ([140.112.30.61]:57778 \"EHLO\n\tsmtp.csie.ntu.edu.tw\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1754180AbdIHHjd (ORCPT\n\t); Fri, 8 Sep 2017 03:39:33 -0400","from mail-wr0-f172.google.com (mail-wr0-f172.google.com\n\t[209.85.128.172])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits))\n\t(No client certificate requested) (Authenticated sender: b93043)\n\tby smtp.csie.ntu.edu.tw (Postfix) with ESMTPSA id 3E26820401;\n\tFri, 8 Sep 2017 15:39:28 +0800 (CST)","by mail-wr0-f172.google.com with SMTP id v109so3037790wrc.1;\n\tFri, 08 Sep 2017 00:39:28 -0700 (PDT)","by 10.223.133.253 with HTTP; Fri, 8 Sep 2017 00:39:04 -0700 (PDT)"],"X-Gm-Message-State":"AHPjjUjik8e+V/WpBF2ei9mHsrnFd5aKcGNzpoAaPoMzMixk1xU41lSe\n\t6mpcK7I3oPt6dXCDEdsrhFz/cLLDMg==","X-Google-Smtp-Source":"ADKCNb4zjrLD08tsFqh+johe+JZgliPIz2T6mGCQ2+VKOWqiFaJF0PAfzFPiXcuR1WDMtTnUOOGf/s8zJSo8a4Af/gc=","X-Received":"by 10.223.132.163 with SMTP id 32mr1180729wrg.267.1504856364815; \n\tFri, 08 Sep 2017 00:39:24 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170908073657.GA29999@Red>","References":"<20170908071156.5115-1-clabbe.montjoie@gmail.com>\n\t<20170908071156.5115-2-clabbe.montjoie@gmail.com>\n\t<20170908071954.j2bhtw4wqa27fald@flea.lan>\n\t<20170908073657.GA29999@Red>","From":"Chen-Yu Tsai ","Date":"Fri, 8 Sep 2017 15:39:04 +0800","X-Gmail-Original-Message-ID":"","Message-ID":"","Subject":"Re: [PATCH v5 01/10] arm64: dts: allwinner: Restore EMAC changes","To":"Corentin Labbe ","Cc":"Maxime Ripard ,\n\tRob Herring , Mark Rutland ,\n\tChen-Yu Tsai , Russell King ,\n\tCatalin Marinas ,\n\tWill Deacon ,\n\tGiuseppe Cavallaro ,\n\tAlexandre Torgue ,\n\tAndrew Lunn , Florian Fainelli ,\n\tnetdev , \n\tdevicetree ,\n\tlinux-arm-kernel ,\n\tlinux-kernel ","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1765327,"web_url":"http://patchwork.ozlabs.org/comment/1765327/","msgid":"<20170908130520.GA11248@lunn.ch>","list_archive_url":null,"date":"2017-09-08T13:05:20","subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","submitter":{"id":13608,"url":"http://patchwork.ozlabs.org/api/people/13608/","name":"Andrew Lunn","email":"andrew@lunn.ch"},"content":"> +#define DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID\t0\n> +#define DWMAC_sUN8I_MDIO_MUX_EXTERNAL_ID\t1\n> \n> /* H3/A64 specific bits */\n> #define SYSCON_RMII_EN\t\tBIT(13) /* 1: enable RMII (overrides EPIT) */\n> @@ -634,6 +639,76 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv)\n> \treturn 0;\n> }\n> \n> +/* MDIO multiplexing switch function\n> + * This function is called by the mdio-mux layer when it thinks the mdio bus\n> + * multiplexer needs to switch.\n> + * 'current_child' is the current value of the mux register\n> + * 'desired_child' is the value of the 'reg' property of the target child MDIO\n> + * node.\n> + * The first time this function is called, current_child == -1.\n> + * If current_child == desired_child, then the mux is already set to the\n> + * correct bus.\n> + *\n> + * Note that we do not use reg/mask like mdio-mux-mmioreg because we need to\n> + * know easily which bus is used (reset must be done only for desired bus).\n> + */\n> +static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,\n> +\t\t\t\t void *data)\n> +{\n> +\tstruct stmmac_priv *priv = data;\n> +\tstruct sunxi_priv_data *gmac = priv->plat->bsp_priv;\n> +\tu32 reg, val;\n> +\tint ret = 0;\n> +\tbool need_reset = false;\n> +\n> +\tif (current_child ^ desired_child) {\n> +\t\tregmap_read(gmac->regmap, SYSCON_EMAC_REG, ®);\n> +\t\tswitch (desired_child) {\n> +\t\tcase DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID:\n> +\t\t\tdev_info(priv->device, \"Switch mux to internal PHY\");\n> +\t\t\tval = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;\n> +\t\t\tif (gmac->use_internal_phy)\n> +\t\t\t\tneed_reset = true;\n> +\t\t\tbreak;\n\nThis i don't get. Why do you need use_internal_phy? Isn't that\nimplicit from DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID? Is it even possible to\nuse an external PHY on the internal MDIO bus?\n\n> +\t\tcase DWMAC_sUN8I_MDIO_MUX_EXTERNAL_ID:\n> +\t\t\tdev_info(priv->device, \"Switch mux to external PHY\");\n> +\t\t\tval = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN;\n> +\t\t\tif (!gmac->use_internal_phy)\n> +\t\t\t\tneed_reset = true;\n> +\t\t\tbreak;\n\nAnd is it possible to use the internal PHY on the external bus?\n\n Andrew\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpcy72rh5z9ryk\n\tfor ;\n\tFri, 8 Sep 2017 23:05:51 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755581AbdIHNFe (ORCPT\n\t);\n\tFri, 8 Sep 2017 09:05:34 -0400","from vps0.lunn.ch ([178.209.37.122]:32888 \"EHLO vps0.lunn.ch\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1755119AbdIHNFc (ORCPT );\n\tFri, 8 Sep 2017 09:05:32 -0400","from andrew by vps0.lunn.ch with local (Exim 4.84_2)\n\t(envelope-from )\n\tid 1dqIyG-0006QP-KT; Fri, 08 Sep 2017 15:05:20 +0200"],"Date":"Fri, 8 Sep 2017 15:05:20 +0200","From":"Andrew Lunn ","To":"Corentin Labbe ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tnetdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","Message-ID":"<20170908130520.GA11248@lunn.ch>","References":"<20170908071156.5115-1-clabbe.montjoie@gmail.com>\n\t<20170908071156.5115-11-clabbe.montjoie@gmail.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170908071156.5115-11-clabbe.montjoie@gmail.com>","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1765351,"web_url":"http://patchwork.ozlabs.org/comment/1765351/","msgid":"<20170908132632.GA3037@Red>","list_archive_url":null,"date":"2017-09-08T13:26:32","subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","submitter":{"id":64152,"url":"http://patchwork.ozlabs.org/api/people/64152/","name":"Corentin Labbe","email":"clabbe.montjoie@gmail.com"},"content":"On Fri, Sep 08, 2017 at 03:05:20PM +0200, Andrew Lunn wrote:\n> > +#define DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID\t0\n> > +#define DWMAC_sUN8I_MDIO_MUX_EXTERNAL_ID\t1\n> > \n> > /* H3/A64 specific bits */\n> > #define SYSCON_RMII_EN\t\tBIT(13) /* 1: enable RMII (overrides EPIT) */\n> > @@ -634,6 +639,76 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv)\n> > \treturn 0;\n> > }\n> > \n> > +/* MDIO multiplexing switch function\n> > + * This function is called by the mdio-mux layer when it thinks the mdio bus\n> > + * multiplexer needs to switch.\n> > + * 'current_child' is the current value of the mux register\n> > + * 'desired_child' is the value of the 'reg' property of the target child MDIO\n> > + * node.\n> > + * The first time this function is called, current_child == -1.\n> > + * If current_child == desired_child, then the mux is already set to the\n> > + * correct bus.\n> > + *\n> > + * Note that we do not use reg/mask like mdio-mux-mmioreg because we need to\n> > + * know easily which bus is used (reset must be done only for desired bus).\n> > + */\n> > +static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,\n> > +\t\t\t\t void *data)\n> > +{\n> > +\tstruct stmmac_priv *priv = data;\n> > +\tstruct sunxi_priv_data *gmac = priv->plat->bsp_priv;\n> > +\tu32 reg, val;\n> > +\tint ret = 0;\n> > +\tbool need_reset = false;\n> > +\n> > +\tif (current_child ^ desired_child) {\n> > +\t\tregmap_read(gmac->regmap, SYSCON_EMAC_REG, ®);\n> > +\t\tswitch (desired_child) {\n> > +\t\tcase DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID:\n> > +\t\t\tdev_info(priv->device, \"Switch mux to internal PHY\");\n> > +\t\t\tval = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;\n> > +\t\t\tif (gmac->use_internal_phy)\n> > +\t\t\t\tneed_reset = true;\n> > +\t\t\tbreak;\n> \n> This i don't get. Why do you need use_internal_phy? Isn't that\n> implicit from DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID? Is it even possible to\n> use an external PHY on the internal MDIO bus?\n> \n\nOn my H3 box with external PHY, the MDIO mux library first select (for scan ?) the internal MDIO.\nWithout use_internal_phy usage, this board will launch a reset to use the internal MDIO... and this reset timeout/fail.\nAfter the MDIO mux select the external MDIO.\n\n> > +\t\tcase DWMAC_sUN8I_MDIO_MUX_EXTERNAL_ID:\n> > +\t\t\tdev_info(priv->device, \"Switch mux to external PHY\");\n> > +\t\t\tval = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN;\n> > +\t\t\tif (!gmac->use_internal_phy)\n> > +\t\t\t\tneed_reset = true;\n> > +\t\t\tbreak;\n> \n> And is it possible to use the internal PHY on the external bus?\n> \n\nI need to check that.\n\nRegards\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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\n\tFri, 08 Sep 2017 06:26:40 -0700 (PDT)","Date":"Fri, 8 Sep 2017 15:26:32 +0200","From":"Corentin Labbe ","To":"Andrew Lunn ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tnetdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","Message-ID":"<20170908132632.GA3037@Red>","References":"<20170908071156.5115-1-clabbe.montjoie@gmail.com>\n\t<20170908071156.5115-11-clabbe.montjoie@gmail.com>\n\t<20170908130520.GA11248@lunn.ch>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170908130520.GA11248@lunn.ch>","User-Agent":"Mutt/1.7.2 (2016-11-26)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1765387,"web_url":"http://patchwork.ozlabs.org/comment/1765387/","msgid":"<20170908140020.GC25219@lunn.ch>","list_archive_url":null,"date":"2017-09-08T14:00:20","subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","submitter":{"id":13608,"url":"http://patchwork.ozlabs.org/api/people/13608/","name":"Andrew Lunn","email":"andrew@lunn.ch"},"content":"> > > +static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,\n> > > +\t\t\t\t void *data)\n> > > +{\n> > > +\tstruct stmmac_priv *priv = data;\n> > > +\tstruct sunxi_priv_data *gmac = priv->plat->bsp_priv;\n> > > +\tu32 reg, val;\n> > > +\tint ret = 0;\n> > > +\tbool need_reset = false;\n> > > +\n> > > +\tif (current_child ^ desired_child) {\n> > > +\t\tregmap_read(gmac->regmap, SYSCON_EMAC_REG, ®);\n> > > +\t\tswitch (desired_child) {\n> > > +\t\tcase DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID:\n> > > +\t\t\tdev_info(priv->device, \"Switch mux to internal PHY\");\n> > > +\t\t\tval = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;\n> > > +\t\t\tif (gmac->use_internal_phy)\n> > > +\t\t\t\tneed_reset = true;\n> > > +\t\t\tbreak;\n> > \n> > This i don't get. Why do you need use_internal_phy? Isn't that\n> > implicit from DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID? Is it even possible to\n> > use an external PHY on the internal MDIO bus?\n> > \n> \n> On my H3 box with external PHY, the MDIO mux library first select (for scan ?) the internal MDIO.\n> Without use_internal_phy usage, this board will launch a reset to use the internal MDIO... and this reset timeout/fail.\n\nDo you know why the reset times out/fails?\n\n Andrew\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpf9C3N65z9sBd\n\tfor ;\n\tSat, 9 Sep 2017 00:00:31 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751441AbdIHOA3 (ORCPT\n\t);\n\tFri, 8 Sep 2017 10:00:29 -0400","from vps0.lunn.ch ([178.209.37.122]:33011 \"EHLO vps0.lunn.ch\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1750985AbdIHOA2 (ORCPT );\n\tFri, 8 Sep 2017 10:00:28 -0400","from andrew by vps0.lunn.ch with local (Exim 4.84_2)\n\t(envelope-from )\n\tid 1dqJpU-00078J-JB; Fri, 08 Sep 2017 16:00:20 +0200"],"Date":"Fri, 8 Sep 2017 16:00:20 +0200","From":"Andrew Lunn ","To":"Corentin Labbe ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tnetdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","Message-ID":"<20170908140020.GC25219@lunn.ch>","References":"<20170908071156.5115-1-clabbe.montjoie@gmail.com>\n\t<20170908071156.5115-11-clabbe.montjoie@gmail.com>\n\t<20170908130520.GA11248@lunn.ch> <20170908132632.GA3037@Red>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170908132632.GA3037@Red>","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1765398,"web_url":"http://patchwork.ozlabs.org/comment/1765398/","msgid":"<20170908140832.GB3037@Red>","list_archive_url":null,"date":"2017-09-08T14:08:32","subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","submitter":{"id":64152,"url":"http://patchwork.ozlabs.org/api/people/64152/","name":"Corentin Labbe","email":"clabbe.montjoie@gmail.com"},"content":"On Fri, Sep 08, 2017 at 04:00:20PM +0200, Andrew Lunn wrote:\n> > > > +static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,\n> > > > +\t\t\t\t void *data)\n> > > > +{\n> > > > +\tstruct stmmac_priv *priv = data;\n> > > > +\tstruct sunxi_priv_data *gmac = priv->plat->bsp_priv;\n> > > > +\tu32 reg, val;\n> > > > +\tint ret = 0;\n> > > > +\tbool need_reset = false;\n> > > > +\n> > > > +\tif (current_child ^ desired_child) {\n> > > > +\t\tregmap_read(gmac->regmap, SYSCON_EMAC_REG, ®);\n> > > > +\t\tswitch (desired_child) {\n> > > > +\t\tcase DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID:\n> > > > +\t\t\tdev_info(priv->device, \"Switch mux to internal PHY\");\n> > > > +\t\t\tval = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;\n> > > > +\t\t\tif (gmac->use_internal_phy)\n> > > > +\t\t\t\tneed_reset = true;\n> > > > +\t\t\tbreak;\n> > > \n> > > This i don't get. Why do you need use_internal_phy? Isn't that\n> > > implicit from DWMAC_sUN8I_MDIO_MUX_INTERNAL_ID? Is it even possible to\n> > > use an external PHY on the internal MDIO bus?\n> > > \n> > \n> > On my H3 box with external PHY, the MDIO mux library first select (for scan ?) the internal MDIO.\n> > Without use_internal_phy usage, this board will launch a reset to use the internal MDIO... and this reset timeout/fail.\n> \n> Do you know why the reset times out/fails?\n> \n\nBecause there are nothing connected to it.\nI got also reset timeout on integrated MDIO when the integrated PHY is not powered.\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"nvjMQr9D\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpfLh48Vlz9sBd\n\tfor ;\n\tSat, 9 Sep 2017 00:08:44 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751166AbdIHOIm (ORCPT\n\t);\n\tFri, 8 Sep 2017 10:08:42 -0400","from mail-wm0-f66.google.com ([74.125.82.66]:36317 \"EHLO\n\tmail-wm0-f66.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751139AbdIHOIl (ORCPT\n\t); Fri, 8 Sep 2017 10:08:41 -0400","by mail-wm0-f66.google.com with SMTP id p17so1817662wmd.3;\n\tFri, 08 Sep 2017 07:08:41 -0700 (PDT)","from Red ([2a01:cb1d:16e:1300:2e56:dcff:fed2:c6d6])\n\tby smtp.googlemail.com with ESMTPSA id\n\tm19sm1477166wmd.16.2017.09.08.07.08.39\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tFri, 08 Sep 2017 07:08:39 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=date:from:to:cc:subject:message-id:references:mime-version\n\t:content-disposition:in-reply-to:user-agent;\n\tbh=p3d0mpH+Jn1o0PcmosPIASkWVhlqhXQi3UxfJu5AajI=;\n\tb=nvjMQr9DKO3FuSLs2fTQTeEgZzZxM7+oFMSfzQKzZlXjb1wgupl/OiJ1gYVJBkIPv2\n\t5YcsbHafvLc/YnrVlnyaWRL7wFGttpod33YNQJDomgGw5RAOgL2m/uwZWpDiJwE/OZbh\n\t5o1NAAnVsmoJ/5yDHd1c1QV9scUwfYdQuw0cww99zj2ea1qG8MW1j5pT7cp7SO+T7Q/L\n\tzEOtJj0l5qBhTZRBnBXzVG7bwrFr/CMLgx3QYfs1ItI9eeVNh5KQwsEm2dw1Kx6ENemn\n\tun4rN8r1CMIpH2BbevaH+4XWc7PQ0HSlXF+CQOsQGf8hR359KqXHRECRgr1u0r+7OEJW\n\t2chA==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=p3d0mpH+Jn1o0PcmosPIASkWVhlqhXQi3UxfJu5AajI=;\n\tb=g8fI/evFfIsmMIDCn42w2e0CmdQqKIJN883hHrR4TFlPDR2Jp3ATgfNj8OuJjoHBEs\n\tCWv0X2VdqeNLmm1BL2hv1HfLRaxlEmpRQrv/m/OgT08irdL+E0wE5dccL+YMNvl16CLt\n\t3QaVW3I3PkuijGAt/I4EXZDAXMFKcTFwXjdVaab+smfvhzitxt7dKjD063l3AZ+j8RaD\n\tdrGeYHABoB+KdivY19XCBYOwVwm+GILqzInYDmLp0gBFUgJWT7fZRaI04x6lLx4xm7by\n\ti1r4NZ08z4fWJxpThc9utEWnWYeJdko1Q+foEzXgXMr8NRw0J9SdqDHRAGUSfWBjHzFC\n\tttpA==","X-Gm-Message-State":"AHPjjUjVbcWZWVB4gRYjsJ8YCBniBqqPEdCdgSuDotU70hzrquZNAa6g\n\tWys/kmckUPr6XBgi+T7Sn0Y=","X-Google-Smtp-Source":"ADKCNb55ddthQdRXcOrvHLlegohEkzxYg9IdwcOuKkS16HRQDW4LzLifqrhbBWvhCknOrBvirOeg5w==","X-Received":"by 10.28.26.15 with SMTP id a15mr968911wma.16.1504879720469;\n\tFri, 08 Sep 2017 07:08:40 -0700 (PDT)","Date":"Fri, 8 Sep 2017 16:08:32 +0200","From":"Corentin Labbe ","To":"Andrew Lunn ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tnetdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","Message-ID":"<20170908140832.GB3037@Red>","References":"<20170908071156.5115-1-clabbe.montjoie@gmail.com>\n\t<20170908071156.5115-11-clabbe.montjoie@gmail.com>\n\t<20170908130520.GA11248@lunn.ch> <20170908132632.GA3037@Red>\n\t<20170908140020.GC25219@lunn.ch>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170908140020.GC25219@lunn.ch>","User-Agent":"Mutt/1.7.2 (2016-11-26)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1765407,"web_url":"http://patchwork.ozlabs.org/comment/1765407/","msgid":"<20170908141736.GF25219@lunn.ch>","list_archive_url":null,"date":"2017-09-08T14:17:36","subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","submitter":{"id":13608,"url":"http://patchwork.ozlabs.org/api/people/13608/","name":"Andrew Lunn","email":"andrew@lunn.ch"},"content":"> > Do you know why the reset times out/fails?\n> > \n> \n> Because there are nothing connected to it.\n\nThat should not be an issue. A read should just return 0xffff. And it\nshould return 0xffff fast. The timing of the MDIO protocol is fixed. A\nread or a write takes a fixed number of cycles, independent of if\nthere is a device there or not. The bus data line has a pullup, so if\nyou try to access a missing device, you automatically read 0xffff.\n\n Andrew\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpfY9198Vz9sBd\n\tfor ;\n\tSat, 9 Sep 2017 00:17:49 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754874AbdIHORr (ORCPT\n\t);\n\tFri, 8 Sep 2017 10:17:47 -0400","from vps0.lunn.ch ([178.209.37.122]:33076 \"EHLO vps0.lunn.ch\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1753243AbdIHORq (ORCPT );\n\tFri, 8 Sep 2017 10:17:46 -0400","from andrew by vps0.lunn.ch with local (Exim 4.84_2)\n\t(envelope-from )\n\tid 1dqK6C-0007Re-MN; Fri, 08 Sep 2017 16:17:36 +0200"],"Date":"Fri, 8 Sep 2017 16:17:36 +0200","From":"Andrew Lunn ","To":"Corentin Labbe ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tnetdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","Message-ID":"<20170908141736.GF25219@lunn.ch>","References":"<20170908071156.5115-1-clabbe.montjoie@gmail.com>\n\t<20170908071156.5115-11-clabbe.montjoie@gmail.com>\n\t<20170908130520.GA11248@lunn.ch> <20170908132632.GA3037@Red>\n\t<20170908140020.GC25219@lunn.ch> <20170908140832.GB3037@Red>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170908140832.GB3037@Red>","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1765415,"web_url":"http://patchwork.ozlabs.org/comment/1765415/","msgid":"<20170908142825.GC3037@Red>","list_archive_url":null,"date":"2017-09-08T14:28:25","subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","submitter":{"id":64152,"url":"http://patchwork.ozlabs.org/api/people/64152/","name":"Corentin Labbe","email":"clabbe.montjoie@gmail.com"},"content":"On Fri, Sep 08, 2017 at 04:17:36PM +0200, Andrew Lunn wrote:\n> > > Do you know why the reset times out/fails?\n> > > \n> > \n> > Because there are nothing connected to it.\n> \n> That should not be an issue. A read should just return 0xffff. And it\n> should return 0xffff fast. The timing of the MDIO protocol is fixed. A\n> read or a write takes a fixed number of cycles, independent of if\n> there is a device there or not. The bus data line has a pullup, so if\n> you try to access a missing device, you automatically read 0xffff.\n> \n\nPerhaps, but the reality is that with nothing connected to it, the reset of the MAC timeout.\nCertainly, the MAC does not support finding no PHY.\n\nSo, to prevent an error message, and a \"freeze\" of the net process, the need_reset trick is necessary.\n\nRegards\nCorentin Labbe\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"g45+HDhj\"; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170908141736.GF25219@lunn.ch>","User-Agent":"Mutt/1.7.2 (2016-11-26)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1765991,"web_url":"http://patchwork.ozlabs.org/comment/1765991/","msgid":"<20170910185640.GA17417@Red>","list_archive_url":null,"date":"2017-09-10T18:56:40","subject":"Re: [PATCH v5 01/10] arm64: dts: allwinner: Restore EMAC changes","submitter":{"id":64152,"url":"http://patchwork.ozlabs.org/api/people/64152/","name":"Corentin Labbe","email":"clabbe.montjoie@gmail.com"},"content":"On Fri, Sep 08, 2017 at 03:39:04PM +0800, Chen-Yu Tsai wrote:\n> On Fri, Sep 8, 2017 at 3:36 PM, Corentin Labbe\n> wrote:\n> > On Fri, Sep 08, 2017 at 09:19:54AM +0200, Maxime Ripard wrote:\n> >> On Fri, Sep 08, 2017 at 09:11:47AM +0200, Corentin Labbe wrote:\n> >> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts\n> >> > index 1c2387bd5df6..968908761194 100644\n> >> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts\n> >> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts\n> >> > @@ -50,6 +50,7 @@\n> >> > compatible = \"friendlyarm,nanopi-neo2\", \"allwinner,sun50i-h5\";\n> >> >\n> >> > aliases {\n> >> > + ethernet0 = &emac;\n> >> > serial0 = &uart0;\n> >> > };\n> >> >\n> >> > @@ -108,6 +109,22 @@\n> >> > status = \"okay\";\n> >> > };\n> >> >\n> >> > +&emac {\n> >> > + pinctrl-names = \"default\";\n> >> > + pinctrl-0 = <&emac_rgmii_pins>;\n> >> > + phy-supply = <®_gmac_3v3>;\n> >> > + phy-handle = <&ext_rgmii_phy>;\n> >> > + phy-mode = \"rgmii\";\n> >> > + status = \"okay\";\n> >> > +};\n> >> > +\n> >> > +&mdio {\n> >> > + ext_rgmii_phy: ethernet-phy@7 {\n> >> > + compatible = \"ethernet-phy-ieee802.3-c22\";\n> >> > + reg = <7>;\n> >> > + };\n> >> > +};\n> >> > +\n> >>\n> >> This won't compile, you don't have that node in the H5 DTSI.\n> >>\n> >\n> > Since H5 DTSI include arm/sunxi-h3-h5.dtsi it compiles.\n> > Furthermore, I restested just now and confirm, it compiles fine.\n> \n> The order of your patches are wrong. No individual patch should\n> introduce build failures, not just the whole patch series.\n> \n\nYes, I just miss-understood the reason of build failure.\nI will fix the order in the next serie.\n\nThanks\nCorentin Labbe\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"fgohQPO8\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xr0fK2Dkyz9t2l\n\tfor ;\n\tMon, 11 Sep 2017 04:56:56 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1750943AbdIJS4u (ORCPT\n\t);\n\tSun, 10 Sep 2017 14:56:50 -0400","from mail-wm0-f65.google.com ([74.125.82.65]:37722 \"EHLO\n\tmail-wm0-f65.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750890AbdIJS4t (ORCPT\n\t); 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","User-Agent":"Mutt/1.7.2 (2016-11-26)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1766377,"web_url":"http://patchwork.ozlabs.org/comment/1766377/","msgid":"<20170911161124.GD27599@lunn.ch>","list_archive_url":null,"date":"2017-09-11T16:11:24","subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","submitter":{"id":13608,"url":"http://patchwork.ozlabs.org/api/people/13608/","name":"Andrew Lunn","email":"andrew@lunn.ch"},"content":"On Fri, Sep 08, 2017 at 04:28:25PM +0200, Corentin Labbe wrote:\n> On Fri, Sep 08, 2017 at 04:17:36PM +0200, Andrew Lunn wrote:\n> > > > Do you know why the reset times out/fails?\n> > > > \n> > > \n> > > Because there are nothing connected to it.\n> > \n> > That should not be an issue. A read should just return 0xffff. And it\n> > should return 0xffff fast. The timing of the MDIO protocol is fixed. A\n> > read or a write takes a fixed number of cycles, independent of if\n> > there is a device there or not. The bus data line has a pullup, so if\n> > you try to access a missing device, you automatically read 0xffff.\n> > \n> \n> Perhaps, but the reality is that with nothing connected to it, the reset of the MAC timeout.\n> Certainly, the MAC does not support finding no PHY.\n\nAre you sure this is not because of the clock and reset?\n\n+ #address-cells = <1>;\n+ #size-cells = <0>;\n+ int_mii_phy: ethernet-phy@1 {\n+ compatible = \"ethernet-phy-ieee802.3-c22\";\n+ reg = <1>;\n+ clocks = <&ccu CLK_BUS_EPHY>;\n+ resets = <&ccu RST_BUS_EPHY>;\n\nThe way you describe it here, the clock and reset are for the PHY. But\nmaybe it is actually for the bus? I can understand a bus timing out if\nit has no clock, or it is held in reset. Try enabling the clock and\nreset when the internal bus is selected, not when the PHY on the bus\nis selected.\n\n\tAndrew\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xrXx71kRfz9s81\n\tfor ;\n\tTue, 12 Sep 2017 02:11:39 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751462AbdIKQLh (ORCPT\n\t);\n\tMon, 11 Sep 2017 12:11:37 -0400","from vps0.lunn.ch ([178.209.37.122]:37299 \"EHLO vps0.lunn.ch\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1750957AbdIKQLg (ORCPT );\n\tMon, 11 Sep 2017 12:11:36 -0400","from andrew by vps0.lunn.ch with local (Exim 4.84_2)\n\t(envelope-from )\n\tid 1drRIy-0008JZ-II; Mon, 11 Sep 2017 18:11:24 +0200"],"Date":"Mon, 11 Sep 2017 18:11:24 +0200","From":"Andrew Lunn ","To":"Corentin Labbe ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tnetdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","Message-ID":"<20170911161124.GD27599@lunn.ch>","References":"<20170908071156.5115-1-clabbe.montjoie@gmail.com>\n\t<20170908071156.5115-11-clabbe.montjoie@gmail.com>\n\t<20170908130520.GA11248@lunn.ch> <20170908132632.GA3037@Red>\n\t<20170908140020.GC25219@lunn.ch> <20170908140832.GB3037@Red>\n\t<20170908141736.GF25219@lunn.ch> <20170908142825.GC3037@Red>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170908142825.GC3037@Red>","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1766512,"web_url":"http://patchwork.ozlabs.org/comment/1766512/","msgid":"<20170911201920.GA5983@lunn.ch>","list_archive_url":null,"date":"2017-09-11T20:19:20","subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","submitter":{"id":13608,"url":"http://patchwork.ozlabs.org/api/people/13608/","name":"Andrew Lunn","email":"andrew@lunn.ch"},"content":"> Even with CLK_BUS_EPHY/RST_BUS_EPHY enabled, the MAC reset timeout.\n> So no the CLK/RST are really for the PHY.\n\nThanks for trying that.\n\nYou said it was probably during scanning of the bus it times out. What\naddress is causing the timeout? 0 or 1? If the internal bus can only\nhave one PHY on it, maybe we need to set bus->phy_mask to 0x1?\n\n Andrew\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xrfRC5yTNz9s8J\n\tfor ;\n\tTue, 12 Sep 2017 06:19:35 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1750957AbdIKUTd (ORCPT\n\t);\n\tMon, 11 Sep 2017 16:19:33 -0400","from vps0.lunn.ch ([178.209.37.122]:37507 \"EHLO vps0.lunn.ch\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1750853AbdIKUTd (ORCPT );\n\tMon, 11 Sep 2017 16:19:33 -0400","from andrew by vps0.lunn.ch with local (Exim 4.84_2)\n\t(envelope-from )\n\tid 1drVAu-0001bU-Ec; Mon, 11 Sep 2017 22:19:20 +0200"],"Date":"Mon, 11 Sep 2017 22:19:20 +0200","From":"Andrew Lunn ","To":"Corentin Labbe ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tnetdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","Message-ID":"<20170911201920.GA5983@lunn.ch>","References":"<20170908071156.5115-1-clabbe.montjoie@gmail.com>\n\t<20170908071156.5115-11-clabbe.montjoie@gmail.com>\n\t<20170908130520.GA11248@lunn.ch> <20170908132632.GA3037@Red>\n\t<20170908140020.GC25219@lunn.ch> <20170908140832.GB3037@Red>\n\t<20170908141736.GF25219@lunn.ch> <20170908142825.GC3037@Red>\n\t<20170911161124.GD27599@lunn.ch> <20170911190850.GA2291@Red>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170911190850.GA2291@Red>","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1766735,"web_url":"http://patchwork.ozlabs.org/comment/1766735/","msgid":"<20170912075415.GA1358@Red>","list_archive_url":null,"date":"2017-09-12T07:54:15","subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","submitter":{"id":64152,"url":"http://patchwork.ozlabs.org/api/people/64152/","name":"Corentin Labbe","email":"clabbe.montjoie@gmail.com"},"content":"On Mon, Sep 11, 2017 at 10:19:20PM +0200, Andrew Lunn wrote:\n> > Even with CLK_BUS_EPHY/RST_BUS_EPHY enabled, the MAC reset timeout.\n> > So no the CLK/RST are really for the PHY.\n> \n> Thanks for trying that.\n> \n> You said it was probably during scanning of the bus it times out. What\n> address is causing the timeout? 0 or 1? If the internal bus can only\n> have one PHY on it, maybe we need to set bus->phy_mask to 0x1?\n> \n\nI have added a trace in begin and end of stmmac_mdio_read()\n\n[ 18.145451] libphy: stmmac: probed\n[ 18.148398] libphy: mdio_mux: probed\n[ 18.148650] dwmac-sun8i 1c30000.ethernet: Switch mux to internal PHY\n[ 18.248751] dwmac-sun8i 1c30000.ethernet: EMAC reset timeout\n[ 18.249297] libphy: mdio_mux: probed\n[ 18.249362] dwmac-sun8i 1c30000.ethernet: Switch mux to external PHY\n[ 18.249391] stmmac_mdio_read 0 2\n[ 18.249598] stmmac_mdio_read 0 2 1c\n[ 18.249623] stmmac_mdio_read 0 3\n[ 18.249811] stmmac_mdio_read 0 3 c915\n[ 20.737271] EXT4-fs (mmcblk0p1): re-mounted. Opts: (null)\n[ 31.294868] stmmac_mdio_read 0 0\n[ 31.295311] stmmac_mdio_read 0 0 1140\n\nIt seems that the timeout is unrelated to MDIO bus.\n\nRegards\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"Dp0EP04w\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xrxrz1KKdz9s7B\n\tfor ;\n\tTue, 12 Sep 2017 17:54:27 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751238AbdILHyZ (ORCPT\n\t);\n\tTue, 12 Sep 2017 03:54:25 -0400","from mail-wr0-f176.google.com ([209.85.128.176]:33355 \"EHLO\n\tmail-wr0-f176.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751089AbdILHyY (ORCPT\n\t); Tue, 12 Sep 2017 03:54:24 -0400","by mail-wr0-f176.google.com with SMTP id a43so18847821wrc.0;\n\tTue, 12 Sep 2017 00:54:23 -0700 (PDT)","from Red ([2a01:cb1d:16e:1300:2e56:dcff:fed2:c6d6])\n\tby smtp.googlemail.com with ESMTPSA id\n\tn6sm7479539wmg.11.2017.09.12.00.54.21\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 12 Sep 2017 00:54:22 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=date:from:to:cc:subject:message-id:references:mime-version\n\t:content-disposition:in-reply-to:user-agent;\n\tbh=YIBazUM2EgCh0VN8t9kDwV+QxrDefETvCWH0it0C/NU=;\n\tb=Dp0EP04wgeZL5EtBNuIouN/sbkbAVKWPB7Z1k8vr/ddTHilsJAwzJx7Ru8jCTxtEt8\n\tExzkLVOJbgaaDkLnBFOjhsUSNHhbo94G+tlnbzsLLPLtu2CegCypNvoxVHS5t6c0PexC\n\tJE1xBiEPk3WmvhaYEyzxjpQQBEwNkVjpxHiRD4kKNtUOy7Tu4NJoGrstaRjyxzGqmgRF\n\tO45IT181kbSCKP0FUXb3JPwlqyms8m2U+MZBJeJ58jSxzNd+TMw8axHiaJNZfMvQOkPF\n\tOVOw6O4Jg+3xGal2Ong2e995gA0w1Tc0pGaVjuDn98kLbaDAUP3x85OPJZ4uSNN3ZDiP\n\tLTew==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=YIBazUM2EgCh0VN8t9kDwV+QxrDefETvCWH0it0C/NU=;\n\tb=TIZDmxsEXoJiK7Ybcuua4zTIEMxopeIxaaIU/R9QojIzUkxBPd2/Vww0BXuZsaK7TS\n\tdf0vwfRApR173X6HimwHtP4Q6jV52UJcqZChABMIETXWyLIPlPUu1RxSX/prlFjd9I/T\n\tyTE+tlK0dEP6zWX5yqWKMux2vzZQXkVQHJy3mEuoFSiteB1zgo4H0wuowYcg4KQWBsa6\n\tGdi0FdBey2F2NBdZ9zVTy0s/iqGJ9jrm//Z+S1sKALrCxBuWcpDxq4JkGQhaIP5jIIL/\n\tvg3vNZ3xcbCMP6pIsMSwaPOFtXb588ACJL8czNrFGg9djm+1kf8pbYoGEWtEbZK72qEr\n\ty8mw==","X-Gm-Message-State":"AHPjjUjtzJ1x85TLW/TsAs/xEX0PJXtuW6qFaSs5LSntX8i1cHLXDeru\n\tqqgdkhe6xtwoeQ==","X-Google-Smtp-Source":"ADKCNb6rFYmG9ggRqEQqniuu0MYwRO1263fhZcUTBm2rC8ARePwUqgplXVukpMJb3e7Zwwmppc05+Q==","X-Received":"by 10.223.177.18 with SMTP id l18mr9086184wra.167.1505202862812; \n\tTue, 12 Sep 2017 00:54:22 -0700 (PDT)","Date":"Tue, 12 Sep 2017 09:54:15 +0200","From":"Corentin Labbe ","To":"Andrew Lunn ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tmaxime.ripard@free-electrons.com, wens@csie.org,\n\tlinux@armlinux.org.uk, catalin.marinas@arm.com,\n\twill.deacon@arm.com, peppe.cavallaro@st.com,\n\talexandre.torgue@st.com, f.fainelli@gmail.com,\n\tnetdev@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle\n\tintegrated/external MDIOs","Message-ID":"<20170912075415.GA1358@Red>","References":"<20170908071156.5115-11-clabbe.montjoie@gmail.com>\n\t<20170908130520.GA11248@lunn.ch> <20170908132632.GA3037@Red>\n\t<20170908140020.GC25219@lunn.ch> <20170908140832.GB3037@Red>\n\t<20170908141736.GF25219@lunn.ch> <20170908142825.GC3037@Red>\n\t<20170911161124.GD27599@lunn.ch> <20170911190850.GA2291@Red>\n\t<20170911201920.GA5983@lunn.ch>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170911201920.GA5983@lunn.ch>","User-Agent":"Mutt/1.7.2 (2016-11-26)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]