[{"id":1765312,"web_url":"http://patchwork.ozlabs.org/comment/1765312/","msgid":"","list_archive_url":null,"date":"2017-09-08T12:50:04","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Thu, Sep 7, 2017 at 5:33 PM, Timur Tabi wrote:\n\n> First patch allows for for pinctrl-msm to understand GPIO groups with\n> no pins. Such pins are \"hidden\" and can't be exported or accessed.\n>\n> Second patch updates the QDF2xxx driver to take advantage of all that.\n>\n> v5:\n> Since gpiochip_add_data no longer requests GPIOs before scanning for\n> the direction (that patch was reverted), pinctrl-msm.c now specifically\n> checks for special case.\n\nWaiting for Bjorn's review on these.\n\nYours,\nLinus Walleij","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"BO/uR/dl\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=infradead.org header.i=@infradead.org\n\theader.b=\"MxY+TGaJ\"; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1768043,"web_url":"http://patchwork.ozlabs.org/comment/1768043/","msgid":"<0dbd161e-5437-7acb-9bc9-4a7b5869a4d7@codeaurora.org>","list_archive_url":null,"date":"2017-09-13T17:09:40","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 09/08/2017 07:50 AM, Linus Walleij wrote:\n>> Since gpiochip_add_data no longer requests GPIOs before scanning for\n>> the direction (that patch was reverted), pinctrl-msm.c now specifically\n>> checks for special case.\n> Waiting for Bjorn's review on these.\n\nBjorn,\n\nDo you think you will have a chance to review these patches in time for \n4.14?","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1505322585;\n\tbh=SkXZc+Jb4G04RMqzFpLHhJciCmJELF+CL3mrcJdnOYo=;\n\th=From:Subject:To:Cc:References:Date:In-Reply-To:From;\n\tb=JWjMJmS4E6qTUeNSplcWGqff5wqfmEZtWoQhMELgxIcUrzC+B2qyabOJnLdHp0zL5\n\tfj4O4c+5w0egJ+XulAXmk6PfkPt5LADBdhogmiAPszSoG3MzC3D5/P2chMrKwg1zWl\n\td1GzPRvQolkIP47bc9s5gmQD4tXqugpv8Y3g5nxQ=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1505322582;\n\tbh=SkXZc+Jb4G04RMqzFpLHhJciCmJELF+CL3mrcJdnOYo=;\n\th=From:Subject:To:Cc:References:Date:In-Reply-To:From;\n\tb=gNRryDk9DvdiNiPAFSaiH+pj6TXO5OkCEJwdU+ANJk+R4ha920kL50lVIWlW1Iorc\n\tKTpwBfo51q0YWbOrJN7rwiQ7WB6OGGrHmFPXr6mRywg4C/2bLeHSXg94gMcr8vNlcp\n\tJ+skx7ny6/odSIsTCutZ9ATaDu+xD1UPdBhSJD8s="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org A878860B71","From":"Timur Tabi ","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Bjorn Andersson ","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t","Message-ID":"<0dbd161e-5437-7acb-9bc9-4a7b5869a4d7@codeaurora.org>","Date":"Wed, 13 Sep 2017 12:09:40 -0500","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170913_181009_261051_F0A492F6 ","X-CRM114-Status":"GOOD ( 13.90 )","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on casper.infradead.org summary:\n\tContent analysis details: (-4.3 points, 5.0 required)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [198.145.29.96 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\tLinus Walleij ,\n\tDavid Brown , \n\tAndy Gross , anjiandi@codeaurora.org,\n\t\"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1770687,"web_url":"http://patchwork.ozlabs.org/comment/1770687/","msgid":"<20170919070422.GI3349@codeaurora.org>","list_archive_url":null,"date":"2017-09-19T07:04:22","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":6071,"url":"http://patchwork.ozlabs.org/api/people/6071/","name":"Stephen Boyd","email":"sboyd@codeaurora.org"},"content":"On 09/07, Timur Tabi wrote:\n> First patch allows for for pinctrl-msm to understand GPIO groups with\n> no pins. Such pins are \"hidden\" and can't be exported or accessed.\n> \n> Second patch updates the QDF2xxx driver to take advantage of all that.\n> \n> v5:\n> Since gpiochip_add_data no longer requests GPIOs before scanning for\n> the direction (that patch was reverted), pinctrl-msm.c now specifically\n> checks for special case.\n\nCan we add a new gpiochip op that checks for \"availability\". I\nread the other thread where the change was reverted (please add a\npointer next time), and as I understand it the gpio request\nmethod can also change the muxing to a gpio instead of something\nelse. Perhaps we can add another hook for our purposes here that\ntells gpiolib that the gpio is not usable and to skip it. The\nsemantics would be clear, it's just about probing availability of\nthis pin as a gpio and doesn't mux any pins.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"FeIsYE49\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"D452G9Z9\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"D452G9Z9\"; \n\tdkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none) header.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=sboyd@codeaurora.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxDR52l1qz9sBZ\n\tfor ;\n\tTue, 19 Sep 2017 17:05:19 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1duCap-0003Eq-DQ; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1770740,"web_url":"http://patchwork.ozlabs.org/comment/1770740/","msgid":"","list_archive_url":null,"date":"2017-09-19T08:15:50","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Tue, Sep 19, 2017 at 9:04 AM, Stephen Boyd wrote:\n\n> Perhaps we can add another hook for our purposes here that\n> tells gpiolib that the gpio is not usable and to skip it. The\n> semantics would be clear, it's just about probing availability of\n> this pin as a gpio and doesn't mux any pins.\n\nOh we already have that I think, Mika Westerberg and Andy Shevcheno\nimplemented that for anyone using CONFIG_GPIOLIB_IRQCHIP, and\nthis driver does. Timur please check: irq_need_valid_mask, irq_valid_mask\nusage.\n\nHelpful commits:\ncommit 49c03096263871a68c9dea3e86b7d1e163d2fba8\n\"pinctrl: baytrail: Do not add all GPIOs to IRQ domain\"\n\nThen you can see in commits:\ncommit 7036502783729c2aaf7a3c24c89087c58721430f\n\"pinctrl: cherryview: Add a quirk to make Acer Chromebook keyboard work again\"\ncommit 2a8209fa68236ad65363dba03db5dbced520268a\n\"pinctrl: cherryview: Extend the Chromebook DMI quirk to Intel_Strago systems\"\n\nHow this valid mask is used to work around specific ACPI\nissues on Intel chips.\n\nI bet a million to one that you have the same problems as them,\nand then we should also deal with it the same way.\n\nSorry for not seeing the obvious connection earlier.\n\nYours,\nLinus Walleij","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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Tue,\n\t19 Sep 2017 01:15:51 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170919070422.GI3349@codeaurora.org>","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<20170919070422.GI3349@codeaurora.org>","From":"Linus Walleij ","Date":"Tue, 19 Sep 2017 10:15:50 +0200","Message-ID":"","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Stephen Boyd ","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170919_011613_310728_9FE2D7BB ","X-CRM114-Status":"GOOD ( 11.70 )","X-Spam-Score":"-2.7 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.7 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow\n\ttrust [2607:f8b0:4001:c0b:0:0:0:230 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\tTimur Tabi ,\n\tBjorn Andersson ,\n\tDavid Brown ,\n\t\"thierry.reding@gmail.com\" ,\n\tAndy Gross ,\n\tAndy Shevchenko ,\n\tMika Westerberg ,\n\tanjiandi@codeaurora.org, \"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1770954,"web_url":"http://patchwork.ozlabs.org/comment/1770954/","msgid":"<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>","list_archive_url":null,"date":"2017-09-19T12:32:22","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 9/19/17 3:15 AM, Linus Walleij wrote:\n> Oh we already have that I think, Mika Westerberg and Andy Shevcheno\n> implemented that for anyone using CONFIG_GPIOLIB_IRQCHIP, and\n> this driver does. Timur please check: irq_need_valid_mask, irq_valid_mask\n> usage.\n\nThese patches already use irq_valid_mask! But that doesn't block \ncomplete access to the GPIO.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"HazWZxZk\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"TEKMcsjG\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"N+UY1gxB\"; \n\tdkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none) header.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=timur@codeaurora.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxMjF5HhPz9s7F\n\tfor ;\n\tTue, 19 Sep 2017 22:33:05 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1duHi0-00080x-1f; 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Intel Mac OS X 10.9; rv:52.0)\n\tGecko/20100101 Thunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170919_053253_100243_947137E1 ","X-CRM114-Status":"GOOD ( 11.10 )","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.3 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [198.145.29.96 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\tanjiandi@codeaurora.org, Bjorn Andersson ,\n\tDavid Brown ,\n\t\"thierry.reding@gmail.com\" ,\n\tAndy Gross ,\n\tAndy Shevchenko ,\n\tMika Westerberg ,\n\t\"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1771771,"web_url":"http://patchwork.ozlabs.org/comment/1771771/","msgid":"","list_archive_url":null,"date":"2017-09-20T11:43:38","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Tue, Sep 19, 2017 at 2:32 PM, Timur Tabi wrote:\n> On 9/19/17 3:15 AM, Linus Walleij wrote:\n>>\n>> Oh we already have that I think, Mika Westerberg and Andy Shevcheno\n>> implemented that for anyone using CONFIG_GPIOLIB_IRQCHIP, and\n>> this driver does. Timur please check: irq_need_valid_mask, irq_valid_mask\n>> usage.\n>\n> These patches already use irq_valid_mask! But that doesn't block complete\n> access to the GPIO.\n\nAha sorry for my ignorance :(\n\nDoesn't that mean we need something like irq_valid_mask but rather\ngpio_valid_mask that just block all usage of certain GPIOs?\n\nYours,\nLinus Walleij","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"oV4Issjl\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"HuewZ2RJ\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxyZJ1slLz9sRm\n\tfor ;\n\tWed, 20 Sep 2017 21:44:08 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dudQD-0000Y6-2i; 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Wed,\n\t20 Sep 2017 04:43:40 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<20170919070422.GI3349@codeaurora.org>\n\t\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>","From":"Linus Walleij ","Date":"Wed, 20 Sep 2017 13:43:38 +0200","Message-ID":"","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Timur Tabi ","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170920_044401_547313_BD3DA78B ","X-CRM114-Status":"GOOD ( 10.64 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\tanjiandi@codeaurora.org, Stephen Boyd ,\n\tBjorn Andersson ,\n\tDavid Brown ,\n\t\"thierry.reding@gmail.com\" ,\n\tAndy Gross ,\n\tAndy Shevchenko ,\n\tMika Westerberg ,\n\t\"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1771823,"web_url":"http://patchwork.ozlabs.org/comment/1771823/","msgid":"","list_archive_url":null,"date":"2017-09-20T13:04:19","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 9/20/17 6:43 AM, Linus Walleij wrote:\n> Doesn't that mean we need something like irq_valid_mask but rather\n> gpio_valid_mask that just block all usage of certain GPIOs?\n\nThat raises a lot of questions. In the meantime, my current patches for \n4.14 work fine.\n\nDo we replace irq_valid_mask with gpio_valid_mask? That would break \ndrivers where the GPIO is valid but the interrupt is not. If we keep \nboth, what happens if gpio_valid_mask is false but irq_valid_mask is \ntrue? And then we would need to audit all gpio drivers to see which \nones should be updated for the new infrastructure.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"QVEB56W7\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"pOy2TO45\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"pOy2TO45\"; \n\tdkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none) header.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=timur@codeaurora.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xy0MQ1bysz9s81\n\tfor ;\n\tWed, 20 Sep 2017 23:04:50 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1duegJ-00020j-1j; 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a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1505912662;\n\tbh=obWjEA2HUt9GYEXJizlAz6ca5MOFfpYRF+qZxPdPAEg=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=pOy2TO45VUrzDuvgiobt61o7XHmwhucbmPIijnPhfCYOulUvYUY9JUkoifjFc3pFz\n\tG6y02Mob9HiCy9+nBN28roLwdSJOLSltpikA+AnXcyNPtaqccrxObwElQQafJMxJr7\n\tB94kfA2lbGXqo8BlEv3O4/wwDw1RI65691D2auXs=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1505912662;\n\tbh=obWjEA2HUt9GYEXJizlAz6ca5MOFfpYRF+qZxPdPAEg=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=pOy2TO45VUrzDuvgiobt61o7XHmwhucbmPIijnPhfCYOulUvYUY9JUkoifjFc3pFz\n\tG6y02Mob9HiCy9+nBN28roLwdSJOLSltpikA+AnXcyNPtaqccrxObwElQQafJMxJr7\n\tB94kfA2lbGXqo8BlEv3O4/wwDw1RI65691D2auXs="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org 479E560134","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Linus Walleij ","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<20170919070422.GI3349@codeaurora.org>\n\t\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t","From":"Timur Tabi ","Message-ID":"","Date":"Wed, 20 Sep 2017 08:04:19 -0500","User-Agent":"Mozilla/5.0 (Macintosh; Intel Mac OS X 10.9; rv:52.0)\n\tGecko/20100101 Thunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170920_060442_958232_1612B917 ","X-CRM114-Status":"GOOD ( 11.90 )","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.3 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [198.145.29.96 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\tanjiandi@codeaurora.org, Stephen Boyd ,\n\tBjorn Andersson ,\n\tDavid Brown ,\n\t\"thierry.reding@gmail.com\" ,\n\tAndy Gross ,\n\tAndy Shevchenko ,\n\tMika Westerberg ,\n\t\"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1772751,"web_url":"http://patchwork.ozlabs.org/comment/1772751/","msgid":"","list_archive_url":null,"date":"2017-09-21T12:08:33","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Wed, Sep 20, 2017 at 3:04 PM, Timur Tabi wrote:\n> On 9/20/17 6:43 AM, Linus Walleij wrote:\n>>\n>> Doesn't that mean we need something like irq_valid_mask but rather\n>> gpio_valid_mask that just block all usage of certain GPIOs?\n>\n>\n> That raises a lot of questions. In the meantime, my current patches for\n> 4.14 work fine.\n>\n> Do we replace irq_valid_mask with gpio_valid_mask? That would break drivers\n> where the GPIO is valid but the interrupt is not. If we keep both, what\n> happens if gpio_valid_mask is false but irq_valid_mask is true? And then we\n> would need to audit all gpio drivers to see which ones should be updated for\n> the new infrastructure.\n\nI guess gpio_valid_mask would take precedence over irq_valid_mask.\nI.e if the GPIO is not valid then the IRQ is per definition not valid either.\n\nSince it is a new thing, we can simply define a semantic like that\nand document it.\n\nYours,\nLinus Walleij","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"Q2tSv1tp\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"T9AgnsP+\"; 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s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:To:Subject:Message-ID:Date:From:\n\tReferences:In-Reply-To:MIME-Version:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=jizFPiodk5QBIqh0wqAN0E01FidE7/FtW/9d7P82rC0=;\n\tb=Q2tSv1tpaSaGzQ\n\tLfSVANMPHG+9A1fYZx8oSiP4cTTBL52iiBr3vdboyW0WXkIkhK2azyBG8k0si5oovBHX20DyYxee+\n\tYP9Akacgg4c3qgmFR0q7sd47d1bXQXBed48rC/lXfiSaz934e5YVuKpqjt+sExsacSyylbLmM9xTT\n\tKscIIeSgmH4AJxE75zhkcANishRYkKdGYhBNynVmjlw5klGIu9YNyFRx6NZJJ9Fvq1ujNsfOOK4tq\n\t7CWgkx/ew8GNVA9IeZTrVD9sT+2GRYRWkOnQfVMOqZmTFmRFY3zs3OTy6A3iHZh2rlphCloZ33Q0O\n\tmO1e3Bw7I1wd6nLwhVoQ==;","v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=g/Hz/lkwGehmko7s2xUQIBfOtu/drzDnhWtEw/zfSqE=;\n\tb=T9AgnsP+1BiIop9PoA+x2cZ06yqfzXsxIyP+gH6voCkyKdzf9PFWt1Xc1QnWMiqReA\n\tIwcKBRXrPkOalgIDMRa9DhXqewQGVjeZno1Vu9yCeey+GObao+7TuUDgrOvjhZdO5cSe\n\t5Izrdy/0VFAp+IqamNYddAYu3a1d+6//06E38="],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=g/Hz/lkwGehmko7s2xUQIBfOtu/drzDnhWtEw/zfSqE=;\n\tb=tzBrKKbD76Szl+dFTJjd2N6n5lefu4PsQfyWEWMp8TyyDNKU8WDBE9IUAqQZoCbY2C\n\t2h3sBRxh5Ltjb6pXmlT7PCvbc3mqpkurzKM8y2voEZSTtURsk4AYXYU2dFyp6zpZsG5M\n\tObpxujySsC4gD1e7W7w/eGuw9s6Trv6smCHzrnC0nuqg6zvxTW/A+b3FJDV1kEgqo3e4\n\t6oDfM2xd5mB2mMSn+3XFT5WCVK5FKpKuP0yXulRjUybweZGdHA+39mP2bD2ds2eZCvwY\n\tALFOQ4C+8Bqw515u03iiZtDLoWv1lYHYukidPmLoAmdEuWtfpNIlpmZE2ouR3UxRefd8\n\tLj6g==","X-Gm-Message-State":"AHPjjUihmZfoVH3rOBMScu7LngG5+Lg5jq2jxK04IspjIaaW9qbApMMT\n\tFjp4AveIuTemxL1ZUycl4xN6su6UmWwCMRzX0FGBPg==","X-Google-Smtp-Source":"AOwi7QCkMDqaWStv1mbTWii4dFHaBZSvJP2/qvZ7vUKHKP0vs3TFG8uagEYfppoiTyagsZ0VsKoCY/mZkzyFM+vna0w=","X-Received":"by 10.107.22.65 with SMTP id 62mr2704027iow.269.1505995714398;\n\tThu, 21 Sep 2017 05:08:34 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<20170919070422.GI3349@codeaurora.org>\n\t\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t","From":"Linus Walleij ","Date":"Thu, 21 Sep 2017 14:08:33 +0200","Message-ID":"","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Timur Tabi ","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170921_050856_243346_328EFC42 ","X-CRM114-Status":"GOOD ( 13.41 )","X-Spam-Score":"-2.7 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.7 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow\n\ttrust [2607:f8b0:4001:c06:0:0:0:22a listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\tanjiandi@codeaurora.org, Stephen Boyd ,\n\tBjorn Andersson ,\n\tDavid Brown ,\n\t\"thierry.reding@gmail.com\" ,\n\tAndy Gross ,\n\tAndy Shevchenko ,\n\tMika Westerberg ,\n\t\"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1772756,"web_url":"http://patchwork.ozlabs.org/comment/1772756/","msgid":"<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>","list_archive_url":null,"date":"2017-09-21T12:12:29","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 9/21/17 7:08 AM, Linus Walleij wrote:\n> I guess gpio_valid_mask would take precedence over irq_valid_mask.\n> I.e if the GPIO is not valid then the IRQ is per definition not valid either.\n> \n> Since it is a new thing, we can simply define a semantic like that\n> and document it.\n\nSo what about my current patches? I hope you're not asking me to \nrewrite them again.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"IHJ144HS\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"HBSoBVsW\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"AkGJBJwK\"; \n\tdkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none) header.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=timur@codeaurora.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xyb9D2X87z9t4P\n\tfor ;\n\tThu, 21 Sep 2017 22:13:04 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dv0Lk-0005z3-TD; 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a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1505995955;\n\tbh=8eoNJ34toxNpBJ6Wd9BB9AagNoirVWjPe09JKoHRtIk=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=HBSoBVsWQS6dm6Dep0tYcopB2LA6kUaq9Lta3OSYmdw/nl3mmuVaPdn8/foNA62mh\n\tRtPyEnWtVBTxFRQ9j8NTzZ+xDvrEXVxpkkd/FfEt+TNfdWEiPU5n2JwE0fqBgdmzBa\n\tkvOrnIqb0hqc9saG53Y8DvIxOZrsDPXR31TLIUGc=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1505995954;\n\tbh=8eoNJ34toxNpBJ6Wd9BB9AagNoirVWjPe09JKoHRtIk=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=AkGJBJwKqT/nzTY4AhPAW7SF9hf+00xSVeiCi7bVD0XPCG1Sa2VUySCh5LMCqyo6b\n\t5vWuBuJ4jNImUBDOx/NKXuCFrdFiDfevRU5QFC6R1wgijI+YcDryFrX2RexPoy0HnO\n\tJI3Rc1DQYlRe5JY92FPMLbddD+v1+s1EK501Ze8Y="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org B88C96087F","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Linus Walleij ","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<20170919070422.GI3349@codeaurora.org>\n\t\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t\n\t","From":"Timur Tabi ","Message-ID":"<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>","Date":"Thu, 21 Sep 2017 07:12:29 -0500","User-Agent":"Mozilla/5.0 (Macintosh; Intel Mac OS X 10.9; rv:52.0)\n\tGecko/20100101 Thunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170921_051256_665499_0F17CB2A ","X-CRM114-Status":"GOOD ( 11.11 )","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.3 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [198.145.29.96 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\tanjiandi@codeaurora.org, Stephen Boyd ,\n\tBjorn Andersson ,\n\tDavid Brown ,\n\t\"thierry.reding@gmail.com\" ,\n\tAndy Gross ,\n\tAndy Shevchenko ,\n\tMika Westerberg ,\n\t\"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1773593,"web_url":"http://patchwork.ozlabs.org/comment/1773593/","msgid":"","list_archive_url":null,"date":"2017-09-22T13:29:53","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Thu, Sep 21, 2017 at 2:12 PM, Timur Tabi wrote:\n> On 9/21/17 7:08 AM, Linus Walleij wrote:\n>>\n>> I guess gpio_valid_mask would take precedence over irq_valid_mask.\n>> I.e if the GPIO is not valid then the IRQ is per definition not valid\n>> either.\n>>\n>> Since it is a new thing, we can simply define a semantic like that\n>> and document it.\n>\n> So what about my current patches?\n\nI am waiting for the maintainer, Bjorn Andersson, to provide review.\n\n> I hope you're not asking me to rewrite\n> them again.\n\nI don't understand your remark. If you are impatient, such is life.\n\nWhat is your response to Stephen's comment:\n\n> [Stephen Boyd]\n> Perhaps we can add another hook for our purposes here that\n> tells gpiolib that the gpio is not usable and to skip it. The\n> semantics would be clear, it's just about probing availability of\n> this pin as a gpio and doesn't mux any pins.\n\nI think this kind of related to my response (after I realized it\nwas not just about IRQs):\n\n> Doesn't that mean we need something like irq_valid_mask but rather\n> gpio_valid_mask that just block all usage of certain GPIOs?\n\nYours,\nLinus Walleij","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"g3lBRO/m\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"EbZrXYqF\"; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1773599,"web_url":"http://patchwork.ozlabs.org/comment/1773599/","msgid":"<255ad0dc-2d16-ae7f-0b45-500e23cff1a4@codeaurora.org>","list_archive_url":null,"date":"2017-09-22T13:37:07","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 09/22/2017 08:29 AM, Linus Walleij wrote:\n> \n> What is your response to Stephen's comment:\n> \n>> [Stephen Boyd]\n>> Perhaps we can add another hook for our purposes here that\n>> tells gpiolib that the gpio is not usable and to skip it. The\n>> semantics would be clear, it's just about probing availability of\n>> this pin as a gpio and doesn't mux any pins.\n\n> I think this kind of related to my response (after I realized it\n> was not just about IRQs):\n\nWe already have 95% of this. We can already specify individual pin \nranges, and the vast majority of the code recognizes the ranges. There \nis only one small loophole, and that's in gpiochip_add_data(). The \nfor-loop iterates over all GPIOs:\n\n\tfor (i = 0; i < chip->ngpio; i++) {\n\t\tstruct gpio_desc *desc = &gdev->descs[i];\n\n\t\tdesc->gdev = gdev;\n\t\t/*\n\t\t * REVISIT: most hardware initializes GPIOs as inputs\n\t\t * (often with pullups enabled) so power usage is\n\t\t * minimized. Linux code should set the gpio direction\n\t\t * first thing; but until it does, and in case\n\t\t * chip->get_direction is not set, we may expose the\n\t\t * wrong direction in sysfs.\n\t\t */\n\nI believe the real problem is that this for-loop should be moved from \ngpiochip_add_data() into some other function that is called *after* the \npin ranges are defined. We can put it in gpiochip_add_pin_range(), maybe.\n\nMy patch covers the loophole by adding a check inside get_direction(). \nIf we fix gpiochip_add_data(), I can remove that patch.\n\nHowever, I think that change is risky and will require a lot of testing \nand review.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"T0WFEaQ1\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"XVTa51tx\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"mloW0/6r\"; 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a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1506087429;\n\tbh=lTFTBYjiGseIbtZpBN18EQMYHNIKeOhe7J4kOCPkL3w=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=mloW0/6ryHspPstvye3PZCC47fND73GvVHLC56GDITNebiLbfq1HUEQTcz53c4haA\n\tPMhb6Bq0wdwFX0sKIzjStQy+3oCAYV8/g3nQr88OXfl4NaU41jD5Zyb+Mw7VTvIZRb\n\tWN3tuCoRXtWzLp5oHHGoheW+g6HY4F0K3BbYB2Fw="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org BA9D160117","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Linus Walleij ","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<20170919070422.GI3349@codeaurora.org>\n\t\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t\n\t\n\t<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>\n\t","From":"Timur Tabi ","Message-ID":"<255ad0dc-2d16-ae7f-0b45-500e23cff1a4@codeaurora.org>","Date":"Fri, 22 Sep 2017 08:37:07 -0500","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170922_063731_233268_F362E637 ","X-CRM114-Status":"GOOD ( 16.07 )","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.3 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [198.145.29.96 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\tanjiandi@codeaurora.org, Stephen Boyd ,\n\tBjorn Andersson ,\n\tDavid Brown ,\n\t\"thierry.reding@gmail.com\" ,\n\tAndy Gross ,\n\tAndy Shevchenko ,\n\tMika Westerberg ,\n\t\"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1778429,"web_url":"http://patchwork.ozlabs.org/comment/1778429/","msgid":"<0ede14eb-a9fc-ab90-4e18-c6c955da2601@codeaurora.org>","list_archive_url":null,"date":"2017-10-02T16:02:50","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 09/22/2017 08:29 AM, Linus Walleij wrote:\n> I am waiting for the maintainer, Bjorn Andersson, to provide review.\n\nBjorn,\n\nWould you please take a moment to review these patches? I'm guessing \nit's too late for 4.14, so I would like these merged into 4.15. But \nwithout your review, very little progress is being made.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"Xc6rDpz8\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"pBeSI2EM\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"EGlepD7i\"; \n\tdkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none) header.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=timur@codeaurora.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y5Rlv5ZsFz9t5s\n\tfor ;\n\tTue, 3 Oct 2017 03:03:23 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dz3Be-0006cv-TA; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171002_090316_215824_4E157064 ","X-CRM114-Status":"UNSURE ( 9.12 )","X-CRM114-Notice":"Please train this message.","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.3 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [198.145.29.96 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\tLinus Walleij ,\n\tStephen Boyd , \n\tDavid Brown ,\n\t\"thierry.reding@gmail.com\" ,\n\tAndy Gross ,\n\tAndy Shevchenko ,\n\tMika Westerberg ,\n\tanjiandi@codeaurora.org, \"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1778488,"web_url":"http://patchwork.ozlabs.org/comment/1778488/","msgid":"<20171002174414.GL1165@minitux>","list_archive_url":null,"date":"2017-10-02T17:44:14","subject":"Re: [PATCH 1/2] [v5] pinctrl: qcom: disable GPIO groups with no pins","submitter":{"id":68398,"url":"http://patchwork.ozlabs.org/api/people/68398/","name":"Bjorn Andersson","email":"bjorn.andersson@linaro.org"},"content":"On Thu 07 Sep 08:33 PDT 2017, Timur Tabi wrote:\n\nSorry for the slow response, I finally met with Linus last week to\ndiscuss this.\n\n> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c\n[..]\n> @@ -825,13 +897,39 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)\n> \tchip->owner = THIS_MODULE;\n> \tchip->of_node = pctrl->dev->of_node;\n> \n> +\t/* If the GPIO map is sparse, then we need to disable specific IRQs */\n> +\tchip->irq_need_valid_mask = pctrl->soc->sparse;\n> +\n> \tret = gpiochip_add_data(&pctrl->chip, pctrl);\n> \tif (ret) {\n> \t\tdev_err(pctrl->dev, \"Failed register gpiochip\\n\");\n> \t\treturn ret;\n> \t}\n> \n> -\tret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);\n> +\t/*\n> +\t * If irq_need_valid_mask is true, then gpiochip_add_data() will\n> +\t * initialize irq_valid_mask to all 1s. We need to clear all the\n> +\t * GPIOs that are unavailable, and we need to find each block\n> +\t * of consecutive available GPIOs are add them as pin ranges.\n> +\t */\n> +\tif (chip->irq_need_valid_mask) {\n> +\t\tfor (i = 0; i < ngpio; i++)\n> +\t\t\tif (!groups[i].npins)\n> +\t\t\t\tclear_bit(i, pctrl->chip.irq_valid_mask);\n> +\n> +\t\twhile ((count = msm_gpio_get_next_range(pctrl, &start))) {\n> +\t\t\tret = gpiochip_add_pin_range(&pctrl->chip,\n> +\t\t\t\t\t\t dev_name(pctrl->dev),\n> +\t\t\t\t\t\t start, start, count);\n> +\t\t\tif (ret)\n> +\t\t\t\tbreak;\n> +\t\t\tstart += count;\n\nI do not fancy the idea of specifying a bitmap of valid irq pins and\nthen having the driver register the pin-ranges in-between. If we provide\na bitmap of validity to the core it should support using this for the\npins as well. (Which I believe is what Linus answered in the discussion\nfollowing patch 0/2)\n\n> +\t\t}\n> +\t} else {\n> +\t\tret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),\n> +\t\t\t\t\t 0, 0, ngpio);\n> +\t}\n> +\n\nRegards,\nBjorn","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"DOQ1lA2H\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"ge5VSg6P\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y5V0v1cjtz9rxm\n\tfor ;\n\tTue, 3 Oct 2017 04:44:47 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dz4ln-0005pe-It; Mon, 02 Oct 2017 17:44:43 +0000","from mail-pg0-x235.google.com ([2607:f8b0:400e:c05::235])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dz4lj-0005oN-2M for linux-arm-kernel@lists.infradead.org;\n\tMon, 02 Oct 2017 17:44:41 +0000","by mail-pg0-x235.google.com with SMTP id v3so3341855pgv.3\n\tfor ;\n\tMon, 02 Oct 2017 10:44:18 -0700 (PDT)","from minitux (ip68-111-217-79.sd.sd.cox.net. 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\n\tMon, 02 Oct 2017 10:44:17 -0700 (PDT)","Date":"Mon, 2 Oct 2017 10:44:14 -0700","From":"Bjorn Andersson ","To":"Timur Tabi ","Subject":"Re: [PATCH 1/2] [v5] pinctrl: qcom: disable GPIO groups with no pins","Message-ID":"<20171002174414.GL1165@minitux>","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<1504798409-32041-2-git-send-email-timur@codeaurora.org>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<1504798409-32041-2-git-send-email-timur@codeaurora.org>","User-Agent":"Mutt/1.8.3 (2017-05-23)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171002_104439_364413_FB0A4B6C ","X-CRM114-Status":"GOOD ( 17.18 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2607:f8b0:400e:c05:0:0:0:235 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n\tLinus Walleij , david.brown@linaro.org,\n\tandy.gross@linaro.org, anjiandi@codeaurora.org,\n\tlinux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1778613,"web_url":"http://patchwork.ozlabs.org/comment/1778613/","msgid":"<9f28c9dd-6277-6c75-1186-a834e15c5346@codeaurora.org>","list_archive_url":null,"date":"2017-10-02T20:47:51","subject":"Re: [PATCH 1/2] [v5] pinctrl: qcom: disable GPIO groups with no pins","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 10/02/2017 12:44 PM, Bjorn Andersson wrote:\n>> +\t/*\n>> +\t * If irq_need_valid_mask is true, then gpiochip_add_data() will\n>> +\t * initialize irq_valid_mask to all 1s. We need to clear all the\n>> +\t * GPIOs that are unavailable, and we need to find each block\n>> +\t * of consecutive available GPIOs are add them as pin ranges.\n>> +\t */\n>> +\tif (chip->irq_need_valid_mask) {\n>> +\t\tfor (i = 0; i < ngpio; i++)\n>> +\t\t\tif (!groups[i].npins)\n>> +\t\t\t\tclear_bit(i, pctrl->chip.irq_valid_mask);\n>> +\n>> +\t\twhile ((count = msm_gpio_get_next_range(pctrl, &start))) {\n>> +\t\t\tret = gpiochip_add_pin_range(&pctrl->chip,\n>> +\t\t\t\t\t\t dev_name(pctrl->dev),\n>> +\t\t\t\t\t\t start, start, count);\n>> +\t\t\tif (ret)\n>> +\t\t\t\tbreak;\n>> +\t\t\tstart += count;\n> I do not fancy the idea of specifying a bitmap of valid irq pins and\n> then having the driver register the pin-ranges in-between. \n\nBut that's exactly what abx500_gpio_probe() in pinctrl-abx500.c does. \nHere's even a reference to holes in the GPIO space:\n\n/*\n * Compute number of GPIOs from the last SoC gpio range descriptors\n * These ranges may include \"holes\" but the GPIO number space shall\n * still be homogeneous, so we need to detect and account for any\n * such holes so that these are included in the number of GPIO pins.\n */\n\n > If we provide\n> a bitmap of validity to the core it should support using this for the\n> pins as well. (Which I believe is what Linus answered in the discussion\n> following patch 0/2)\n\nSo you want to change \"gpio_chip\" to add an \"available\" callback? And \nevery time gpiolib wants to call a gpio_chip callback, it should call \n->available first? Like this:\n\nif (chip->available && chip->available())\n\tstatus = chip->direction_input(chip, gpio_chip_hwgpio(desc));\n\nI can do that, but it just seems very redundant. The core already knows \nnot to touch GPIOs that are not in a pin range. The only exception is \ngpiochip_add_data(), as I've stated before.\n\nIt just seems wrong to call an API every time to ask permission before \nwe can call any other API. But since the API may not be defined, we \nhave to first check if the API exists before we can ask permission.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"lH0ORwxU\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"do5DxFyg\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"S2mEHhyT\"; \n\tdkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none) header.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=timur@codeaurora.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y5Z4k6H59z9t5R\n\tfor ;\n\tTue, 3 Oct 2017 07:48:22 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dz7dR-0002Bh-Kw; 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a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1506977273;\n\tbh=iMtQ/VsLvWmenX+CJydSwWjWTECDEwSE1A1yB7612/4=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=do5DxFygdervj44DSkMowCEdpV8+ayfRcFRzelxvPEuS0JuKeE87PXOZrDevVzjU4\n\teE4mK93sKWqANQLRbm6ieWfBHjy6ni/XcJNHD4OYBm3xrrWtJdSsMrmW2YNYQRlv4A\n\tnGfljHz7/vlk22QIvs1FDMm+EANEgzaxbM+OjMmE=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1506977272;\n\tbh=iMtQ/VsLvWmenX+CJydSwWjWTECDEwSE1A1yB7612/4=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=S2mEHhyT3kOLIJ1BlhEGihNqDyL4/ipumaSDctinlzm4HfgABaEPIFjuJS2nHG2Tr\n\tLM1KpmrvIuDC5CNyBwGIH6AkFjw3S023bBYhUQ9ao1kq6Ie3Vh4HZx1LSEotriZdJw\n\tjOQXVh4R9oN7i6z/cG7CWI2+1B4k3sKhcOIgvc2Q="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org 22840600D0","Subject":"Re: [PATCH 1/2] [v5] pinctrl: qcom: disable GPIO groups with no pins","To":"Bjorn Andersson ","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<1504798409-32041-2-git-send-email-timur@codeaurora.org>\n\t<20171002174414.GL1165@minitux>","From":"Timur Tabi ","Message-ID":"<9f28c9dd-6277-6c75-1186-a834e15c5346@codeaurora.org>","Date":"Mon, 2 Oct 2017 15:47:51 -0500","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20171002174414.GL1165@minitux>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171002_134814_241566_F08368DE ","X-CRM114-Status":"GOOD ( 19.09 )","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.3 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [198.145.29.96 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n\tLinus Walleij , david.brown@linaro.org,\n\tandy.gross@linaro.org, anjiandi@codeaurora.org,\n\tlinux-arm-kernel@lists.infradead.org","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1779297,"web_url":"http://patchwork.ozlabs.org/comment/1779297/","msgid":"<40a0ab68-dc3a-10e2-f78e-9a386b4a72bd@codeaurora.org>","list_archive_url":null,"date":"2017-10-03T22:12:08","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 10/03/2017 05:03 PM, Stephen Boyd wrote:\n> I've run into this now on our mobile SoCs after I pull in commit\n> 8e51533780ba (\"pinctrl: qcom: add get_direction function\").\n> Before that commit we never read each pin of the device. On our\n> mobile SoCs we have devicetree and it feels like having that\n> describe which pins are available and not available is\n> half-duplicating information we would already have via consumers\n> indicating which pins they care about. I don't see any value\n> beyond system wide debug in figuring out the default pin\n> configuration of a pin that doesn't have a consumer in Linux.\n\nAt the time I wrote that patch, the ACPI tables exposed all of the \nGPIOs, even the ones it didn't care about. The new ACPI tables list \nonly specific GPIOs, and so we no longer need to blindly read the \ndirection of all GPIOs.\n\n> Could we remove the pin direction finding part here in\n> gpiochip_add_pin_range() and lazily resolve the pin direction\n> when a pin is requested?\n\nThat makes a lot more sense.\n\n> We would need a similar check in the msm\n> specific debugfs code where we skip pins that aren't requested.\n\nI have that in patch #1.\n\n> This is basically a revert of commit 72d320006177 (\"gpio: set up\n> initial state from .get_direction()\").\n\nI would be in favor of either reverting that patch, or moving the code \ninto gpiochip_add_pin_range().\n\n> ACPI can still describe only the pin ranges that they care about\n> exposing, but from the devicetree side it's been working well\n> enough to not touch pins that aren't used by anything in Linux.\n\nI do hate having to hack up the driver to support crappy ACPI \ndefinitions, but I'm stuck between a rock and a hard place.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507068731;\n\tbh=JknIM+3foHJ3/YqOE9WLexyCC9zgU+JO26zswTdbQiE=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=lNX5T+sgCRJLqwS+k+1db/Jgmg+V3uzWFEaAUh1RoXYHVAV/RwFQ2MUXpL+COU/L2\n\tq3tL9z/Ml+pXGRDo5RhBr3xWEXB+7eWENCJLbIrevY7ZkJG7p9B72IJ9SZbZdV9DlP\n\tVN/eErL11VGk4XcmAyae/9BKLS6N0+Xg8OqT2pYU=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507068730;\n\tbh=JknIM+3foHJ3/YqOE9WLexyCC9zgU+JO26zswTdbQiE=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=Y8ggvrNu6EMGoIa5q4ncHsLEKGyJszBLfbDhLun79A2QzHgzs+VXplrtEucUVmE/+\n\tw7tDcFJdQEUjwfTD/gFp9tJvlxncABwoq2Eo/z35mDVOduBBPTjY5Ts6bxTKkjebcv\n\t+jVMVMgPzyPwMRHazYeXgEdujR/VjpxMGID52weg="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org DD52E60723","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Stephen Boyd ","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<20170919070422.GI3349@codeaurora.org>\n\t\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t\n\t\n\t<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>\n\t\n\t<255ad0dc-2d16-ae7f-0b45-500e23cff1a4@codeaurora.org>\n\t<20171003220311.GU457@codeaurora.org>","From":"Timur Tabi ","Message-ID":"<40a0ab68-dc3a-10e2-f78e-9a386b4a72bd@codeaurora.org>","Date":"Tue, 3 Oct 2017 17:12:08 -0500","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20171003220311.GU457@codeaurora.org>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171003_151231_895417_CFC8BB56 ","X-CRM114-Status":"GOOD ( 17.67 )","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.3 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [198.145.29.96 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\tLinus Walleij ,\n\tBjorn Andersson ,\n\tDavid Brown ,\n\t\"thierry.reding@gmail.com\" ,\n\tAndy Gross ,\n\tAndy Shevchenko ,\n\tMika Westerberg ,\n\tanjiandi@codeaurora.org, \"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1780139,"web_url":"http://patchwork.ozlabs.org/comment/1780139/","msgid":"<20171004215023.GA457@codeaurora.org>","list_archive_url":null,"date":"2017-10-04T21:50:23","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":6071,"url":"http://patchwork.ozlabs.org/api/people/6071/","name":"Stephen Boyd","email":"sboyd@codeaurora.org"},"content":"On 10/03, Timur Tabi wrote:\n> On 10/03/2017 05:03 PM, Stephen Boyd wrote:\n> >I've run into this now on our mobile SoCs after I pull in commit\n> >8e51533780ba (\"pinctrl: qcom: add get_direction function\").\n> >Before that commit we never read each pin of the device. On our\n> >mobile SoCs we have devicetree and it feels like having that\n> >describe which pins are available and not available is\n> >half-duplicating information we would already have via consumers\n> >indicating which pins they care about. I don't see any value\n> >beyond system wide debug in figuring out the default pin\n> >configuration of a pin that doesn't have a consumer in Linux.\n> \n> At the time I wrote that patch, the ACPI tables exposed all of the\n> GPIOs, even the ones it didn't care about. The new ACPI tables list\n> only specific GPIOs, and so we no longer need to blindly read the\n> direction of all GPIOs.\n> \n\nDo you avoid this problem on new ACPI tables because only pins\nthat are able to be read are exposed?\n\n> \n> >This is basically a revert of commit 72d320006177 (\"gpio: set up\n> >initial state from .get_direction()\").\n> \n> I would be in favor of either reverting that patch, or moving the\n> code into gpiochip_add_pin_range().\n\nIf it's in gpiochip_add_pin_range() would we still read the\nhardware when creating the pin ranges? I don't want to have to\ndescribe pin ranges of \"valid\" pins that won't cause the system\nto blow up if we touch them, because those pins are never used by\nLinux so reading them is not useful.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"eZLU7rqy\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"HJFIcyHm\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"kKp1ruNE\"; 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a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507153824;\n\tbh=MnQB+DrXaZifypzRvP/m30zSLMFKhfakis1rM6rf5pE=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=kKp1ruNEmWF6cGsRHUbVeExrVcwXSY92Kf7DBC35iQ6ROg1wTQGJlyZgxo+XHkBCm\n\tVyxBtPeFs1MR250GtZ9gfPppQmEj2mHgPUZhS20s01PTTLSrnVrU30g3GtEUGIvV+W\n\tm0FEfIFRRce6MIchmP0FQS7fiKRp066mLF2TvC38="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4F29F6071B","Date":"Wed, 4 Oct 2017 14:50:23 -0700","From":"Stephen Boyd ","To":"Timur Tabi ","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","Message-ID":"<20171004215023.GA457@codeaurora.org>","References":"\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t\n\t\n\t<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>\n\t\n\t<255ad0dc-2d16-ae7f-0b45-500e23cff1a4@codeaurora.org>\n\t<20171003220311.GU457@codeaurora.org>\n\t<40a0ab68-dc3a-10e2-f78e-9a386b4a72bd@codeaurora.org>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<40a0ab68-dc3a-10e2-f78e-9a386b4a72bd@codeaurora.org>","User-Agent":"Mutt/1.5.21 (2010-09-15)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171004_145045_759075_4B9E6B5E ","X-CRM114-Status":"GOOD ( 16.93 )","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.3 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [198.145.29.96 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\tLinus Walleij ,\n\tBjorn Andersson ,\n\tDavid Brown ,\n\t\"thierry.reding@gmail.com\" ,\n\tAndy Gross ,\n\tAndy Shevchenko ,\n\tMika Westerberg ,\n\tanjiandi@codeaurora.org, \"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1780157,"web_url":"http://patchwork.ozlabs.org/comment/1780157/","msgid":"","list_archive_url":null,"date":"2017-10-04T22:41:27","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 10/04/2017 04:50 PM, Stephen Boyd wrote:\n\n>> At the time I wrote that patch, the ACPI tables exposed all of the\n>> GPIOs, even the ones it didn't care about. The new ACPI tables list\n>> only specific GPIOs, and so we no longer need to blindly read the\n>> direction of all GPIOs.\n>>\n> \n> Do you avoid this problem on new ACPI tables because only pins\n> that are able to be read are exposed?\n\nYes. A recent firmware update enabled the \"XPU\" block which is being \nprogrammed with a select subset of individual GPIOs. On our silicon, \neach TLMM GPIO is in a separate 64k page, and so the XPU can block any \nindividual GPIO. Any attempt to touch those registers causes an XPU \nviolation which takes the whole system down.\n\n>>> This is basically a revert of commit 72d320006177 (\"gpio: set up\n>>> initial state from .get_direction()\").\n>>\n>> I would be in favor of either reverting that patch, or moving the\n>> code into gpiochip_add_pin_range().\n> \n> If it's in gpiochip_add_pin_range() would we still read the\n> hardware when creating the pin ranges?\n\nI presume so. The idea is that pinctrl-qdf2xxx/pinctrl-msm only submit \npin ranges that are present in the ACPI tables.\n\n > I don't want to have to> describe pin ranges of \"valid\" pins that \nwon't cause the system\n> to blow up if we touch them, because those pins are never used by\n> Linux so reading them is not useful.\n\nWell, that's exactly what I'm trying to do with current patch set :-) \nIt seems the most logical approach to me. I don't understand the \ndislike for it. What else are pin ranges for, other than to specify \nranges of pins that can be accessed?\n\nAnother alternative was to enumerate all of the GPIOs starting from 0. \nSo the first GPIO in ACPI would be gpio0, regardless of what gpio number \nit actually was. E.g. GPIO 37 would appear as gpio0, GPIO 38 would \nappear as gpio1, and so on. That also worked, but it meant that \ncustomers would need to figure out which GPIO that \"gpio0\" actually \npointed to. That was not acceptable, so I dropped it.\n\nI'm at a loss on how else to do it. I think a gpio_chip.available \ncallback is far less elegant than define pin ranges. There is no chance \nthat unavailable GPIOs can be accessed because the physical addresses \nare not in the msm_pingroup array. That is, groups[0].ctrl_reg == 0, \nnot 0xFF02010000.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"tw4Ml1RO\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"J+158nCz\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"NxRDbCWa\"; \n\tdkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none) header.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=timur@codeaurora.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y6rVt1vzjz9t2Z\n\tfor ;\n\tThu, 5 Oct 2017 09:41:58 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dzsMV-0005W0-4F; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20171004215023.GA457@codeaurora.org>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171004_154151_238116_BEE025D4 ","X-CRM114-Status":"GOOD ( 17.57 )","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.3 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [198.145.29.96 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\tLinus Walleij ,\n\tBjorn Andersson ,\n\tDavid Brown ,\n\t\"thierry.reding@gmail.com\" ,\n\tAndy Gross ,\n\tAndy Shevchenko ,\n\tMika Westerberg ,\n\tanjiandi@codeaurora.org, \"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1781037,"web_url":"http://patchwork.ozlabs.org/comment/1781037/","msgid":"<20171005213035.GF457@codeaurora.org>","list_archive_url":null,"date":"2017-10-05T21:30:35","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":6071,"url":"http://patchwork.ozlabs.org/api/people/6071/","name":"Stephen Boyd","email":"sboyd@codeaurora.org"},"content":"On 10/04, Timur Tabi wrote:\n> On 10/04/2017 04:50 PM, Stephen Boyd wrote:\n> \n> Yes. A recent firmware update enabled the \"XPU\" block which is\n> being programmed with a select subset of individual GPIOs. On our\n> silicon, each TLMM GPIO is in a separate 64k page, and so the XPU\n> can block any individual GPIO. Any attempt to touch those registers\n> causes an XPU violation which takes the whole system down.\n\nYes it's the same sort of design with the hardware I have too.\n\n> \n> >\n> >If it's in gpiochip_add_pin_range() would we still read the\n> >hardware when creating the pin ranges?\n> \n> I presume so. The idea is that pinctrl-qdf2xxx/pinctrl-msm only\n> submit pin ranges that are present in the ACPI tables.\n\nOk.\n\n> \n> > I don't want to have to describe pin ranges of \"valid\" pins that\n> > won't cause the system\n> > to blow up if we touch them, because those pins are never used by\n> > Linux so reading them is not useful.\n> \n> Well, that's exactly what I'm trying to do with current patch set\n> :-) It seems the most logical approach to me. I don't understand\n> the dislike for it. What else are pin ranges for, other than to\n> specify ranges of pins that can be accessed?\n\nI have no idea. To describe non-contiguous pin ranges? Linus?\n\n> \n> Another alternative was to enumerate all of the GPIOs starting from\n> 0. So the first GPIO in ACPI would be gpio0, regardless of what gpio\n> number it actually was. E.g. GPIO 37 would appear as gpio0, GPIO 38\n> would appear as gpio1, and so on. That also worked, but it meant\n> that customers would need to figure out which GPIO that \"gpio0\"\n> actually pointed to. That was not acceptable, so I dropped it.\n\nAgreed.\n\n> \n> I'm at a loss on how else to do it. I think a gpio_chip.available\n> callback is far less elegant than define pin ranges. There is no\n> chance that unavailable GPIOs can be accessed because the physical\n> addresses are not in the msm_pingroup array. That is,\n> groups[0].ctrl_reg == 0, not 0xFF02010000.\n> \n\nYes, thinking more about it I don't want an available callback\neither. It will add burden on DT platforms where we have to\ndescribe per-firmware pin ranges just because gpiolib is reading\nthe direction of gpios we don't use.\n\nInstead, I'd prefer we delay reading the direction until a\nconsumer requests the gpio, this way we don't touch the hardware\nunless a consumer wants to. That seems simpler and doesn't\nrequire anything special from the driver.\n\nDon't get me wrong, I'm willing to describe with DT/ACPI which\npins are available if we have a need for it, but so far I don't\nsee the requirement and I'm a lazy person so I like avoiding more\nwork.\n\nDoes my patch fail on your platform for some reason? I can only\nguess that somewhere we don't request the gpio before using it\nand then you don't see the proper direction.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"eAJ4yrgP\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"PaVOFZKj\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"Svmg3R56\"; \n\tdkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none) header.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=sboyd@codeaurora.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y7Qtg3kMHz9t2Z\n\tfor ;\n\tFri, 6 Oct 2017 08:31:05 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e0DjR-0004mQ-CH; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1782079,"web_url":"http://patchwork.ozlabs.org/comment/1782079/","msgid":"","list_archive_url":null,"date":"2017-10-07T11:07:50","subject":"Re: [PATCH 1/2] [v5] pinctrl: qcom: disable GPIO groups with no pins","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Mon, Oct 2, 2017 at 10:47 PM, Timur Tabi wrote:\n> On 10/02/2017 12:44 PM, Bjorn Andersson wrote:\n>>>\n>>> + /*\n>>> + * If irq_need_valid_mask is true, then gpiochip_add_data() will\n>>> + * initialize irq_valid_mask to all 1s. We need to clear all the\n>>> + * GPIOs that are unavailable, and we need to find each block\n>>> + * of consecutive available GPIOs are add them as pin ranges.\n>>> + */\n>>> + if (chip->irq_need_valid_mask) {\n>>> + for (i = 0; i < ngpio; i++)\n>>> + if (!groups[i].npins)\n>>> + clear_bit(i, pctrl->chip.irq_valid_mask);\n>>> +\n>>> + while ((count = msm_gpio_get_next_range(pctrl, &start)))\n>>> {\n>>> + ret = gpiochip_add_pin_range(&pctrl->chip,\n>>> +\n>>> dev_name(pctrl->dev),\n>>> + start, start,\n>>> count);\n>>> + if (ret)\n>>> + break;\n>>> + start += count;\n>>\n>> I do not fancy the idea of specifying a bitmap of valid irq pins and\n>> then having the driver register the pin-ranges in-between.\n>\n> But that's exactly what abx500_gpio_probe() in pinctrl-abx500.c does. Here's\n> even a reference to holes in the GPIO space:\n\nThis driver is not a good example of what is desireable.\n\nI am sorry that the kernel contains a lot of bad examples. These\nare historical artifacts, they cannot be used as an argument to write\ncode in the same style.\n\n>> If we provide\n>>\n>> a bitmap of validity to the core it should support using this for the\n>> pins as well. (Which I believe is what Linus answered in the discussion\n>> following patch 0/2)\n>\n> So you want to change \"gpio_chip\" to add an \"available\" callback? And every\n> time gpiolib wants to call a gpio_chip callback, it should call ->available\n> first? Like this:\n>\n> if (chip->available && chip->available())\n> status = chip->direction_input(chip, gpio_chip_hwgpio(desc));\n\nI mean that you add\nunsigned long *line_valid_mask;\nto struct gpio_chip using the same type of logic\nas .irq_valid_mask. The mask should be optional.\n\nThen the operation gpiod_get[_index]() will FAIL if the\nline is not valid.\n\nThere is no need to check on every operation, there should\nbe no way to get a handle on the pin any other way.\n\nAll new code should be using descriptors at this point so we\nonly need to design for that case.\n\nYours,\nLinus Walleij","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"KXlk9zaN\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"OAuxvZNG\"; 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s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:To:Subject:Message-ID:Date:From:\n\tReferences:In-Reply-To:MIME-Version:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=dH+F7UwPX9v+iZ8Jr7Io9bZ1Sx+1+yGJ+x14Q87X7Co=;\n\tb=KXlk9zaNm+q9nh\n\tR1cDVKACZ2Tf1QByFhcx/MBX3mLCEaZbkzSHlMUY8o3GhYHZEyaWton1VRbVYcx/ktS05aIOfoxzZ\n\t8n2db5zF74FtYRAoy/1nl7yvTVFEClmTkFpKxlrbRvZwUJNxBTDZsbLlt9bDqZZaOC5a1tZpGl87B\n\tQFpPYCn5CRVWtRDE+pQe3a20zwh+/CQeXkhawenqJdFzSHF7eG7J2YLZJhpkmb9y84chHbHmjc8C1\n\thJoAnC728rEFfw0MUOtO5DIEvhu7gk4m9zrgHqY1N/LKdLy0xtwGw1equIFvmAxYUeymetK2lDuWh\n\tdCCe0PkMUXqQnfRAFuRQ==;","v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=w3VcogT5xw8PNiUht3azU7HmAy/aZxi1uzLeullcIoI=;\n\tb=OAuxvZNGIGmrIC5TW7WKzZsAMFm3pxLa+UZQQQHXgdWG65O3F+W23EwoPFaZVqXLxC\n\tkzE+0U0rYoWrghBWpuFHVQMvxNsX0+UgOluaJNHmfFksC+VebUnjT9zlfIeH2FGZ/lWy\n\tKCkwVHAHHzKI9wYoxaSuFBLPPq4OBIGFq7z7g="],"X-Google-DKIM-Signature":"v=1; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1784352,"web_url":"http://patchwork.ozlabs.org/comment/1784352/","msgid":"","list_archive_url":null,"date":"2017-10-11T07:51:08","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Wed, Oct 4, 2017 at 12:03 AM, Stephen Boyd wrote:\n\n> Could we remove the pin direction finding part here in\n> gpiochip_add_pin_range() and lazily resolve the pin direction\n> when a pin is requested? We would need a similar check in the msm\n> specific debugfs code where we skip pins that aren't requested.\n> This is basically a revert of commit 72d320006177 (\"gpio: set up\n> initial state from .get_direction()\").\n\nIt seems reasonable for the gpiolib to be able to call this\nfunction immediately after registering the new GPIO chip\nwith its vtable.\n\nI think it is more up to the driver to numb the reply with\nsome dummy return value (i.e. input mode) or refactor the\ncallback so that it is acceptable for gpiolib to get an -EINVAL\nor so from the driver (again it will assume input mode) if the\ndriver can't return the direction at this time.\n\nYours,\nLinus Walleij","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1785182,"web_url":"http://patchwork.ozlabs.org/comment/1785182/","msgid":"<20171012073922.GB18706@codeaurora.org>","list_archive_url":null,"date":"2017-10-12T07:39:22","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":6071,"url":"http://patchwork.ozlabs.org/api/people/6071/","name":"Stephen Boyd","email":"sboyd@codeaurora.org"},"content":"On 10/11, Linus Walleij wrote:\n> On Wed, Oct 4, 2017 at 12:03 AM, Stephen Boyd wrote:\n> \n> > Could we remove the pin direction finding part here in\n> > gpiochip_add_pin_range() and lazily resolve the pin direction\n> > when a pin is requested? We would need a similar check in the msm\n> > specific debugfs code where we skip pins that aren't requested.\n> > This is basically a revert of commit 72d320006177 (\"gpio: set up\n> > initial state from .get_direction()\").\n> \n> It seems reasonable for the gpiolib to be able to call this\n> function immediately after registering the new GPIO chip\n> with its vtable.\n\nI agree. I don't see the benefit though. Reading the direction\nlater would achieve the same effect and also work for ACPI qcom\nplatforms.\n\n> \n> I think it is more up to the driver to numb the reply with\n> some dummy return value (i.e. input mode) or refactor the\n> callback so that it is acceptable for gpiolib to get an -EINVAL\n> or so from the driver (again it will assume input mode) if the\n> driver can't return the direction at this time.\n> \n\nFor qcom platforms the driver will never be able to return the\ndirection for these certain pins because reading the register is\nnot allowed by the firmware. Doing so will cause the device to\ncrash with a security violation.\n\nIf you don't want to delay reading the direction until request\ntime, we should have the DT msm pinctrl drivers leave the\nget_direction() pointer as NULL. We don't need to read the\ndirection on DT platforms to make anything work.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"GRIfXyNn\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=infradead.org header.i=@infradead.org\n\theader.b=\"sLNkJioM\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"cXRrydk8\"; \n\tdkim=neutral (0-bit key) header.d=codeaurora.org\n\theader.i=@codeaurora.org\n\theader.b=\"cXRrydk8\"; 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a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507793966;\n\tbh=dSEvhKnV+4a3YMpgySiIC61vNggmj3t42QrwSgdLYa8=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=cXRrydk82pBDj0jjAHYR0AQxJvu8jDzYat3PvtSE3gqf6Lrp3mYuq+s+vWXzWG1gN\n\towNqXxYFtCAg7rUdWN9s9bEm3vaVlAUX+RA8/TcG39i9eZKYx/EIJ8+3JHE24QAGyt\n\tNihHajOvHwsc2ZJ4UMWk0fThYEl6ZWMJg8991U44="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org 542B5607CC","Date":"Thu, 12 Oct 2017 00:39:22 -0700","From":"Stephen Boyd ","To":"Linus Walleij ","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","Message-ID":"<20171012073922.GB18706@codeaurora.org>","References":"\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t\n\t\n\t<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>\n\t\n\t<255ad0dc-2d16-ae7f-0b45-500e23cff1a4@codeaurora.org>\n\t<20171003220311.GU457@codeaurora.org>\n\t","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"","User-Agent":"Mutt/1.5.21 (2010-09-15)","X-Spam-Note":"CRM114 invocation failed","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on merlin.infradead.org summary:\n\tContent analysis details: (-4.3 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [198.145.29.96 listed in list.dnswl.org]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\tTimur Tabi ,\n\tBjorn Andersson ,\n\tDavid Brown ,\n\t\"thierry.reding@gmail.com\" ,\n\tAndy Gross ,\n\tAndy Shevchenko ,\n\tMika Westerberg ,\n\tanjiandi@codeaurora.org, \"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1786735,"web_url":"http://patchwork.ozlabs.org/comment/1786735/","msgid":"<4f067c09-9ecf-9266-baa0-18575bca94eb@codeaurora.org>","list_archive_url":null,"date":"2017-10-13T23:26:23","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 10/03/2017 05:03 PM, Stephen Boyd wrote:\n> I don't see any value\n> beyond system wide debug in figuring out the default pin\n> configuration of a pin that doesn't have a consumer in Linux.\n\nI can agree with that.\n\n> Could we remove the pin direction finding part here in\n> gpiochip_add_pin_range() and lazily resolve the pin direction\n> when a pin is requested? We would need a similar check in the msm\n> specific debugfs code where we skip pins that aren't requested.\n> This is basically a revert of commit 72d320006177 (\"gpio: set up\n> initial state from .get_direction()\").\n> \n> ACPI can still describe only the pin ranges that they care about\n> exposing, but from the devicetree side it's been working well\n> enough to not touch pins that aren't used by anything in Linux.\n> \n> ---8<----\n> diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c\n> index cd003b74512f..673028823bc5 100644\n> --- a/drivers/gpio/gpiolib.c\n> +++ b/drivers/gpio/gpiolib.c\n> @@ -1210,16 +1210,7 @@ int gpiochip_add_data(struct gpio_chip *chip, void *data)\n> \t\t * wrong direction in sysfs.\n> \t\t */\n> \n> -\t\tif (chip->get_direction) {\n> -\t\t\t/*\n> -\t\t\t * If we have .get_direction, set up the initial\n> -\t\t\t * direction flag from the hardware.\n> -\t\t\t */\n> -\t\t\tint dir = chip->get_direction(chip, i);\n> -\n> -\t\t\tif (!dir)\n> -\t\t\t\tset_bit(FLAG_IS_OUT, &desc->flags);\n> -\t\t} else if (!chip->direction_input) {\n> +\t\tif (!chip->direction_input) {\n> \t\t\t/*\n> \t\t\t * If the chip lacks the .direction_input callback\n> \t\t\t * we logically assume all lines are outputs.\n> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c\n> index 273badd92561..4a0aeceb42f1 100644\n> --- a/drivers/pinctrl/qcom/pinctrl-msm.c\n> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c\n> @@ -24,7 +24,7 @@\n> #include \n> #include \n> #include \n> -#include \n> +#include \n> #include \n> #include \n> #include \n> @@ -494,6 +494,12 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,\n> \t};\n> \n> \tg = &pctrl->soc->groups[offset];\n> +\n> +\tif (!gpiochip_is_requested(chip, gpio)) {\n> +\t\tseq_printf(s, \" %-8s:\", g->name);\n> +\t\treturn;\n> +\t}\n> +\n> \tctl_reg = readl(pctrl->regs + g->ctl_reg);\n> \n> \tis_out = !!(ctl_reg & BIT(g->oe_bit));\n\nIn order for this to work, I had to add this function from patch #1:\n\nstatic int msm_gpio_request(struct gpio_chip *chip, unsigned int offset)\n{\n\tstruct msm_pinctrl *pctrl = gpiochip_get_data(chip);\n\tconst struct msm_pingroup *g = &pctrl->soc->groups[offset];\n\n\tif (!g->npins)\n\t\treturn -ENODEV;\n\n\treturn gpiochip_generic_request(chip, offset);\n}\n\nThe problem with this is that none of the GPIOs are \"requested\", so it \ndisplays an output like this:\n\n# cat /sys/kernel/debug/gpio\ngpiochip0: GPIOs 0-149, parent: platform/QCOM8002:00, QCOM8002:00:\n (null) :\n (null) :\n (null) :\n[... truncated ]]\n (null) :\n (null) :\n (null) :\n (null) :\n gpio36 :\n gpio37 :\n gpio38 :\n gpio39 :\n (null) :\n (null) :\n\nIt can't differentiate between GPIOs that don't exist and GPIOs that \nhaven't been requested. Plus, the \"(null)\" entries are what I've been \ntrying to avoid in the first place.\n\nSo overall, this patch seems okay, although it needs a little work. \nHowever, it doesn't address Bjorn's complaint that he doesn't want me to \nuse pin ranges at all.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"gxdhgYmz\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"ICTwwFME\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"ICTwwFME\"; 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a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507937185;\n\tbh=6w59syL+nzs2bEgbx4OqrsU6udg43NF4I/NMX/oDRs0=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=ICTwwFMEYCaDzadE0pTMVSnGIaM5YSkIQGcX5GIwz5ytgbGVhYwnrJNwjqxKWGC23\n\t+LKn+7e1m3zFGZxKLUr+kf1lqzpOz0Arek7aHj3yS5KVXjcfru0iNxQhgIMPExbm9U\n\tTDEvTUq2HQ3yaMYlUAx1i4fyQmYbamfZKOMe3k9M="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org 0716761424","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Stephen Boyd ","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<20170919070422.GI3349@codeaurora.org>\n\t\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t\n\t\n\t<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>\n\t\n\t<255ad0dc-2d16-ae7f-0b45-500e23cff1a4@codeaurora.org>\n\t<20171003220311.GU457@codeaurora.org>","From":"Timur Tabi ","Message-ID":"<4f067c09-9ecf-9266-baa0-18575bca94eb@codeaurora.org>","Date":"Fri, 13 Oct 2017 18:26:23 -0500","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20171003220311.GU457@codeaurora.org>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171013_162646_948175_587843DA ","X-CRM114-Status":"GOOD ( 21.70 )","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.3 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [198.145.29.96 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\tLinus Walleij ,\n\tBjorn Andersson ,\n\tDavid Brown ,\n\t\"thierry.reding@gmail.com\" ,\n\tAndy Gross ,\n\tAndy Shevchenko ,\n\tMika Westerberg ,\n\tanjiandi@codeaurora.org, \"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1786737,"web_url":"http://patchwork.ozlabs.org/comment/1786737/","msgid":"<2be95dec-5e53-71b4-1b08-3e8dd45ca30c@codeaurora.org>","list_archive_url":null,"date":"2017-10-13T23:35:59","subject":"Re: [PATCH 1/2] [v5] pinctrl: qcom: disable GPIO groups with no pins","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 10/07/2017 06:07 AM, Linus Walleij wrote:\n> I mean that you add\n> unsigned long *line_valid_mask;\n> to struct gpio_chip using the same type of logic\n> as .irq_valid_mask. The mask should be optional.\n\nHmmm okay\n\n> Then the operation gpiod_get[_index]() will FAIL if the\n> line is not valid.\n\nJust to be clear, you want gpiod_get_index() to check line_valid_mask \n(if present) and return -ENODEV if not valid?\n\n> There is no need to check on every operation, there should\n> be no way to get a handle on the pin any other way.\n> \n> All new code should be using descriptors at this point so we\n> only need to design for that case.\n\nOk, I will check this.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"MaixnG+a\"; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171013_163621_670632_4697CDCF ","X-CRM114-Status":"GOOD ( 12.81 )","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.3 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [198.145.29.96 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\tanjiandi@codeaurora.org, Bjorn Andersson ,\n\tDavid Brown ,\n\tAndy Gross , \n\t\"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1786916,"web_url":"http://patchwork.ozlabs.org/comment/1786916/","msgid":"","list_archive_url":null,"date":"2017-10-14T22:43:16","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Thu, Oct 12, 2017 at 9:39 AM, Stephen Boyd wrote:\n\n> For qcom platforms the driver will never be able to return the\n> direction for these certain pins because reading the register is\n> not allowed by the firmware. Doing so will cause the device to\n> crash with a security violation.\n\nSo I guess the driver needs to know what pin registers it can't\naccess so the user does not get a gun to shoot in the foot with.\n\nIf we augment gpiolib to just handle -EACCES or something\n(-EIO?) from the driver .get_direction() callback for these lines,\nthings should be smooth?\n\nYours,\nLinus Walleij","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"Rb7o8J6R\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"DjaghxPR\"; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1787068,"web_url":"http://patchwork.ozlabs.org/comment/1787068/","msgid":"<20171015201811.GA13063@mithrandir>","list_archive_url":null,"date":"2017-10-15T20:18:13","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":26234,"url":"http://patchwork.ozlabs.org/api/people/26234/","name":"Thierry Reding","email":"thierry.reding@gmail.com"},"content":"On Fri, Oct 13, 2017 at 06:26:23PM -0500, Timur Tabi wrote:\n> On 10/03/2017 05:03 PM, Stephen Boyd wrote:\n> > I don't see any value\n> > beyond system wide debug in figuring out the default pin\n> > configuration of a pin that doesn't have a consumer in Linux.\n> \n> I can agree with that.\n> \n> > Could we remove the pin direction finding part here in\n> > gpiochip_add_pin_range() and lazily resolve the pin direction\n> > when a pin is requested? We would need a similar check in the msm\n> > specific debugfs code where we skip pins that aren't requested.\n> > This is basically a revert of commit 72d320006177 (\"gpio: set up\n> > initial state from .get_direction()\").\n> > \n> > ACPI can still describe only the pin ranges that they care about\n> > exposing, but from the devicetree side it's been working well\n> > enough to not touch pins that aren't used by anything in Linux.\n> > \n> > ---8<----\n> > diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c\n> > index cd003b74512f..673028823bc5 100644\n> > --- a/drivers/gpio/gpiolib.c\n> > +++ b/drivers/gpio/gpiolib.c\n> > @@ -1210,16 +1210,7 @@ int gpiochip_add_data(struct gpio_chip *chip, void *data)\n> > \t\t * wrong direction in sysfs.\n> > \t\t */\n> > -\t\tif (chip->get_direction) {\n> > -\t\t\t/*\n> > -\t\t\t * If we have .get_direction, set up the initial\n> > -\t\t\t * direction flag from the hardware.\n> > -\t\t\t */\n> > -\t\t\tint dir = chip->get_direction(chip, i);\n> > -\n> > -\t\t\tif (!dir)\n> > -\t\t\t\tset_bit(FLAG_IS_OUT, &desc->flags);\n> > -\t\t} else if (!chip->direction_input) {\n> > +\t\tif (!chip->direction_input) {\n> > \t\t\t/*\n> > \t\t\t * If the chip lacks the .direction_input callback\n> > \t\t\t * we logically assume all lines are outputs.\n> > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c\n> > index 273badd92561..4a0aeceb42f1 100644\n> > --- a/drivers/pinctrl/qcom/pinctrl-msm.c\n> > +++ b/drivers/pinctrl/qcom/pinctrl-msm.c\n> > @@ -24,7 +24,7 @@\n> > #include \n> > #include \n> > #include \n> > -#include \n> > +#include \n> > #include \n> > #include \n> > #include \n> > @@ -494,6 +494,12 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,\n> > \t};\n> > \tg = &pctrl->soc->groups[offset];\n> > +\n> > +\tif (!gpiochip_is_requested(chip, gpio)) {\n> > +\t\tseq_printf(s, \" %-8s:\", g->name);\n> > +\t\treturn;\n> > +\t}\n> > +\n> > \tctl_reg = readl(pctrl->regs + g->ctl_reg);\n> > \tis_out = !!(ctl_reg & BIT(g->oe_bit));\n> \n> In order for this to work, I had to add this function from patch #1:\n> \n> static int msm_gpio_request(struct gpio_chip *chip, unsigned int offset)\n> {\n> \tstruct msm_pinctrl *pctrl = gpiochip_get_data(chip);\n> \tconst struct msm_pingroup *g = &pctrl->soc->groups[offset];\n> \n> \tif (!g->npins)\n> \t\treturn -ENODEV;\n> \n> \treturn gpiochip_generic_request(chip, offset);\n> }\n> \n> The problem with this is that none of the GPIOs are \"requested\", so it\n> displays an output like this:\n> \n> # cat /sys/kernel/debug/gpio\n> gpiochip0: GPIOs 0-149, parent: platform/QCOM8002:00, QCOM8002:00:\n> (null) :\n> (null) :\n> (null) :\n> [... truncated ]]\n> (null) :\n> (null) :\n> (null) :\n> (null) :\n> gpio36 :\n> gpio37 :\n> gpio38 :\n> gpio39 :\n> (null) :\n> (null) :\n> \n> It can't differentiate between GPIOs that don't exist and GPIOs that haven't\n> been requested.\n\nThis confuses me. Why would you even want to register pins that don't\nexist? It sounds to me like you're lying to gpiolib and then try to work\naround it trying to access the GPIOs that don't exist but which you told\nit were there.\n\nWhy not just tell gpiolib about only the GPIOs that exist?\n\nThierry","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"Q7eG1dkW\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"b6EN83aB\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yFXpY2r5rz9sRn\n\tfor ;\n\tMon, 16 Oct 2017 07:18:45 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e3pMw-00053X-2Y; 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Why would you even want to register pins that don't\n> exist? It sounds to me like you're lying to gpiolib and then try to work\n> around it trying to access the GPIOs that don't exist but which you told\n> it were there.\n> \n> Why not just tell gpiolib about only the GPIOs that exist?\n\nPlease look at my patches. That's exactly what they do, but no one else \nlikes that approach.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"NGH+N7+W\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"oH3i2EW7\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"oH3i2EW7\"; \n\tdkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none) header.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=timur@codeaurora.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yFYxW6r1Jz9sRq\n\tfor ;\n\tMon, 16 Oct 2017 08:09:50 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e3qAM-0006eY-Rh; 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Intel Mac OS X 10.9; rv:52.0)\n\tGecko/20100101 Thunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20171015201811.GA13063@mithrandir>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171015_140943_442303_395609D3 ","X-CRM114-Status":"GOOD ( 11.58 )","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.3 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [198.145.29.96 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\tLinus Walleij ,\n\tStephen Boyd , \n\tBjorn Andersson ,\n\tDavid Brown ,\n\tAndy Gross , \n\tAndy Shevchenko ,\n\tMika Westerberg ,\n\tanjiandi@codeaurora.org, \"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1787204,"web_url":"http://patchwork.ozlabs.org/comment/1787204/","msgid":"<20171016080117.GA17369@ulmo>","list_archive_url":null,"date":"2017-10-16T08:01:17","subject":"Re: [PATCH 1/2] [v5] pinctrl: qcom: disable GPIO groups with no pins","submitter":{"id":26234,"url":"http://patchwork.ozlabs.org/api/people/26234/","name":"Thierry Reding","email":"thierry.reding@gmail.com"},"content":"On Thu, Sep 07, 2017 at 10:33:28AM -0500, Timur Tabi wrote:\n[...]\n> \tret = gpiochip_add_data(&pctrl->chip, pctrl);\n> \tif (ret) {\n> \t\tdev_err(pctrl->dev, \"Failed register gpiochip\\n\");\n> \t\treturn ret;\n> \t}\n> \n> -\tret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);\n> +\t/*\n> +\t * If irq_need_valid_mask is true, then gpiochip_add_data() will\n> +\t * initialize irq_valid_mask to all 1s. We need to clear all the\n> +\t * GPIOs that are unavailable, and we need to find each block\n> +\t * of consecutive available GPIOs are add them as pin ranges.\n> +\t */\n> +\tif (chip->irq_need_valid_mask) {\n> +\t\tfor (i = 0; i < ngpio; i++)\n> +\t\t\tif (!groups[i].npins)\n> +\t\t\t\tclear_bit(i, pctrl->chip.irq_valid_mask);\n> +\n> +\t\twhile ((count = msm_gpio_get_next_range(pctrl, &start))) {\n> +\t\t\tret = gpiochip_add_pin_range(&pctrl->chip,\n> +\t\t\t\t\t\t dev_name(pctrl->dev),\n> +\t\t\t\t\t\t start, start, count);\n> +\t\t\tif (ret)\n> +\t\t\t\tbreak;\n> +\t\t\tstart += count;\n> +\t\t}\n> +\t} else {\n> +\t\tret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),\n> +\t\t\t\t\t 0, 0, ngpio);\n> +\t}\n\nThis is the bit that I don't understand. If you only tell gpiolib about\nthe GPIOs that exist, then it won't be initializing the .irq_valid_mask\nin a wrong way.\n\nIn other words, what I'm trying to say is that in your case, ngpio isn't\nequal to the sum of .npins over all groups. If instead you make the chip\nregister only the lines that actually exist, .irq_valid_mask will only\ncontain bits that do exist.\n\nThe reason I'm bringing this up is because we had the same discussion\nback in November last year (yes, that driver still isn't upstream...):\n\n\thttps://lkml.org/lkml/2016/11/22/543\n\nIn a nutshell: the Tegra driver was assuming that each port had a fixed\nnumber (8) of lines, but when gpiolib changed to query the direction of\nGPIOs at driver probe time this broke badly because on of the instances\nof the GPIO controller is very strict about what it allows access to.\n\nThis seems to be similar to what you're experiencing. In our case we'd\nrun into a hard hang trying to access a register for a non-existing\nGPIO. One of the possibilities discussed in the thread was to introduce\nsomething akin to what's being proposed here.\n\nIn the end it turned out to be easiest to just don't tell gpiolib about\nany non-existing GPIOs, because then you don't get to deal with any of\nthese workarounds. The downside is that you need a little more code to\nfind out exactly what GPIO you're talking about, or to determine how\nmany you have. In the end I think it's all worth it by making it a lot\neasier in general to deal with. I think it's really confusing if you\nexpose, say, 200 pins, and for 50 of them users will get -EACCES, or\n-ENOENT or whatever if they try to use them.\n\nThierry","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"Rh4DCNqh\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"oglZsipx\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yFrQP3k1vz9sDB\n\tfor ;\n\tMon, 16 Oct 2017 19:02:21 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e40Lo-0000V9-10; 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\n\tMon, 16 Oct 2017 01:01:20 -0700 (PDT)","Date":"Mon, 16 Oct 2017 10:01:17 +0200","From":"Thierry Reding ","To":"Timur Tabi ","Subject":"Re: [PATCH 1/2] [v5] pinctrl: qcom: disable GPIO groups with no pins","Message-ID":"<20171016080117.GA17369@ulmo>","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<1504798409-32041-2-git-send-email-timur@codeaurora.org>","MIME-Version":"1.0","In-Reply-To":"<1504798409-32041-2-git-send-email-timur@codeaurora.org>","User-Agent":"Mutt/1.9.1 (2017-09-22)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171016_010142_197832_4DC72AE7 ","X-CRM114-Status":"GOOD ( 19.78 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (thierry.reding[at]gmail.com)\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n\tLinus Walleij ,\n\tBjorn Andersson , david.brown@linaro.org, \n\tandy.gross@linaro.org, anjiandi@codeaurora.org,\n\tlinux-arm-kernel@lists.infradead.org","Content-Type":"multipart/mixed;\n\tboundary=\"===============7448033305941038858==\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1787456,"web_url":"http://patchwork.ozlabs.org/comment/1787456/","msgid":"<9c142b32-5f14-38c5-3611-884f2589d682@codeaurora.org>","list_archive_url":null,"date":"2017-10-16T13:52:09","subject":"Re: [PATCH 1/2] [v5] pinctrl: qcom: disable GPIO groups with no pins","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 10/16/2017 03:01 AM, Thierry Reding wrote:\n> This is the bit that I don't understand. If you only tell gpiolib about\n> the GPIOs that exist, then it won't be initializing the .irq_valid_mask\n> in a wrong way.\n\nI know, and that's what my patches do. I tell gpiolib that I need a \nvalid mask:\n\n/* If the GPIO map is sparse, then we need to disable specific IRQs */\nchip->irq_need_valid_mask = pctrl->soc->sparse;\n\nThen I proceed to provide the specific GPIOs that exist, one block at a \ntime:\n\n\tret = gpiochip_add_pin_range(&pctrl->chip,\n\t\t\t\t dev_name(pctrl->dev),\n\t\t\t\t start, start, count);\n\n> In other words, what I'm trying to say is that in your case, ngpio isn't\n> equal to the sum of .npins over all groups.\n\nThat's true. I set it to the maximum number of GPIOs that exist on the \nchip. I could set it to the highest number of GPIOs that I register \n(e.g. the highest value of \"start + count\"), but that's not necessary \nfor my patches to work.\n\n> If instead you make the chip\n> register only the lines that actually exist, .irq_valid_mask will only\n> contain bits that do exist.\n\nThat's what I'm doing.\n\n> The reason I'm bringing this up is because we had the same discussion\n> back in November last year (yes, that driver still isn't upstream...):\n> \n> \thttps://lkml.org/lkml/2016/11/22/543\n> \n> In a nutshell: the Tegra driver was assuming that each port had a fixed\n> number (8) of lines, but when gpiolib changed to query the direction of\n> GPIOs at driver probe time this broke badly because on of the instances\n> of the GPIO controller is very strict about what it allows access to.\n\nIt appear we're re-hashing that same exact argument.\n\n> This seems to be similar to what you're experiencing. In our case we'd\n> run into a hard hang trying to access a register for a non-existing\n> GPIO. One of the possibilities discussed in the thread was to introduce\n> something akin to what's being proposed here.\n\nI guess great minds do think alike!\n\n> In the end it turned out to be easiest to just don't tell gpiolib about\n> any non-existing GPIOs, because then you don't get to deal with any of\n> these workarounds.\n\nI agree.\n\n> The downside is that you need a little more code to\n> find out exactly what GPIO you're talking about, or to determine how\n> many you have.\n\nIn my case, the ACPI table provides an exact list that I use at probe() \ntime.\n\n> In the end I think it's all worth it by making it a lot\n> easier in general to deal with. I think it's really confusing if you\n> expose, say, 200 pins, and for 50 of them users will get -EACCES, or\n> -ENOENT or whatever if they try to use them.\n\nTrue, but /sys/kernel/debug/gpio is the only mechanism I found where the \nuser can get a list of valid GPIOs. Maybe we need something similar in \n/sys/class/gpio/.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"TeTC+xu1\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"lzER1yru\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"o9YmFmxP\"; \n\tdkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none) header.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=timur@codeaurora.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yG0WM6glDz9s7M\n\tfor ;\n\tTue, 17 Oct 2017 01:07:11 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e462s-0008An-Eq; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20171016080117.GA17369@ulmo>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171016_065235_768821_CB839AC7 ","X-CRM114-Status":"GOOD ( 22.85 )","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.3 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [198.145.29.96 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n\tLinus Walleij ,\n\tBjorn Andersson , david.brown@linaro.org, \n\tandy.gross@linaro.org, anjiandi@codeaurora.org,\n\tlinux-arm-kernel@lists.infradead.org","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1791012,"web_url":"http://patchwork.ozlabs.org/comment/1791012/","msgid":"<819a0c67-3494-030d-3166-748081509c83@codeaurora.org>","list_archive_url":null,"date":"2017-10-19T22:44:59","subject":"Re: [PATCH 1/2] [v5] pinctrl: qcom: disable GPIO groups with no pins","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 10/07/2017 06:07 AM, Linus Walleij wrote:\n> I mean that you add\n> unsigned long *line_valid_mask;\n> to struct gpio_chip using the same type of logic\n> as .irq_valid_mask. The mask should be optional.\n> \n> Then the operation gpiod_get[_index]() will FAIL if the\n> line is not valid.\n> \n> There is no need to check on every operation, there should\n> be no way to get a handle on the pin any other way.\n> \n> All new code should be using descriptors at this point so we\n> only need to design for that case.\n\nI think I'm missing something, because I implemented what you're asking \nfor, but whenever I try to expose a GPIO from sysfs (e.g. echo 37 > \n/sys/class/gpio/export), gpiod_get_index() is not called. The only \nthing preventing the GPIO from being exported is the ->request callback:\n\nstatic int msm_gpio_request(struct gpio_chip *chip, unsigned int offset)\n{\n\tstruct msm_pinctrl *pctrl = gpiochip_get_data(chip);\n\tconst struct msm_pingroup *g = &pctrl->soc->groups[offset];\n\n\tif (!g->npins)\n\t\treturn -ENODEV;\n\nWhat operation is supposed to trigger a call to gpiod_get_index?","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"lKzPnOZn\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"ZKBa9Iz/\"; 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Thu, 19 Oct 2017 22:45:01 +0000 (UTC)","from [10.222.143.167] (i-global254.qualcomm.com [199.106.103.254])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\t(Authenticated sender: timur@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id 90FE760351;\n\tThu, 19 Oct 2017 22:45:00 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type:\n\tContent-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive:\n\tList-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From:\n\tReferences:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;\n\tbh=FzhXi2tfmQQ+Vf/9ooY8fP3gdhN3uFH7YgePIriRc54=;\n\tb=lKzPnOZn+QxpTY5fxm48Atsrf\n\tvxQBfRPU/oTtXduIDTgvpmbxD+Nvvw/L4EfjESHUY8ZslNBRENmdddy4XuK1df5rmL2p2nZve0frm\n\tf6RXjsaoHFmN6z3MyLAjCsXTeRmHskPLXqBGlmkLO4r+sTj++zhROhwxNehRj4+TtZD3nHXK7a4dM\n\tLcVwxas4r/GCDD/pGVJIRv4VG/VSTBx/EHsObDouDXAi0wP8XMFZQJ04D/9b4VDB9emQCEBdW2EGE\n\tK5w7dDaILh2xH2PpePbxsswZkr8+9VFpDxi+FR0KRAR3vScAG3lz7jpA5iEuX7PacclEtxiKncIV/\n\tDASE6SLhQ==;","v=1; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171019_154518_033746_2B281EBC ","X-CRM114-Status":"GOOD ( 16.85 )","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.3 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [198.145.29.96 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\tanjiandi@codeaurora.org, Bjorn Andersson ,\n\tDavid Brown ,\n\tAndy Gross , \n\t\"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}}]