[{"id":1765307,"web_url":"http://patchwork.ozlabs.org/comment/1765307/","msgid":"","list_archive_url":null,"date":"2017-09-08T12:50:04","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Thu, Sep 7, 2017 at 5:33 PM, Timur Tabi wrote:\n\n> First patch allows for for pinctrl-msm to understand GPIO groups with\n> no pins. Such pins are \"hidden\" and can't be exported or accessed.\n>\n> Second patch updates the QDF2xxx driver to take advantage of all that.\n>\n> v5:\n> Since gpiochip_add_data no longer requests GPIOs before scanning for\n> the direction (that patch was reverted), pinctrl-msm.c now specifically\n> checks for special case.\n\nWaiting for Bjorn's review on these.\n\nYours,\nLinus Walleij\n--\nTo unsubscribe from this list: send the line \"unsubscribe linux-gpio\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"g0pvB9+9\"; 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charset=\"UTF-8\"","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1768035,"web_url":"http://patchwork.ozlabs.org/comment/1768035/","msgid":"<0dbd161e-5437-7acb-9bc9-4a7b5869a4d7@codeaurora.org>","list_archive_url":null,"date":"2017-09-13T17:09:40","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 09/08/2017 07:50 AM, Linus Walleij wrote:\n>> Since gpiochip_add_data no longer requests GPIOs before scanning for\n>> the direction (that patch was reverted), pinctrl-msm.c now specifically\n>> checks for special case.\n> Waiting for Bjorn's review on these.\n\nBjorn,\n\nDo you think you will have a chance to review these patches in time for \n4.14?","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"BEomJvpW\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"gNRryDk9\"; dkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=timur@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xsp7H1VK0z9s9Y\n\tfor ;\n\tThu, 14 Sep 2017 03:09:47 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751112AbdIMRJp (ORCPT );\n\tWed, 13 Sep 2017 13:09:45 -0400","from smtp.codeaurora.org ([198.145.29.96]:47874 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751101AbdIMRJp (ORCPT\n\t); Wed, 13 Sep 2017 13:09:45 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid 7F3BC60F66; Wed, 13 Sep 2017 17:09:43 +0000 (UTC)","from [10.222.143.167] (i-global254.qualcomm.com [199.106.103.254])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\t(Authenticated sender: timur@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id A878860B71;\n\tWed, 13 Sep 2017 17:09:41 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1505322584;\n\tbh=SkXZc+Jb4G04RMqzFpLHhJciCmJELF+CL3mrcJdnOYo=;\n\th=From:Subject:To:Cc:References:Date:In-Reply-To:From;\n\tb=BEomJvpW9yOdWFNApzOlAO83ESnA4/NLFSuxl7m6k035r4FbvAy24/91ho+PaSJp+\n\ttbTUe3ZxZJX9Ov0k2MuOrWKqrY4UWMJJA+UvxqInlbcbv6qcxlnsMWhyNWITH7AL3w\n\tkDsA4w2Q4cZVGnIporvbcPkD3VQmJ7Z1Kh/Z4LCs=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1505322582;\n\tbh=SkXZc+Jb4G04RMqzFpLHhJciCmJELF+CL3mrcJdnOYo=;\n\th=From:Subject:To:Cc:References:Date:In-Reply-To:From;\n\tb=gNRryDk9DvdiNiPAFSaiH+pj6TXO5OkCEJwdU+ANJk+R4ha920kL50lVIWlW1Iorc\n\tKTpwBfo51q0YWbOrJN7rwiQ7WB6OGGrHmFPXr6mRywg4C/2bLeHSXg94gMcr8vNlcp\n\tJ+skx7ny6/odSIsTCutZ9ATaDu+xD1UPdBhSJD8s="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org A878860B71","From":"Timur Tabi ","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Bjorn Andersson ","Cc":"Linus Walleij ,\n\tAndy Gross ,\n\tDavid Brown , anjiandi@codeaurora.org,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-arm-msm@vger.kernel.org\" ","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t","Message-ID":"<0dbd161e-5437-7acb-9bc9-4a7b5869a4d7@codeaurora.org>","Date":"Wed, 13 Sep 2017 12:09:40 -0500","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1770686,"web_url":"http://patchwork.ozlabs.org/comment/1770686/","msgid":"<20170919070422.GI3349@codeaurora.org>","list_archive_url":null,"date":"2017-09-19T07:04:22","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":6071,"url":"http://patchwork.ozlabs.org/api/people/6071/","name":"Stephen Boyd","email":"sboyd@codeaurora.org"},"content":"On 09/07, Timur Tabi wrote:\n> First patch allows for for pinctrl-msm to understand GPIO groups with\n> no pins. Such pins are \"hidden\" and can't be exported or accessed.\n> \n> Second patch updates the QDF2xxx driver to take advantage of all that.\n> \n> v5:\n> Since gpiochip_add_data no longer requests GPIOs before scanning for\n> the direction (that patch was reverted), pinctrl-msm.c now specifically\n> checks for special case.\n\nCan we add a new gpiochip op that checks for \"availability\". I\nread the other thread where the change was reverted (please add a\npointer next time), and as I understand it the gpio request\nmethod can also change the muxing to a gpio instead of something\nelse. Perhaps we can add another hook for our purposes here that\ntells gpiolib that the gpio is not usable and to skip it. The\nsemantics would be clear, it's just about probing availability of\nthis pin as a gpio and doesn't mux any pins.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"D452G9Z9\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"D452G9Z9\"; dkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=sboyd@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxDR53ddTz9sDB\n\tfor ;\n\tTue, 19 Sep 2017 17:05:21 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751227AbdISHFT (ORCPT );\n\tTue, 19 Sep 2017 03:05:19 -0400","from smtp.codeaurora.org ([198.145.29.96]:51658 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751572AbdISHEq (ORCPT\n\t); Tue, 19 Sep 2017 03:04:46 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid 77AAB6070F; Tue, 19 Sep 2017 07:04:45 +0000 (UTC)","from localhost (i-global254.qualcomm.com [199.106.103.254])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\t(Authenticated sender: sboyd@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id F11DF602A9;\n\tTue, 19 Sep 2017 07:04:44 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1505804685;\n\tbh=nbVdJv8XCe+35DTuFfZEd6shS40UPgJtLtHARHZWOYw=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=D452G9Z9LaoTeN+spgsAkHrd9McoLCqfj1sB2II7JwDbSyXiBzz2QTA/MWkJnrG2N\n\t1/MHnUAhG5clWlRqvjhchPAqSNV4tET9Eniqgs5iu5PmoXtaBFnx5itcCv8QZu7rxc\n\tyN9xMYOWRaAQZFsbOZIB6BuGeJFx+FtgGPfcXhKA=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1505804685;\n\tbh=nbVdJv8XCe+35DTuFfZEd6shS40UPgJtLtHARHZWOYw=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=D452G9Z9LaoTeN+spgsAkHrd9McoLCqfj1sB2II7JwDbSyXiBzz2QTA/MWkJnrG2N\n\t1/MHnUAhG5clWlRqvjhchPAqSNV4tET9Eniqgs5iu5PmoXtaBFnx5itcCv8QZu7rxc\n\tyN9xMYOWRaAQZFsbOZIB6BuGeJFx+FtgGPfcXhKA="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org F11DF602A9","Date":"Tue, 19 Sep 2017 00:04:22 -0700","From":"Stephen Boyd ","To":"Timur Tabi ","Cc":"Linus Walleij , andy.gross@linaro.org,\n\tdavid.brown@linaro.org, anjiandi@codeaurora.org,\n\tBjorn Andersson ,\n\tlinux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-arm-msm@vger.kernel.org","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","Message-ID":"<20170919070422.GI3349@codeaurora.org>","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1770739,"web_url":"http://patchwork.ozlabs.org/comment/1770739/","msgid":"","list_archive_url":null,"date":"2017-09-19T08:15:50","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Tue, Sep 19, 2017 at 9:04 AM, Stephen Boyd wrote:\n\n> Perhaps we can add another hook for our purposes here that\n> tells gpiolib that the gpio is not usable and to skip it. The\n> semantics would be clear, it's just about probing availability of\n> this pin as a gpio and doesn't mux any pins.\n\nOh we already have that I think, Mika Westerberg and Andy Shevcheno\nimplemented that for anyone using CONFIG_GPIOLIB_IRQCHIP, and\nthis driver does. Timur please check: irq_need_valid_mask, irq_valid_mask\nusage.\n\nHelpful commits:\ncommit 49c03096263871a68c9dea3e86b7d1e163d2fba8\n\"pinctrl: baytrail: Do not add all GPIOs to IRQ domain\"\n\nThen you can see in commits:\ncommit 7036502783729c2aaf7a3c24c89087c58721430f\n\"pinctrl: cherryview: Add a quirk to make Acer Chromebook keyboard work again\"\ncommit 2a8209fa68236ad65363dba03db5dbced520268a\n\"pinctrl: cherryview: Extend the Chromebook DMI quirk to Intel_Strago systems\"\n\nHow this valid mask is used to work around specific ACPI\nissues on Intel chips.\n\nI bet a million to one that you have the same problems as them,\nand then we should also deal with it the same way.\n\nSorry for not seeing the obvious connection earlier.\n\nYours,\nLinus Walleij\n--\nTo unsubscribe from this list: send the line \"unsubscribe linux-gpio\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"OzG+Qkdf\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxG0V1fVSz9s7m\n\tfor ;\n\tTue, 19 Sep 2017 18:15:54 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1750938AbdISIPx (ORCPT );\n\tTue, 19 Sep 2017 04:15:53 -0400","from mail-it0-f45.google.com ([209.85.214.45]:43227 \"EHLO\n\tmail-it0-f45.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750982AbdISIPw (ORCPT\n\t); Tue, 19 Sep 2017 04:15:52 -0400","by mail-it0-f45.google.com with SMTP id l136so5571362ita.0\n\tfor ;\n\tTue, 19 Sep 2017 01:15:52 -0700 (PDT)","by 10.79.164.78 with HTTP; Tue, 19 Sep 2017 01:15:50 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; 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Tue,\n\t19 Sep 2017 01:15:51 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170919070422.GI3349@codeaurora.org>","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<20170919070422.GI3349@codeaurora.org>","From":"Linus Walleij ","Date":"Tue, 19 Sep 2017 10:15:50 +0200","Message-ID":"","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Stephen Boyd ","Cc":"Timur Tabi , Andy Gross ,\n\tDavid Brown , anjiandi@codeaurora.org,\n\tBjorn Andersson ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\t\"thierry.reding@gmail.com\" ,\n\tMika Westerberg ,\n\tAndy Shevchenko ","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1770953,"web_url":"http://patchwork.ozlabs.org/comment/1770953/","msgid":"<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>","list_archive_url":null,"date":"2017-09-19T12:32:22","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 9/19/17 3:15 AM, Linus Walleij wrote:\n> Oh we already have that I think, Mika Westerberg and Andy Shevcheno\n> implemented that for anyone using CONFIG_GPIOLIB_IRQCHIP, and\n> this driver does. Timur please check: irq_need_valid_mask, irq_valid_mask\n> usage.\n\nThese patches already use irq_valid_mask! But that doesn't block \ncomplete access to the GPIO.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"N+UY1gxB\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"N+UY1gxB\"; dkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=timur@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxMhh19Xgz9s7F\n\tfor ;\n\tTue, 19 Sep 2017 22:32:34 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1750972AbdISMcd (ORCPT );\n\tTue, 19 Sep 2017 08:32:33 -0400","from smtp.codeaurora.org ([198.145.29.96]:50564 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750823AbdISMcc (ORCPT\n\t); Tue, 19 Sep 2017 08:32:32 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid DA29C60724; Tue, 19 Sep 2017 12:32:31 +0000 (UTC)","from [192.168.0.106] (cpe-72-177-20-249.austin.res.rr.com\n\t[72.177.20.249])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\t(Authenticated sender: timur@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id B6E786031A;\n\tTue, 19 Sep 2017 12:32:28 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1505824351;\n\tbh=tkF3zjXGhizNkYfTZHxxHk3vloXu8XgJEkP3wBzNCJQ=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=N+UY1gxBzlEwwO6iKPssnVeMvctVrW2DZEIurlNvtlEF+EAYtvntijekZYKW2yiva\n\tGS9OPK9YfFgFnBzxlzHrasF5dL9HwpdpM299fq28ONrXynrTj9KNMFsas17kIwz9/V\n\tGTPplEAd+R4a4Vei1QjqxozR/uqheVKooc8kOY7Y=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1505824351;\n\tbh=tkF3zjXGhizNkYfTZHxxHk3vloXu8XgJEkP3wBzNCJQ=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=N+UY1gxBzlEwwO6iKPssnVeMvctVrW2DZEIurlNvtlEF+EAYtvntijekZYKW2yiva\n\tGS9OPK9YfFgFnBzxlzHrasF5dL9HwpdpM299fq28ONrXynrTj9KNMFsas17kIwz9/V\n\tGTPplEAd+R4a4Vei1QjqxozR/uqheVKooc8kOY7Y="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org B6E786031A","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Linus Walleij ,\n\tStephen Boyd ","Cc":"Andy Gross ,\n\tDavid Brown , anjiandi@codeaurora.org,\n\tBjorn Andersson ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\t\"thierry.reding@gmail.com\" ,\n\tMika Westerberg ,\n\tAndy Shevchenko ","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<20170919070422.GI3349@codeaurora.org>\n\t","From":"Timur Tabi ","Message-ID":"<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>","Date":"Tue, 19 Sep 2017 07:32:22 -0500","User-Agent":"Mozilla/5.0 (Macintosh; Intel Mac OS X 10.9; rv:52.0)\n\tGecko/20100101 Thunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1771770,"web_url":"http://patchwork.ozlabs.org/comment/1771770/","msgid":"","list_archive_url":null,"date":"2017-09-20T11:43:38","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Tue, Sep 19, 2017 at 2:32 PM, Timur Tabi wrote:\n> On 9/19/17 3:15 AM, Linus Walleij wrote:\n>>\n>> Oh we already have that I think, Mika Westerberg and Andy Shevcheno\n>> implemented that for anyone using CONFIG_GPIOLIB_IRQCHIP, and\n>> this driver does. Timur please check: irq_need_valid_mask, irq_valid_mask\n>> usage.\n>\n> These patches already use irq_valid_mask! But that doesn't block complete\n> access to the GPIO.\n\nAha sorry for my ignorance :(\n\nDoesn't that mean we need something like irq_valid_mask but rather\ngpio_valid_mask that just block all usage of certain GPIOs?\n\nYours,\nLinus Walleij\n--\nTo unsubscribe from this list: send the line \"unsubscribe linux-gpio\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"HuewZ2RJ\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxyYq1n30z9t2W\n\tfor ;\n\tWed, 20 Sep 2017 21:43:43 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751763AbdITLnl (ORCPT );\n\tWed, 20 Sep 2017 07:43:41 -0400","from mail-it0-f54.google.com ([209.85.214.54]:45931 \"EHLO\n\tmail-it0-f54.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751568AbdITLnk (ORCPT\n\t); Wed, 20 Sep 2017 07:43:40 -0400","by mail-it0-f54.google.com with SMTP id v19so2263587ite.0\n\tfor ;\n\tWed, 20 Sep 2017 04:43:40 -0700 (PDT)","by 10.79.164.78 with HTTP; Wed, 20 Sep 2017 04:43:38 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=sYFV+goDajRAJJaMERLTkkeyulJrYMYr0MXfj/3DddU=;\n\tb=HuewZ2RJuBweW1qAt8MS2s7tjD8AYsXAkxvtJ1s3bS/SK5v5DPNLbJGZXuF9hxIyOk\n\tt6PI8mnHf/yKCumt2dGWbivdzoYIeju7lkxJqZsQ15jWaAgGo8cavinru13DAdtkMO5N\n\ttez3g8nL3rJEYJMzanuWeifzBa8rnCSNpiV1s=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=sYFV+goDajRAJJaMERLTkkeyulJrYMYr0MXfj/3DddU=;\n\tb=CCxZ6isRsaz6xj5T6HHeXmsVwFrGPjagnVL+cfnVldJ8D0ZZZEqGIhldg5bK1ESG+7\n\tCWjGJEOj3iGr0W31YBWz+BGgE28E/alcmglx6pwhUaxOzJL2izVbEKBn+uBItMkTi+Cm\n\tmRKoiKtDOflYExOOH6qhYdYNDSVjgrey+7/lQbzpjjTCkuh/qEezoX2qHGIrtWLlq2p4\n\ttIywt/dqGgkggYO1p51JTBWeN+d3bemavyHGr4l/Q7TPIvuEJ1RqvgXtRRiQFRSNZdmR\n\ttyJIhYx5eE4SwrYDYeyXS4XtslWPqcRUSHabIpw+SaS3IWkkvESL5sVmjLdFC1ObdcGL\n\tZsow==","X-Gm-Message-State":"AHPjjUg6j5LeBu6HXVTS5NWOdos1en7x4UaO/CMW3NejxLssDbzdVBED\n\tjl/fihtosYOSF4gnjlg2EcnuLF1ojbgSsql8axvy0A==","X-Google-Smtp-Source":"AOwi7QCOU1oXRT8FhMu94g34PYmdfiqzLo8GTMzR4X1KU/WEE+dDSo2RDkdtWygVQ21IOtMYL9XoOyMDRMk85LV7khE=","X-Received":"by 10.36.167.5 with SMTP id a5mr2485770itf.69.1505907820088; Wed,\n\t20 Sep 2017 04:43:40 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<20170919070422.GI3349@codeaurora.org>\n\t\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>","From":"Linus Walleij ","Date":"Wed, 20 Sep 2017 13:43:38 +0200","Message-ID":"","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Timur Tabi ","Cc":"Stephen Boyd , Andy Gross ,\n\tDavid Brown , anjiandi@codeaurora.org,\n\tBjorn Andersson ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\t\"thierry.reding@gmail.com\" ,\n\tMika Westerberg ,\n\tAndy Shevchenko ","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1771822,"web_url":"http://patchwork.ozlabs.org/comment/1771822/","msgid":"","list_archive_url":null,"date":"2017-09-20T13:04:19","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 9/20/17 6:43 AM, Linus Walleij wrote:\n> Doesn't that mean we need something like irq_valid_mask but rather\n> gpio_valid_mask that just block all usage of certain GPIOs?\n\nThat raises a lot of questions. In the meantime, my current patches for \n4.14 work fine.\n\nDo we replace irq_valid_mask with gpio_valid_mask? That would break \ndrivers where the GPIO is valid but the interrupt is not. If we keep \nboth, what happens if gpio_valid_mask is false but irq_valid_mask is \ntrue? And then we would need to audit all gpio drivers to see which \nones should be updated for the new infrastructure.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"pOy2TO45\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"pOy2TO45\"; dkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=timur@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xy0Lx0VtFz9s81\n\tfor ;\n\tWed, 20 Sep 2017 23:04:25 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751663AbdITNEX (ORCPT );\n\tWed, 20 Sep 2017 09:04:23 -0400","from smtp.codeaurora.org ([198.145.29.96]:60494 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751529AbdITNEW (ORCPT\n\t); Wed, 20 Sep 2017 09:04:22 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid 7CECB60724; Wed, 20 Sep 2017 13:04:22 +0000 (UTC)","from [192.168.0.106] (cpe-72-177-20-249.austin.res.rr.com\n\t[72.177.20.249])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\t(Authenticated sender: timur@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id 479E560134;\n\tWed, 20 Sep 2017 13:04:20 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1505912662;\n\tbh=obWjEA2HUt9GYEXJizlAz6ca5MOFfpYRF+qZxPdPAEg=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=pOy2TO45VUrzDuvgiobt61o7XHmwhucbmPIijnPhfCYOulUvYUY9JUkoifjFc3pFz\n\tG6y02Mob9HiCy9+nBN28roLwdSJOLSltpikA+AnXcyNPtaqccrxObwElQQafJMxJr7\n\tB94kfA2lbGXqo8BlEv3O4/wwDw1RI65691D2auXs=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1505912662;\n\tbh=obWjEA2HUt9GYEXJizlAz6ca5MOFfpYRF+qZxPdPAEg=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=pOy2TO45VUrzDuvgiobt61o7XHmwhucbmPIijnPhfCYOulUvYUY9JUkoifjFc3pFz\n\tG6y02Mob9HiCy9+nBN28roLwdSJOLSltpikA+AnXcyNPtaqccrxObwElQQafJMxJr7\n\tB94kfA2lbGXqo8BlEv3O4/wwDw1RI65691D2auXs="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org 479E560134","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Linus Walleij ","Cc":"Stephen Boyd , Andy Gross ,\n\tDavid Brown , anjiandi@codeaurora.org,\n\tBjorn Andersson ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\t\"thierry.reding@gmail.com\" ,\n\tMika Westerberg ,\n\tAndy Shevchenko ","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<20170919070422.GI3349@codeaurora.org>\n\t\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t","From":"Timur Tabi ","Message-ID":"","Date":"Wed, 20 Sep 2017 08:04:19 -0500","User-Agent":"Mozilla/5.0 (Macintosh; Intel Mac OS X 10.9; rv:52.0)\n\tGecko/20100101 Thunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1772750,"web_url":"http://patchwork.ozlabs.org/comment/1772750/","msgid":"","list_archive_url":null,"date":"2017-09-21T12:08:33","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Wed, Sep 20, 2017 at 3:04 PM, Timur Tabi wrote:\n> On 9/20/17 6:43 AM, Linus Walleij wrote:\n>>\n>> Doesn't that mean we need something like irq_valid_mask but rather\n>> gpio_valid_mask that just block all usage of certain GPIOs?\n>\n>\n> That raises a lot of questions. In the meantime, my current patches for\n> 4.14 work fine.\n>\n> Do we replace irq_valid_mask with gpio_valid_mask? That would break drivers\n> where the GPIO is valid but the interrupt is not. If we keep both, what\n> happens if gpio_valid_mask is false but irq_valid_mask is true? And then we\n> would need to audit all gpio drivers to see which ones should be updated for\n> the new infrastructure.\n\nI guess gpio_valid_mask would take precedence over irq_valid_mask.\nI.e if the GPIO is not valid then the IRQ is per definition not valid either.\n\nSince it is a new thing, we can simply define a semantic like that\nand document it.\n\nYours,\nLinus Walleij\n--\nTo unsubscribe from this list: send the line \"unsubscribe linux-gpio\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"T9AgnsP+\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyb4503Shz9s7c\n\tfor ;\n\tThu, 21 Sep 2017 22:08:37 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751745AbdIUMIf (ORCPT );\n\tThu, 21 Sep 2017 08:08:35 -0400","from mail-io0-f180.google.com ([209.85.223.180]:56369 \"EHLO\n\tmail-io0-f180.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751738AbdIUMIe (ORCPT\n\t); Thu, 21 Sep 2017 08:08:34 -0400","by mail-io0-f180.google.com with SMTP id m103so10202028iod.13\n\tfor ;\n\tThu, 21 Sep 2017 05:08:34 -0700 (PDT)","by 10.79.164.78 with HTTP; Thu, 21 Sep 2017 05:08:33 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=g/Hz/lkwGehmko7s2xUQIBfOtu/drzDnhWtEw/zfSqE=;\n\tb=T9AgnsP+1BiIop9PoA+x2cZ06yqfzXsxIyP+gH6voCkyKdzf9PFWt1Xc1QnWMiqReA\n\tIwcKBRXrPkOalgIDMRa9DhXqewQGVjeZno1Vu9yCeey+GObao+7TuUDgrOvjhZdO5cSe\n\t5Izrdy/0VFAp+IqamNYddAYu3a1d+6//06E38=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=g/Hz/lkwGehmko7s2xUQIBfOtu/drzDnhWtEw/zfSqE=;\n\tb=Qs7mudwP6UcDvpajaZ9ib/XW9jMXpuKUQqGDsDzo/J6DXPJNeCvI5gRr7W39LB2UDc\n\tmNpUiaMKM62NJslALEiOILbAlDGfpYWEKpAAKfaN57hbeD6j2OmLXM1h7F9uHNy355UN\n\t7yc09tGQtMVIR94eYvOjNb/HvqksArF9OsSmPsU4pdwe++P3/5yHEVFbLE+V6WNFpMSi\n\tflXNZQtCflMh25RXOkSHgWr9w9Zf+Mn031eFsh2QnFb1P/gOmmF7tQcq5J/xxLyK10Ov\n\tyecLrhpmCvEnoQXol5D81qq66E+vZ15iNauwUIRKVX1fKxS/X3yBHmINzgd4+aB0pfeC\n\t9rPg==","X-Gm-Message-State":"AHPjjUiim8Utiz1QjtIksasBFTLMbNZpVn8/E2fEsL221KOi3SNQmHQP\n\tUcJyWfdw6h8HPk2fVqBtRInny0dlkM4U1LErl8q+/w==","X-Google-Smtp-Source":"AOwi7QCkMDqaWStv1mbTWii4dFHaBZSvJP2/qvZ7vUKHKP0vs3TFG8uagEYfppoiTyagsZ0VsKoCY/mZkzyFM+vna0w=","X-Received":"by 10.107.22.65 with SMTP id 62mr2704027iow.269.1505995714398;\n\tThu, 21 Sep 2017 05:08:34 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<20170919070422.GI3349@codeaurora.org>\n\t\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t","From":"Linus Walleij ","Date":"Thu, 21 Sep 2017 14:08:33 +0200","Message-ID":"","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Timur Tabi ","Cc":"Stephen Boyd , Andy Gross ,\n\tDavid Brown , anjiandi@codeaurora.org,\n\tBjorn Andersson ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\t\"thierry.reding@gmail.com\" ,\n\tMika Westerberg ,\n\tAndy Shevchenko ","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1772755,"web_url":"http://patchwork.ozlabs.org/comment/1772755/","msgid":"<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>","list_archive_url":null,"date":"2017-09-21T12:12:29","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 9/21/17 7:08 AM, Linus Walleij wrote:\n> I guess gpio_valid_mask would take precedence over irq_valid_mask.\n> I.e if the GPIO is not valid then the IRQ is per definition not valid either.\n> \n> Since it is a new thing, we can simply define a semantic like that\n> and document it.\n\nSo what about my current patches? I hope you're not asking me to \nrewrite them again.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"HBSoBVsW\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"AkGJBJwK\"; dkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=timur@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyb8j51Xlz9t43\n\tfor ;\n\tThu, 21 Sep 2017 22:12:37 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751617AbdIUMMg (ORCPT );\n\tThu, 21 Sep 2017 08:12:36 -0400","from smtp.codeaurora.org ([198.145.29.96]:55250 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751581AbdIUMMg (ORCPT\n\t); Thu, 21 Sep 2017 08:12:36 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid 8A8FE60B69; Thu, 21 Sep 2017 12:12:35 +0000 (UTC)","from [192.168.0.106] (cpe-72-177-20-249.austin.res.rr.com\n\t[72.177.20.249])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\t(Authenticated sender: timur@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id B88C96087F;\n\tThu, 21 Sep 2017 12:12:33 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1505995955;\n\tbh=8eoNJ34toxNpBJ6Wd9BB9AagNoirVWjPe09JKoHRtIk=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=HBSoBVsWQS6dm6Dep0tYcopB2LA6kUaq9Lta3OSYmdw/nl3mmuVaPdn8/foNA62mh\n\tRtPyEnWtVBTxFRQ9j8NTzZ+xDvrEXVxpkkd/FfEt+TNfdWEiPU5n2JwE0fqBgdmzBa\n\tkvOrnIqb0hqc9saG53Y8DvIxOZrsDPXR31TLIUGc=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1505995954;\n\tbh=8eoNJ34toxNpBJ6Wd9BB9AagNoirVWjPe09JKoHRtIk=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=AkGJBJwKqT/nzTY4AhPAW7SF9hf+00xSVeiCi7bVD0XPCG1Sa2VUySCh5LMCqyo6b\n\t5vWuBuJ4jNImUBDOx/NKXuCFrdFiDfevRU5QFC6R1wgijI+YcDryFrX2RexPoy0HnO\n\tJI3Rc1DQYlRe5JY92FPMLbddD+v1+s1EK501Ze8Y="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org B88C96087F","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Linus Walleij ","Cc":"Stephen Boyd , Andy Gross ,\n\tDavid Brown , anjiandi@codeaurora.org,\n\tBjorn Andersson ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\t\"thierry.reding@gmail.com\" ,\n\tMika Westerberg ,\n\tAndy Shevchenko ","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<20170919070422.GI3349@codeaurora.org>\n\t\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t\n\t","From":"Timur Tabi ","Message-ID":"<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>","Date":"Thu, 21 Sep 2017 07:12:29 -0500","User-Agent":"Mozilla/5.0 (Macintosh; Intel Mac OS X 10.9; rv:52.0)\n\tGecko/20100101 Thunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1773592,"web_url":"http://patchwork.ozlabs.org/comment/1773592/","msgid":"","list_archive_url":null,"date":"2017-09-22T13:29:53","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Thu, Sep 21, 2017 at 2:12 PM, Timur Tabi wrote:\n> On 9/21/17 7:08 AM, Linus Walleij wrote:\n>>\n>> I guess gpio_valid_mask would take precedence over irq_valid_mask.\n>> I.e if the GPIO is not valid then the IRQ is per definition not valid\n>> either.\n>>\n>> Since it is a new thing, we can simply define a semantic like that\n>> and document it.\n>\n> So what about my current patches?\n\nI am waiting for the maintainer, Bjorn Andersson, to provide review.\n\n> I hope you're not asking me to rewrite\n> them again.\n\nI don't understand your remark. If you are impatient, such is life.\n\nWhat is your response to Stephen's comment:\n\n> [Stephen Boyd]\n> Perhaps we can add another hook for our purposes here that\n> tells gpiolib that the gpio is not usable and to skip it. The\n> semantics would be clear, it's just about probing availability of\n> this pin as a gpio and doesn't mux any pins.\n\nI think this kind of related to my response (after I realized it\nwas not just about IRQs):\n\n> Doesn't that mean we need something like irq_valid_mask but rather\n> gpio_valid_mask that just block all usage of certain GPIOs?\n\nYours,\nLinus Walleij\n--\nTo unsubscribe from this list: send the line \"unsubscribe linux-gpio\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"EbZrXYqF\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xzDqZ5kL4z9s06\n\tfor ;\n\tFri, 22 Sep 2017 23:30:02 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751875AbdIVNaB (ORCPT );\n\tFri, 22 Sep 2017 09:30:01 -0400","from mail-io0-f182.google.com ([209.85.223.182]:43287 \"EHLO\n\tmail-io0-f182.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751877AbdIVNaA (ORCPT\n\t); Fri, 22 Sep 2017 09:30:00 -0400","by mail-io0-f182.google.com with SMTP id k101so3045882iod.0\n\tfor ;\n\tFri, 22 Sep 2017 06:30:00 -0700 (PDT)","by 10.79.164.78 with HTTP; Fri, 22 Sep 2017 06:29:53 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=m5upsB7BuF6T+vaUI7Ov4wQ6DYU9TQnnnaSx7qfH5PA=;\n\tb=EbZrXYqFU96ZNhZIwrEKjX73ONkR1RvRg3Gd8f3m6jATj9t//odAWB1KOAkvz4GDVt\n\tWKQ2b1efDRvaj/tzoXx7DIQ2fqb5itQ3r3T44VFMNyGXv7vb7z9hvLCJkYJ35D7aHBfC\n\tuS+QtT1c3G0Bjz0SuHrEzxj9J1JQv4OrroVM8=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=m5upsB7BuF6T+vaUI7Ov4wQ6DYU9TQnnnaSx7qfH5PA=;\n\tb=scl4Vv4sYYyo8FOsc6m/29Afv0Nk4glEZzyRYufOWv8rz5kMuoZWXiIIjUUyoAAQjk\n\tX2nYr/PfO20D/yDyHwmUqB2b5aQMjYaIv+GM2UsHsE5CHsXP8pwKoDiFNQvojmKI0lrO\n\ty1MZJFB9GrhNusY452vkg0nD7jb3SZY7Zxm7t5VBDNUvGCO05NmzHV/0HpqK4Q0L7pSS\n\tOBtztmr3WTJBBuRW0nMJ/mJBKIfg27XOQOp/tAltSOo9NLdpJLi+qVNhauQ5z5/9F/pR\n\tJA95FHj6vYG0QPn9CXs6tJenVNmTPr1gHJe04s3hayw0pycDdc6/uOfR9/dKwth5O6wM\n\t37Zg==","X-Gm-Message-State":"AHPjjUgIgvWl0UKjt0SN6yTO6DjuVk8hLiqidF84JVGzwEmgBG4zxMO+\n\t++ZIgZcPC8HACNvYwctZyuzg3n+iDWCJUx3kLjG8kg==","X-Google-Smtp-Source":"AOwi7QDTvGaC7pr0fKHxZXyThJqK/J7Aam+o9RVU3L7s1u3OrSZtnY1BaXptxp0hB1cdXmxiUPFJ9gpJiF/IKk7JKNA=","X-Received":"by 10.107.22.65 with SMTP id 62mr8044797iow.269.1506086994027;\n\tFri, 22 Sep 2017 06:29:54 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<20170919070422.GI3349@codeaurora.org>\n\t\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t\n\t\n\t<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>","From":"Linus Walleij ","Date":"Fri, 22 Sep 2017 15:29:53 +0200","Message-ID":"","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Timur Tabi ","Cc":"Stephen Boyd , Andy Gross ,\n\tDavid Brown , anjiandi@codeaurora.org,\n\tBjorn Andersson ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\t\"thierry.reding@gmail.com\" ,\n\tMika Westerberg ,\n\tAndy Shevchenko ","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1773598,"web_url":"http://patchwork.ozlabs.org/comment/1773598/","msgid":"<255ad0dc-2d16-ae7f-0b45-500e23cff1a4@codeaurora.org>","list_archive_url":null,"date":"2017-09-22T13:37:07","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 09/22/2017 08:29 AM, Linus Walleij wrote:\n> \n> What is your response to Stephen's comment:\n> \n>> [Stephen Boyd]\n>> Perhaps we can add another hook for our purposes here that\n>> tells gpiolib that the gpio is not usable and to skip it. The\n>> semantics would be clear, it's just about probing availability of\n>> this pin as a gpio and doesn't mux any pins.\n\n> I think this kind of related to my response (after I realized it\n> was not just about IRQs):\n\nWe already have 95% of this. We can already specify individual pin \nranges, and the vast majority of the code recognizes the ranges. There \nis only one small loophole, and that's in gpiochip_add_data(). The \nfor-loop iterates over all GPIOs:\n\n\tfor (i = 0; i < chip->ngpio; i++) {\n\t\tstruct gpio_desc *desc = &gdev->descs[i];\n\n\t\tdesc->gdev = gdev;\n\t\t/*\n\t\t * REVISIT: most hardware initializes GPIOs as inputs\n\t\t * (often with pullups enabled) so power usage is\n\t\t * minimized. Linux code should set the gpio direction\n\t\t * first thing; but until it does, and in case\n\t\t * chip->get_direction is not set, we may expose the\n\t\t * wrong direction in sysfs.\n\t\t */\n\nI believe the real problem is that this for-loop should be moved from \ngpiochip_add_data() into some other function that is called *after* the \npin ranges are defined. We can put it in gpiochip_add_pin_range(), maybe.\n\nMy patch covers the loophole by adding a check inside get_direction(). \nIf we fix gpiochip_add_data(), I can remove that patch.\n\nHowever, I think that change is risky and will require a lot of testing \nand review.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"XVTa51tx\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"mloW0/6r\"; dkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=timur@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xzDzs09zDz9s06\n\tfor ;\n\tFri, 22 Sep 2017 23:37:13 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751928AbdIVNhL (ORCPT );\n\tFri, 22 Sep 2017 09:37:11 -0400","from smtp.codeaurora.org ([198.145.29.96]:50242 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751877AbdIVNhK (ORCPT\n\t); Fri, 22 Sep 2017 09:37:10 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid 642EA6070F; Fri, 22 Sep 2017 13:37:10 +0000 (UTC)","from [10.222.143.167] (i-global254.qualcomm.com [199.106.103.254])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\t(Authenticated sender: timur@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id BA9D160117;\n\tFri, 22 Sep 2017 13:37:08 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1506087430;\n\tbh=lTFTBYjiGseIbtZpBN18EQMYHNIKeOhe7J4kOCPkL3w=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=XVTa51tx7P5hIlKk0BucwiMK08pUZKTze0Plazz/Ixr8FrW+UZ3ePhuTUH7/nfXi9\n\t1PaKFzaqkVE0KCDmTbr1+DTXqINWF0yQtNl7UDqcTgYIsVAjG5fUcqDWoUlG9dq6T3\n\tVDwNRFmsMyzAMhJ7HoL7x1oARgwhrhgpG56JSxIo=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1506087429;\n\tbh=lTFTBYjiGseIbtZpBN18EQMYHNIKeOhe7J4kOCPkL3w=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=mloW0/6ryHspPstvye3PZCC47fND73GvVHLC56GDITNebiLbfq1HUEQTcz53c4haA\n\tPMhb6Bq0wdwFX0sKIzjStQy+3oCAYV8/g3nQr88OXfl4NaU41jD5Zyb+Mw7VTvIZRb\n\tWN3tuCoRXtWzLp5oHHGoheW+g6HY4F0K3BbYB2Fw="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org BA9D160117","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Linus Walleij ","Cc":"Stephen Boyd , Andy Gross ,\n\tDavid Brown , anjiandi@codeaurora.org,\n\tBjorn Andersson ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\t\"thierry.reding@gmail.com\" ,\n\tMika Westerberg ,\n\tAndy Shevchenko ","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<20170919070422.GI3349@codeaurora.org>\n\t\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t\n\t\n\t<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>\n\t","From":"Timur Tabi ","Message-ID":"<255ad0dc-2d16-ae7f-0b45-500e23cff1a4@codeaurora.org>","Date":"Fri, 22 Sep 2017 08:37:07 -0500","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1778428,"web_url":"http://patchwork.ozlabs.org/comment/1778428/","msgid":"<0ede14eb-a9fc-ab90-4e18-c6c955da2601@codeaurora.org>","list_archive_url":null,"date":"2017-10-02T16:02:50","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 09/22/2017 08:29 AM, Linus Walleij wrote:\n> I am waiting for the maintainer, Bjorn Andersson, to provide review.\n\nBjorn,\n\nWould you please take a moment to review these patches? I'm guessing \nit's too late for 4.14, so I would like these merged into 4.15. But \nwithout your review, very little progress is being made.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"pBeSI2EM\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"EGlepD7i\"; dkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=timur@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y5RlP0xmfz9t5s\n\tfor ;\n\tTue, 3 Oct 2017 03:02:57 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751174AbdJBQCz (ORCPT );\n\tMon, 2 Oct 2017 12:02:55 -0400","from smtp.codeaurora.org ([198.145.29.96]:50358 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751061AbdJBQCy (ORCPT\n\t); Mon, 2 Oct 2017 12:02:54 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid 5D4B460724; Mon, 2 Oct 2017 16:02:54 +0000 (UTC)","from [10.222.143.167] (i-global254.qualcomm.com [199.106.103.254])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\t(Authenticated sender: timur@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id DBF3D60715;\n\tMon, 2 Oct 2017 16:02:52 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1506960174;\n\tbh=wQNiYuoSW++942fGesjdX5fI38rYpOJpcGG8H9L1XIc=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=pBeSI2EMcMfhlfwKlAsGE0iVnW4hwA6adyW/4y0TQqTqlRi3sHxdck+rQUgYaauQA\n\tsXPOmxgrLspS0hWk/MTdLG6K8V+rHeVg69O8OKWREfvl4tCjU+TFUF4UsPjX7ZmLqP\n\tXMhBSf04dGYNLeQDfJme8W/iKskPgRjKTfCptdgU=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1506960173;\n\tbh=wQNiYuoSW++942fGesjdX5fI38rYpOJpcGG8H9L1XIc=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=EGlepD7i9YNwQ8tn337eOOKqX/Wh2BO7a5j8bxoniFfwWBmV8MIdDk7EcQOkoDurV\n\tfg/VwRf9QP1z8N9yzpbw1EAp9MWVvE4TIpeCimS/QK/Drjvf/6htCZ23xtYiGtrLfx\n\tfwnu7YdZTTMX4lIJO4yn8WixgLRdiQ3wIaCiV5+o="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org DBF3D60715","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Bjorn Andersson ","Cc":"Linus Walleij ,\n\tStephen Boyd , Andy Gross ,\n\tDavid Brown , anjiandi@codeaurora.org,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\t\"thierry.reding@gmail.com\" ,\n\tMika Westerberg ,\n\tAndy Shevchenko ","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<20170919070422.GI3349@codeaurora.org>\n\t\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t\n\t\n\t<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>\n\t","From":"Timur Tabi ","Message-ID":"<0ede14eb-a9fc-ab90-4e18-c6c955da2601@codeaurora.org>","Date":"Mon, 2 Oct 2017 11:02:50 -0500","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1779291,"web_url":"http://patchwork.ozlabs.org/comment/1779291/","msgid":"<20171003220311.GU457@codeaurora.org>","list_archive_url":null,"date":"2017-10-03T22:03:11","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":6071,"url":"http://patchwork.ozlabs.org/api/people/6071/","name":"Stephen Boyd","email":"sboyd@codeaurora.org"},"content":"On 09/22, Timur Tabi wrote:\n> On 09/22/2017 08:29 AM, Linus Walleij wrote:\n> >\n> >What is your response to Stephen's comment:\n> >\n> >>[Stephen Boyd]\n> >>Perhaps we can add another hook for our purposes here that\n> >>tells gpiolib that the gpio is not usable and to skip it. The\n> >>semantics would be clear, it's just about probing availability of\n> >>this pin as a gpio and doesn't mux any pins.\n> \n> >I think this kind of related to my response (after I realized it\n> >was not just about IRQs):\n> \n> We already have 95% of this. We can already specify individual pin\n> ranges, and the vast majority of the code recognizes the ranges.\n> There is only one small loophole, and that's in gpiochip_add_data().\n> The for-loop iterates over all GPIOs:\n> \n> \tfor (i = 0; i < chip->ngpio; i++) {\n> \t\tstruct gpio_desc *desc = &gdev->descs[i];\n> \n> \t\tdesc->gdev = gdev;\n> \t\t/*\n> \t\t * REVISIT: most hardware initializes GPIOs as inputs\n> \t\t * (often with pullups enabled) so power usage is\n> \t\t * minimized. Linux code should set the gpio direction\n> \t\t * first thing; but until it does, and in case\n> \t\t * chip->get_direction is not set, we may expose the\n> \t\t * wrong direction in sysfs.\n> \t\t */\n> \n> I believe the real problem is that this for-loop should be moved\n> from gpiochip_add_data() into some other function that is called\n> *after* the pin ranges are defined. We can put it in\n> gpiochip_add_pin_range(), maybe.\n> \n> My patch covers the loophole by adding a check inside\n> get_direction(). If we fix gpiochip_add_data(), I can remove that\n> patch.\n> \n> However, I think that change is risky and will require a lot of\n> testing and review.\n> \n\nI've run into this now on our mobile SoCs after I pull in commit\n8e51533780ba (\"pinctrl: qcom: add get_direction function\").\nBefore that commit we never read each pin of the device. On our\nmobile SoCs we have devicetree and it feels like having that\ndescribe which pins are available and not available is\nhalf-duplicating information we would already have via consumers\nindicating which pins they care about. I don't see any value\nbeyond system wide debug in figuring out the default pin\nconfiguration of a pin that doesn't have a consumer in Linux.\n\nCould we remove the pin direction finding part here in\ngpiochip_add_pin_range() and lazily resolve the pin direction\nwhen a pin is requested? We would need a similar check in the msm\nspecific debugfs code where we skip pins that aren't requested.\nThis is basically a revert of commit 72d320006177 (\"gpio: set up\ninitial state from .get_direction()\").\n\nACPI can still describe only the pin ranges that they care about\nexposing, but from the devicetree side it's been working well\nenough to not touch pins that aren't used by anything in Linux.\n\n---8<----\ndiff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c\nindex cd003b74512f..673028823bc5 100644\n--- a/drivers/gpio/gpiolib.c\n+++ b/drivers/gpio/gpiolib.c\n@@ -1210,16 +1210,7 @@ int gpiochip_add_data(struct gpio_chip *chip, void *data)\n \t\t * wrong direction in sysfs.\n \t\t */\n \n-\t\tif (chip->get_direction) {\n-\t\t\t/*\n-\t\t\t * If we have .get_direction, set up the initial\n-\t\t\t * direction flag from the hardware.\n-\t\t\t */\n-\t\t\tint dir = chip->get_direction(chip, i);\n-\n-\t\t\tif (!dir)\n-\t\t\t\tset_bit(FLAG_IS_OUT, &desc->flags);\n-\t\t} else if (!chip->direction_input) {\n+\t\tif (!chip->direction_input) {\n \t\t\t/*\n \t\t\t * If the chip lacks the .direction_input callback\n \t\t\t * we logically assume all lines are outputs.\ndiff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c\nindex 273badd92561..4a0aeceb42f1 100644\n--- a/drivers/pinctrl/qcom/pinctrl-msm.c\n+++ b/drivers/pinctrl/qcom/pinctrl-msm.c\n@@ -24,7 +24,7 @@\n #include \n #include \n #include \n-#include \n+#include \n #include \n #include \n #include \n@@ -494,6 +494,12 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,\n \t};\n \n \tg = &pctrl->soc->groups[offset];\n+\n+\tif (!gpiochip_is_requested(chip, gpio)) {\n+\t\tseq_printf(s, \" %-8s:\", g->name);\n+\t\treturn;\n+\t}\n+\n \tctl_reg = readl(pctrl->regs + g->ctl_reg);\n \n \tis_out = !!(ctl_reg & BIT(g->oe_bit));","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"MXfWsKaC\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"MXfWsKaC\"; dkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=sboyd@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y6Chg18qdz9s81\n\tfor ;\n\tWed, 4 Oct 2017 09:03:15 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751158AbdJCWDO (ORCPT );\n\tTue, 3 Oct 2017 18:03:14 -0400","from smtp.codeaurora.org ([198.145.29.96]:35958 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750841AbdJCWDN (ORCPT\n\t); Tue, 3 Oct 2017 18:03:13 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid D9CD360B72; Tue, 3 Oct 2017 22:03:12 +0000 (UTC)","from localhost (i-global254.qualcomm.com [199.106.103.254])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\t(Authenticated sender: sboyd@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id E778460723;\n\tTue, 3 Oct 2017 22:03:11 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507068192;\n\tbh=pmoY1eRyPfs16xpUIqWIPf2tXNrq5bPY+4fobKMKAvE=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=MXfWsKaC6jB78Pg5Whp8yKv468Vg086FRV6vWi74iQLt/ZyYM04a17v4YWbklowWz\n\tyfhN2ot36IHxTz1p92Lxqyqfpo1yvMHlfvu2flGf+dnFMwz09QTSjkAGx8EHZMKcH6\n\tJPlV6cNmZKl3OEedqlus0tnVvX7UsEq+YBrFn+jE=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507068192;\n\tbh=pmoY1eRyPfs16xpUIqWIPf2tXNrq5bPY+4fobKMKAvE=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=MXfWsKaC6jB78Pg5Whp8yKv468Vg086FRV6vWi74iQLt/ZyYM04a17v4YWbklowWz\n\tyfhN2ot36IHxTz1p92Lxqyqfpo1yvMHlfvu2flGf+dnFMwz09QTSjkAGx8EHZMKcH6\n\tJPlV6cNmZKl3OEedqlus0tnVvX7UsEq+YBrFn+jE="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org E778460723","Date":"Tue, 3 Oct 2017 15:03:11 -0700","From":"Stephen Boyd ","To":"Timur Tabi ","Cc":"Linus Walleij ,\n\tAndy Gross ,\n\tDavid Brown , anjiandi@codeaurora.org,\n\tBjorn Andersson ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\t\"thierry.reding@gmail.com\" ,\n\tMika Westerberg ,\n\tAndy Shevchenko ","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","Message-ID":"<20171003220311.GU457@codeaurora.org>","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<20170919070422.GI3349@codeaurora.org>\n\t\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t\n\t\n\t<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>\n\t\n\t<255ad0dc-2d16-ae7f-0b45-500e23cff1a4@codeaurora.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<255ad0dc-2d16-ae7f-0b45-500e23cff1a4@codeaurora.org>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1779296,"web_url":"http://patchwork.ozlabs.org/comment/1779296/","msgid":"<40a0ab68-dc3a-10e2-f78e-9a386b4a72bd@codeaurora.org>","list_archive_url":null,"date":"2017-10-03T22:12:08","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 10/03/2017 05:03 PM, Stephen Boyd wrote:\n> I've run into this now on our mobile SoCs after I pull in commit\n> 8e51533780ba (\"pinctrl: qcom: add get_direction function\").\n> Before that commit we never read each pin of the device. On our\n> mobile SoCs we have devicetree and it feels like having that\n> describe which pins are available and not available is\n> half-duplicating information we would already have via consumers\n> indicating which pins they care about. I don't see any value\n> beyond system wide debug in figuring out the default pin\n> configuration of a pin that doesn't have a consumer in Linux.\n\nAt the time I wrote that patch, the ACPI tables exposed all of the \nGPIOs, even the ones it didn't care about. The new ACPI tables list \nonly specific GPIOs, and so we no longer need to blindly read the \ndirection of all GPIOs.\n\n> Could we remove the pin direction finding part here in\n> gpiochip_add_pin_range() and lazily resolve the pin direction\n> when a pin is requested?\n\nThat makes a lot more sense.\n\n> We would need a similar check in the msm\n> specific debugfs code where we skip pins that aren't requested.\n\nI have that in patch #1.\n\n> This is basically a revert of commit 72d320006177 (\"gpio: set up\n> initial state from .get_direction()\").\n\nI would be in favor of either reverting that patch, or moving the code \ninto gpiochip_add_pin_range().\n\n> ACPI can still describe only the pin ranges that they care about\n> exposing, but from the devicetree side it's been working well\n> enough to not touch pins that aren't used by anything in Linux.\n\nI do hate having to hack up the driver to support crappy ACPI \ndefinitions, but I'm stuck between a rock and a hard place.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"lNX5T+sg\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"Y8ggvrNu\"; dkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=timur@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y6Cv33xD1z9s81\n\tfor ;\n\tWed, 4 Oct 2017 09:12:14 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751184AbdJCWMN (ORCPT );\n\tTue, 3 Oct 2017 18:12:13 -0400","from smtp.codeaurora.org ([198.145.29.96]:39204 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751115AbdJCWMM (ORCPT\n\t); Tue, 3 Oct 2017 18:12:12 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid 82D1360B68; Tue, 3 Oct 2017 22:12:11 +0000 (UTC)","from [10.222.143.167] (i-global254.qualcomm.com [199.106.103.254])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\t(Authenticated sender: timur@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id DD52E60723;\n\tTue, 3 Oct 2017 22:12:09 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507068731;\n\tbh=JknIM+3foHJ3/YqOE9WLexyCC9zgU+JO26zswTdbQiE=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=lNX5T+sgCRJLqwS+k+1db/Jgmg+V3uzWFEaAUh1RoXYHVAV/RwFQ2MUXpL+COU/L2\n\tq3tL9z/Ml+pXGRDo5RhBr3xWEXB+7eWENCJLbIrevY7ZkJG7p9B72IJ9SZbZdV9DlP\n\tVN/eErL11VGk4XcmAyae/9BKLS6N0+Xg8OqT2pYU=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507068730;\n\tbh=JknIM+3foHJ3/YqOE9WLexyCC9zgU+JO26zswTdbQiE=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=Y8ggvrNu6EMGoIa5q4ncHsLEKGyJszBLfbDhLun79A2QzHgzs+VXplrtEucUVmE/+\n\tw7tDcFJdQEUjwfTD/gFp9tJvlxncABwoq2Eo/z35mDVOduBBPTjY5Ts6bxTKkjebcv\n\t+jVMVMgPzyPwMRHazYeXgEdujR/VjpxMGID52weg="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org DD52E60723","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Stephen Boyd ","Cc":"Linus Walleij ,\n\tAndy Gross ,\n\tDavid Brown , anjiandi@codeaurora.org,\n\tBjorn Andersson ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\t\"thierry.reding@gmail.com\" ,\n\tMika Westerberg ,\n\tAndy Shevchenko ","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<20170919070422.GI3349@codeaurora.org>\n\t\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t\n\t\n\t<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>\n\t\n\t<255ad0dc-2d16-ae7f-0b45-500e23cff1a4@codeaurora.org>\n\t<20171003220311.GU457@codeaurora.org>","From":"Timur Tabi ","Message-ID":"<40a0ab68-dc3a-10e2-f78e-9a386b4a72bd@codeaurora.org>","Date":"Tue, 3 Oct 2017 17:12:08 -0500","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20171003220311.GU457@codeaurora.org>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1780138,"web_url":"http://patchwork.ozlabs.org/comment/1780138/","msgid":"<20171004215023.GA457@codeaurora.org>","list_archive_url":null,"date":"2017-10-04T21:50:23","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":6071,"url":"http://patchwork.ozlabs.org/api/people/6071/","name":"Stephen Boyd","email":"sboyd@codeaurora.org"},"content":"On 10/03, Timur Tabi wrote:\n> On 10/03/2017 05:03 PM, Stephen Boyd wrote:\n> >I've run into this now on our mobile SoCs after I pull in commit\n> >8e51533780ba (\"pinctrl: qcom: add get_direction function\").\n> >Before that commit we never read each pin of the device. On our\n> >mobile SoCs we have devicetree and it feels like having that\n> >describe which pins are available and not available is\n> >half-duplicating information we would already have via consumers\n> >indicating which pins they care about. I don't see any value\n> >beyond system wide debug in figuring out the default pin\n> >configuration of a pin that doesn't have a consumer in Linux.\n> \n> At the time I wrote that patch, the ACPI tables exposed all of the\n> GPIOs, even the ones it didn't care about. The new ACPI tables list\n> only specific GPIOs, and so we no longer need to blindly read the\n> direction of all GPIOs.\n> \n\nDo you avoid this problem on new ACPI tables because only pins\nthat are able to be read are exposed?\n\n> \n> >This is basically a revert of commit 72d320006177 (\"gpio: set up\n> >initial state from .get_direction()\").\n> \n> I would be in favor of either reverting that patch, or moving the\n> code into gpiochip_add_pin_range().\n\nIf it's in gpiochip_add_pin_range() would we still read the\nhardware when creating the pin ranges? I don't want to have to\ndescribe pin ranges of \"valid\" pins that won't cause the system\nto blow up if we touch them, because those pins are never used by\nLinux so reading them is not useful.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"HJFIcyHm\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"kKp1ruNE\"; dkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=sboyd@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y6qMT04ryz9t3R\n\tfor ;\n\tThu, 5 Oct 2017 08:50:29 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751195AbdJDVu1 (ORCPT );\n\tWed, 4 Oct 2017 17:50:27 -0400","from smtp.codeaurora.org ([198.145.29.96]:41096 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750951AbdJDVuZ (ORCPT\n\t); Wed, 4 Oct 2017 17:50:25 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid 28BF3609FE; Wed, 4 Oct 2017 21:50:25 +0000 (UTC)","from localhost (i-global254.qualcomm.com [199.106.103.254])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\t(Authenticated sender: sboyd@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id 4F29F6071B;\n\tWed, 4 Oct 2017 21:50:24 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507153825;\n\tbh=MnQB+DrXaZifypzRvP/m30zSLMFKhfakis1rM6rf5pE=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=HJFIcyHm0vnII+8fEhf6db5E1kMH1FivH5Kvp3XIGOxyqxAbiW6i1Qe5OpuLXgMPZ\n\ts49JQ8fiSa86l4vh8H3MOe5JHMJfY5JqpvtKc44DcNpyMruomdHiLG9j0VfM5sm9nZ\n\tJTtQWSUtYWyanbWo1u4/gAuuis6UI5lMQ5iFAT6o=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507153824;\n\tbh=MnQB+DrXaZifypzRvP/m30zSLMFKhfakis1rM6rf5pE=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=kKp1ruNEmWF6cGsRHUbVeExrVcwXSY92Kf7DBC35iQ6ROg1wTQGJlyZgxo+XHkBCm\n\tVyxBtPeFs1MR250GtZ9gfPppQmEj2mHgPUZhS20s01PTTLSrnVrU30g3GtEUGIvV+W\n\tm0FEfIFRRce6MIchmP0FQS7fiKRp066mLF2TvC38="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4F29F6071B","Date":"Wed, 4 Oct 2017 14:50:23 -0700","From":"Stephen Boyd ","To":"Timur Tabi ","Cc":"Linus Walleij ,\n\tAndy Gross ,\n\tDavid Brown , anjiandi@codeaurora.org,\n\tBjorn Andersson ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\t\"thierry.reding@gmail.com\" ,\n\tMika Westerberg ,\n\tAndy Shevchenko ","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","Message-ID":"<20171004215023.GA457@codeaurora.org>","References":"\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t\n\t\n\t<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>\n\t\n\t<255ad0dc-2d16-ae7f-0b45-500e23cff1a4@codeaurora.org>\n\t<20171003220311.GU457@codeaurora.org>\n\t<40a0ab68-dc3a-10e2-f78e-9a386b4a72bd@codeaurora.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<40a0ab68-dc3a-10e2-f78e-9a386b4a72bd@codeaurora.org>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1780156,"web_url":"http://patchwork.ozlabs.org/comment/1780156/","msgid":"","list_archive_url":null,"date":"2017-10-04T22:41:27","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 10/04/2017 04:50 PM, Stephen Boyd wrote:\n\n>> At the time I wrote that patch, the ACPI tables exposed all of the\n>> GPIOs, even the ones it didn't care about. The new ACPI tables list\n>> only specific GPIOs, and so we no longer need to blindly read the\n>> direction of all GPIOs.\n>>\n> \n> Do you avoid this problem on new ACPI tables because only pins\n> that are able to be read are exposed?\n\nYes. A recent firmware update enabled the \"XPU\" block which is being \nprogrammed with a select subset of individual GPIOs. On our silicon, \neach TLMM GPIO is in a separate 64k page, and so the XPU can block any \nindividual GPIO. Any attempt to touch those registers causes an XPU \nviolation which takes the whole system down.\n\n>>> This is basically a revert of commit 72d320006177 (\"gpio: set up\n>>> initial state from .get_direction()\").\n>>\n>> I would be in favor of either reverting that patch, or moving the\n>> code into gpiochip_add_pin_range().\n> \n> If it's in gpiochip_add_pin_range() would we still read the\n> hardware when creating the pin ranges?\n\nI presume so. The idea is that pinctrl-qdf2xxx/pinctrl-msm only submit \npin ranges that are present in the ACPI tables.\n\n > I don't want to have to> describe pin ranges of \"valid\" pins that \nwon't cause the system\n> to blow up if we touch them, because those pins are never used by\n> Linux so reading them is not useful.\n\nWell, that's exactly what I'm trying to do with current patch set :-) \nIt seems the most logical approach to me. I don't understand the \ndislike for it. What else are pin ranges for, other than to specify \nranges of pins that can be accessed?\n\nAnother alternative was to enumerate all of the GPIOs starting from 0. \nSo the first GPIO in ACPI would be gpio0, regardless of what gpio number \nit actually was. E.g. GPIO 37 would appear as gpio0, GPIO 38 would \nappear as gpio1, and so on. That also worked, but it meant that \ncustomers would need to figure out which GPIO that \"gpio0\" actually \npointed to. That was not acceptable, so I dropped it.\n\nI'm at a loss on how else to do it. I think a gpio_chip.available \ncallback is far less elegant than define pin ranges. There is no chance \nthat unavailable GPIOs can be accessed because the physical addresses \nare not in the msm_pingroup array. That is, groups[0].ctrl_reg == 0, \nnot 0xFF02010000.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"J+158nCz\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"NxRDbCWa\"; dkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=timur@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y6rVP2rGjz9t2Z\n\tfor ;\n\tThu, 5 Oct 2017 09:41:33 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751201AbdJDWlc (ORCPT );\n\tWed, 4 Oct 2017 18:41:32 -0400","from smtp.codeaurora.org ([198.145.29.96]:38500 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751194AbdJDWla (ORCPT\n\t); Wed, 4 Oct 2017 18:41:30 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid 48E1460A10; Wed, 4 Oct 2017 22:41:30 +0000 (UTC)","from [10.222.143.167] (i-global254.qualcomm.com [199.106.103.254])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\t(Authenticated sender: timur@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id 7E7AB6099A;\n\tWed, 4 Oct 2017 22:41:28 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507156890;\n\tbh=4KtDFk5RC3rLhGm2ead1NnTMDLSxHeQ6pLLZtdHsICk=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=J+158nCzjrWKe3jbBT0XMiFEUEfHbQIzoR+rki3gFfhZaYuM+RVHzduD/4yjsSysZ\n\tD1goDTlO8lVWBL9ldaYZBoKxq1Fipka5d8VoTaxWdBC52Z+q6Yso4OQOxNit9uOX2/\n\t4AUxT+U5wg/JHEG20DalAck9yu8ObfFL+a+BSOBs=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507156889;\n\tbh=4KtDFk5RC3rLhGm2ead1NnTMDLSxHeQ6pLLZtdHsICk=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=NxRDbCWaWt+arSbaXt73zwljKsRW6ecSHqnoBKwjH6jE51dTBVZi1cHn7zarRo1p6\n\t0HBKdIjLIgZ+AWLmFZj7DwA7SgV4VZcRSo//G4+A8431YqFJAIGfzKqEfypmoJQl/I\n\tdjtPQFgaq7pcp6Ht8yhiQbeYjB57Ahj/FG64tARk="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7E7AB6099A","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Stephen Boyd ","Cc":"Linus Walleij ,\n\tAndy Gross ,\n\tDavid Brown , anjiandi@codeaurora.org,\n\tBjorn Andersson ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\t\"thierry.reding@gmail.com\" ,\n\tMika Westerberg ,\n\tAndy Shevchenko ","References":"\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t\n\t\n\t<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>\n\t\n\t<255ad0dc-2d16-ae7f-0b45-500e23cff1a4@codeaurora.org>\n\t<20171003220311.GU457@codeaurora.org>\n\t<40a0ab68-dc3a-10e2-f78e-9a386b4a72bd@codeaurora.org>\n\t<20171004215023.GA457@codeaurora.org>","From":"Timur Tabi ","Message-ID":"","Date":"Wed, 4 Oct 2017 17:41:27 -0500","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20171004215023.GA457@codeaurora.org>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1781034,"web_url":"http://patchwork.ozlabs.org/comment/1781034/","msgid":"<20171005213035.GF457@codeaurora.org>","list_archive_url":null,"date":"2017-10-05T21:30:35","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":6071,"url":"http://patchwork.ozlabs.org/api/people/6071/","name":"Stephen Boyd","email":"sboyd@codeaurora.org"},"content":"On 10/04, Timur Tabi wrote:\n> On 10/04/2017 04:50 PM, Stephen Boyd wrote:\n> \n> Yes. A recent firmware update enabled the \"XPU\" block which is\n> being programmed with a select subset of individual GPIOs. On our\n> silicon, each TLMM GPIO is in a separate 64k page, and so the XPU\n> can block any individual GPIO. Any attempt to touch those registers\n> causes an XPU violation which takes the whole system down.\n\nYes it's the same sort of design with the hardware I have too.\n\n> \n> >\n> >If it's in gpiochip_add_pin_range() would we still read the\n> >hardware when creating the pin ranges?\n> \n> I presume so. The idea is that pinctrl-qdf2xxx/pinctrl-msm only\n> submit pin ranges that are present in the ACPI tables.\n\nOk.\n\n> \n> > I don't want to have to describe pin ranges of \"valid\" pins that\n> > won't cause the system\n> > to blow up if we touch them, because those pins are never used by\n> > Linux so reading them is not useful.\n> \n> Well, that's exactly what I'm trying to do with current patch set\n> :-) It seems the most logical approach to me. I don't understand\n> the dislike for it. What else are pin ranges for, other than to\n> specify ranges of pins that can be accessed?\n\nI have no idea. To describe non-contiguous pin ranges? Linus?\n\n> \n> Another alternative was to enumerate all of the GPIOs starting from\n> 0. So the first GPIO in ACPI would be gpio0, regardless of what gpio\n> number it actually was. E.g. GPIO 37 would appear as gpio0, GPIO 38\n> would appear as gpio1, and so on. That also worked, but it meant\n> that customers would need to figure out which GPIO that \"gpio0\"\n> actually pointed to. That was not acceptable, so I dropped it.\n\nAgreed.\n\n> \n> I'm at a loss on how else to do it. I think a gpio_chip.available\n> callback is far less elegant than define pin ranges. There is no\n> chance that unavailable GPIOs can be accessed because the physical\n> addresses are not in the msm_pingroup array. That is,\n> groups[0].ctrl_reg == 0, not 0xFF02010000.\n> \n\nYes, thinking more about it I don't want an available callback\neither. It will add burden on DT platforms where we have to\ndescribe per-firmware pin ranges just because gpiolib is reading\nthe direction of gpios we don't use.\n\nInstead, I'd prefer we delay reading the direction until a\nconsumer requests the gpio, this way we don't touch the hardware\nunless a consumer wants to. That seems simpler and doesn't\nrequire anything special from the driver.\n\nDon't get me wrong, I'm willing to describe with DT/ACPI which\npins are available if we have a need for it, but so far I don't\nsee the requirement and I'm a lazy person so I like avoiding more\nwork.\n\nDoes my patch fail on your platform for some reason? I can only\nguess that somewhere we don't request the gpio before using it\nand then you don't see the proper direction.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"PaVOFZKj\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"Svmg3R56\"; dkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=sboyd@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y7Qt80SRMz9t2f\n\tfor ;\n\tFri, 6 Oct 2017 08:30:40 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751486AbdJEVai (ORCPT );\n\tThu, 5 Oct 2017 17:30:38 -0400","from smtp.codeaurora.org ([198.145.29.96]:57798 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751423AbdJEVah (ORCPT\n\t); Thu, 5 Oct 2017 17:30:37 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid 2FD9D60261; Thu, 5 Oct 2017 21:30:37 +0000 (UTC)","from localhost (i-global254.qualcomm.com [199.106.103.254])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\t(Authenticated sender: sboyd@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id 4A47F6020B;\n\tThu, 5 Oct 2017 21:30:36 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507239037;\n\tbh=3RZ7TFu1D0zzzFmhmFRhT5uagV65UY1LUo2p/udtFI4=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=PaVOFZKj4EMcixz5EHXAEM6VjhMNuDB3d/gjtcUR694jwpApyZKT3TXOFypil1uve\n\thfppfwd8x+E8MdHj5L8+BQRs2lq6mahztairW1UAR2RtD78ZNRBAyzdJxWtCvHBHr5\n\tcAYjjCuElse59S4kpOBBQjC0bu2VxD5Re+xkxohg=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507239036;\n\tbh=3RZ7TFu1D0zzzFmhmFRhT5uagV65UY1LUo2p/udtFI4=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=Svmg3R56LB/j1iQLeX1Q9hTZTN3TW0kmGYEwvoX1fjw93QGASA2ZIGLFfEkkiI95V\n\t8sOfc4ukAkpicPiG/8RXhvEzX+5nNep3qz4oOl2cgMDXHZwlwCdn7XW9nWx06IGWTA\n\t+NBUBiWiCNlRy/ynbtg3y9hXRd/zd4Oob9IIvBZQ="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4A47F6020B","Date":"Thu, 5 Oct 2017 14:30:35 -0700","From":"Stephen Boyd ","To":"Timur Tabi ","Cc":"Linus Walleij ,\n\tAndy Gross ,\n\tDavid Brown , anjiandi@codeaurora.org,\n\tBjorn Andersson ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\t\"thierry.reding@gmail.com\" ,\n\tMika Westerberg ,\n\tAndy Shevchenko ","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","Message-ID":"<20171005213035.GF457@codeaurora.org>","References":"\n\t\n\t\n\t<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>\n\t\n\t<255ad0dc-2d16-ae7f-0b45-500e23cff1a4@codeaurora.org>\n\t<20171003220311.GU457@codeaurora.org>\n\t<40a0ab68-dc3a-10e2-f78e-9a386b4a72bd@codeaurora.org>\n\t<20171004215023.GA457@codeaurora.org>\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1784351,"web_url":"http://patchwork.ozlabs.org/comment/1784351/","msgid":"","list_archive_url":null,"date":"2017-10-11T07:51:08","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Wed, Oct 4, 2017 at 12:03 AM, Stephen Boyd wrote:\n\n> Could we remove the pin direction finding part here in\n> gpiochip_add_pin_range() and lazily resolve the pin direction\n> when a pin is requested? We would need a similar check in the msm\n> specific debugfs code where we skip pins that aren't requested.\n> This is basically a revert of commit 72d320006177 (\"gpio: set up\n> initial state from .get_direction()\").\n\nIt seems reasonable for the gpiolib to be able to call this\nfunction immediately after registering the new GPIO chip\nwith its vtable.\n\nI think it is more up to the driver to numb the reply with\nsome dummy return value (i.e. input mode) or refactor the\ncallback so that it is acceptable for gpiolib to get an -EINVAL\nor so from the driver (again it will assume input mode) if the\ndriver can't return the direction at this time.\n\nYours,\nLinus Walleij\n--\nTo unsubscribe from this list: send the line \"unsubscribe linux-gpio\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"LXWin89S\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yBmPv3pHYz9t3R\n\tfor ;\n\tWed, 11 Oct 2017 18:51:15 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S932583AbdJKHvN (ORCPT );\n\tWed, 11 Oct 2017 03:51:13 -0400","from mail-it0-f49.google.com ([209.85.214.49]:48661 \"EHLO\n\tmail-it0-f49.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S932552AbdJKHvJ (ORCPT\n\t); Wed, 11 Oct 2017 03:51:09 -0400","by mail-it0-f49.google.com with SMTP id c3so1866158itc.3\n\tfor ;\n\tWed, 11 Oct 2017 00:51:09 -0700 (PDT)","by 10.79.14.140 with HTTP; Wed, 11 Oct 2017 00:51:08 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=1Enz2asVx8kRl6VYKaiehziA+2PaGIXUp7YGSMd07Qs=;\n\tb=LXWin89S3/Zi7Y1DeuzxixGujCVX4I2ujXLAoskt3VcrWxl5NyBO2to5dyBn1i5m8T\n\tRvOwXKKos+U6CRjQWdmk169u/EPMprZVSUEQlG/9Ijf0/VUrVX3SWTg75mxeSvIQVVvu\n\tlWSFeoM3fB5pOORnU0bM6JQpf7P4bx2kPEGS8=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=1Enz2asVx8kRl6VYKaiehziA+2PaGIXUp7YGSMd07Qs=;\n\tb=OCbfmorrTsDwdgkepOm8dUPMkRl/TVDO8ddDHXHoPk5Kc/NikqnWo/AfvVwbwEevuQ\n\tWr1mpjCEJW6ft1luQ8jCxDwmAuwf2/dV/4idgpNabRRzdrRFKZKUhGg+wStHZ16l8nC7\n\tfQQAh+HotxiR52VfpCaMWkCbbd20GpS0SUOCfzA/pg0TQjmf7VDyqZAz/4ErzFdZycqX\n\tFgetggZ6qW7PTKojAtHIkMVjRsKs9ONIqzlcCkt3E63B8MbpbKA8Nac3T6R/YlAf3f2k\n\tjsIMxNWL4yiDe4wiHdxgvZdoWZAVVoBz/fsDu+7qrf8TAAp1BzJbAcQH6IkSI78Ok6wa\n\tnYPA==","X-Gm-Message-State":"AMCzsaVHajqcBVg/gl5XnC8QbB2mVwLnjViBw5eVD+mt8xlGq7OyrPx7\n\tMAjphcUxQP3kP1v7ofipcUEg/XYsfmuW9TzBVk61+A==","X-Google-Smtp-Source":"AOwi7QCt28j5YEepfTrn91Wb+ZaGJF0IhtVzZfXSTQctWeR/fUN7WxoK/SuCEPJaoSZM3NQ+TFLzT5QJbNpmsTFB5Jk=","X-Received":"by 10.36.22.13 with SMTP id a13mr21475039ita.69.1507708269011;\n\tWed, 11 Oct 2017 00:51:09 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20171003220311.GU457@codeaurora.org>","References":"<1504798409-32041-1-git-send-email-timur@codeaurora.org>\n\t<20170919070422.GI3349@codeaurora.org>\n\t\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t\n\t\n\t<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>\n\t\n\t<255ad0dc-2d16-ae7f-0b45-500e23cff1a4@codeaurora.org>\n\t<20171003220311.GU457@codeaurora.org>","From":"Linus Walleij ","Date":"Wed, 11 Oct 2017 09:51:08 +0200","Message-ID":"","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Stephen Boyd ","Cc":"Timur Tabi , Andy Gross ,\n\tDavid Brown , anjiandi@codeaurora.org,\n\tBjorn Andersson ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\t\"thierry.reding@gmail.com\" ,\n\tMika Westerberg ,\n\tAndy Shevchenko ","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1785181,"web_url":"http://patchwork.ozlabs.org/comment/1785181/","msgid":"<20171012073922.GB18706@codeaurora.org>","list_archive_url":null,"date":"2017-10-12T07:39:22","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":6071,"url":"http://patchwork.ozlabs.org/api/people/6071/","name":"Stephen Boyd","email":"sboyd@codeaurora.org"},"content":"On 10/11, Linus Walleij wrote:\n> On Wed, Oct 4, 2017 at 12:03 AM, Stephen Boyd wrote:\n> \n> > Could we remove the pin direction finding part here in\n> > gpiochip_add_pin_range() and lazily resolve the pin direction\n> > when a pin is requested? We would need a similar check in the msm\n> > specific debugfs code where we skip pins that aren't requested.\n> > This is basically a revert of commit 72d320006177 (\"gpio: set up\n> > initial state from .get_direction()\").\n> \n> It seems reasonable for the gpiolib to be able to call this\n> function immediately after registering the new GPIO chip\n> with its vtable.\n\nI agree. I don't see the benefit though. Reading the direction\nlater would achieve the same effect and also work for ACPI qcom\nplatforms.\n\n> \n> I think it is more up to the driver to numb the reply with\n> some dummy return value (i.e. input mode) or refactor the\n> callback so that it is acceptable for gpiolib to get an -EINVAL\n> or so from the driver (again it will assume input mode) if the\n> driver can't return the direction at this time.\n> \n\nFor qcom platforms the driver will never be able to return the\ndirection for these certain pins because reading the register is\nnot allowed by the firmware. Doing so will cause the device to\ncrash with a security violation.\n\nIf you don't want to delay reading the direction until request\ntime, we should have the DT msm pinctrl drivers leave the\nget_direction() pointer as NULL. We don't need to read the\ndirection on DT platforms to make anything work.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"ccW279v9\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"cXRrydk8\"; dkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=sboyd@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yCN5s5r7Jz9s7m\n\tfor ;\n\tThu, 12 Oct 2017 18:39:29 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752716AbdJLHj2 (ORCPT );\n\tThu, 12 Oct 2017 03:39:28 -0400","from smtp.codeaurora.org ([198.145.29.96]:60640 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752673AbdJLHj1 (ORCPT\n\t); Thu, 12 Oct 2017 03:39:27 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid 2FAA060724; Thu, 12 Oct 2017 07:39:27 +0000 (UTC)","from localhost (i-global254.qualcomm.com [199.106.103.254])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\t(Authenticated sender: sboyd@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id 542B5607CC;\n\tThu, 12 Oct 2017 07:39:26 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507793967;\n\tbh=dSEvhKnV+4a3YMpgySiIC61vNggmj3t42QrwSgdLYa8=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=ccW279v9GyjEFW5Q90iSAHJ1maxfsLzWa4kGOCLuyPtSskowQMs95FLrqt7eIq+7l\n\tG1g4dijPeC9b4/R9duxTMxTTzdZfUaLW3pF6Rq3qUoGaXuNJKqK7/xur+zDvuYHYxG\n\tmmKMgBXzdVIBg9+T+fd22Dy9wzC3hR00ubfpTVjU=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507793966;\n\tbh=dSEvhKnV+4a3YMpgySiIC61vNggmj3t42QrwSgdLYa8=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=cXRrydk82pBDj0jjAHYR0AQxJvu8jDzYat3PvtSE3gqf6Lrp3mYuq+s+vWXzWG1gN\n\towNqXxYFtCAg7rUdWN9s9bEm3vaVlAUX+RA8/TcG39i9eZKYx/EIJ8+3JHE24QAGyt\n\tNihHajOvHwsc2ZJ4UMWk0fThYEl6ZWMJg8991U44="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org 542B5607CC","Date":"Thu, 12 Oct 2017 00:39:22 -0700","From":"Stephen Boyd ","To":"Linus Walleij ","Cc":"Timur Tabi , Andy Gross ,\n\tDavid Brown , anjiandi@codeaurora.org,\n\tBjorn Andersson ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\t\"thierry.reding@gmail.com\" ,\n\tMika Westerberg ,\n\tAndy Shevchenko ","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","Message-ID":"<20171012073922.GB18706@codeaurora.org>","References":"\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t\n\t\n\t<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>\n\t\n\t<255ad0dc-2d16-ae7f-0b45-500e23cff1a4@codeaurora.org>\n\t<20171003220311.GU457@codeaurora.org>\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1786734,"web_url":"http://patchwork.ozlabs.org/comment/1786734/","msgid":"<4f067c09-9ecf-9266-baa0-18575bca94eb@codeaurora.org>","list_archive_url":null,"date":"2017-10-13T23:26:23","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 10/03/2017 05:03 PM, Stephen Boyd wrote:\n> I don't see any value\n> beyond system wide debug in figuring out the default pin\n> configuration of a pin that doesn't have a consumer in Linux.\n\nI can agree with that.\n\n> Could we remove the pin direction finding part here in\n> gpiochip_add_pin_range() and lazily resolve the pin direction\n> when a pin is requested? We would need a similar check in the msm\n> specific debugfs code where we skip pins that aren't requested.\n> This is basically a revert of commit 72d320006177 (\"gpio: set up\n> initial state from .get_direction()\").\n> \n> ACPI can still describe only the pin ranges that they care about\n> exposing, but from the devicetree side it's been working well\n> enough to not touch pins that aren't used by anything in Linux.\n> \n> ---8<----\n> diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c\n> index cd003b74512f..673028823bc5 100644\n> --- a/drivers/gpio/gpiolib.c\n> +++ b/drivers/gpio/gpiolib.c\n> @@ -1210,16 +1210,7 @@ int gpiochip_add_data(struct gpio_chip *chip, void *data)\n> \t\t * wrong direction in sysfs.\n> \t\t */\n> \n> -\t\tif (chip->get_direction) {\n> -\t\t\t/*\n> -\t\t\t * If we have .get_direction, set up the initial\n> -\t\t\t * direction flag from the hardware.\n> -\t\t\t */\n> -\t\t\tint dir = chip->get_direction(chip, i);\n> -\n> -\t\t\tif (!dir)\n> -\t\t\t\tset_bit(FLAG_IS_OUT, &desc->flags);\n> -\t\t} else if (!chip->direction_input) {\n> +\t\tif (!chip->direction_input) {\n> \t\t\t/*\n> \t\t\t * If the chip lacks the .direction_input callback\n> \t\t\t * we logically assume all lines are outputs.\n> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c\n> index 273badd92561..4a0aeceb42f1 100644\n> --- a/drivers/pinctrl/qcom/pinctrl-msm.c\n> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c\n> @@ -24,7 +24,7 @@\n> #include \n> #include \n> #include \n> -#include \n> +#include \n> #include \n> #include \n> #include \n> @@ -494,6 +494,12 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,\n> \t};\n> \n> \tg = &pctrl->soc->groups[offset];\n> +\n> +\tif (!gpiochip_is_requested(chip, gpio)) {\n> +\t\tseq_printf(s, \" %-8s:\", g->name);\n> +\t\treturn;\n> +\t}\n> +\n> \tctl_reg = readl(pctrl->regs + g->ctl_reg);\n> \n> \tis_out = !!(ctl_reg & BIT(g->oe_bit));\n\nIn order for this to work, I had to add this function from patch #1:\n\nstatic int msm_gpio_request(struct gpio_chip *chip, unsigned int offset)\n{\n\tstruct msm_pinctrl *pctrl = gpiochip_get_data(chip);\n\tconst struct msm_pingroup *g = &pctrl->soc->groups[offset];\n\n\tif (!g->npins)\n\t\treturn -ENODEV;\n\n\treturn gpiochip_generic_request(chip, offset);\n}\n\nThe problem with this is that none of the GPIOs are \"requested\", so it \ndisplays an output like this:\n\n# cat /sys/kernel/debug/gpio\ngpiochip0: GPIOs 0-149, parent: platform/QCOM8002:00, QCOM8002:00:\n (null) :\n (null) :\n (null) :\n[... truncated ]]\n (null) :\n (null) :\n (null) :\n (null) :\n gpio36 :\n gpio37 :\n gpio38 :\n gpio39 :\n (null) :\n (null) :\n\nIt can't differentiate between GPIOs that don't exist and GPIOs that \nhaven't been requested. Plus, the \"(null)\" entries are what I've been \ntrying to avoid in the first place.\n\nSo overall, this patch seems okay, although it needs a little work. \nHowever, it doesn't address Bjorn's complaint that he doesn't want me to \nuse pin ranges at all.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"ICTwwFME\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"ICTwwFME\"; dkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=timur@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yDP445b2Rz9t2V\n\tfor ;\n\tSat, 14 Oct 2017 10:26:28 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752966AbdJMX01 (ORCPT );\n\tFri, 13 Oct 2017 19:26:27 -0400","from smtp.codeaurora.org ([198.145.29.96]:56416 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751617AbdJMX00 (ORCPT\n\t); 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20171003220311.GU457@codeaurora.org>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1786915,"web_url":"http://patchwork.ozlabs.org/comment/1786915/","msgid":"","list_archive_url":null,"date":"2017-10-14T22:43:16","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Thu, Oct 12, 2017 at 9:39 AM, Stephen Boyd wrote:\n\n> For qcom platforms the driver will never be able to return the\n> direction for these certain pins because reading the register is\n> not allowed by the firmware. Doing so will cause the device to\n> crash with a security violation.\n\nSo I guess the driver needs to know what pin registers it can't\naccess so the user does not get a gun to shoot in the foot with.\n\nIf we augment gpiolib to just handle -EACCES or something\n(-EIO?) from the driver .get_direction() callback for these lines,\nthings should be smooth?\n\nYours,\nLinus Walleij\n--\nTo unsubscribe from this list: send the line \"unsubscribe linux-gpio\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"DjaghxPR\"; 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charset=\"UTF-8\"","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1787067,"web_url":"http://patchwork.ozlabs.org/comment/1787067/","msgid":"<20171015201811.GA13063@mithrandir>","list_archive_url":null,"date":"2017-10-15T20:18:13","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":26234,"url":"http://patchwork.ozlabs.org/api/people/26234/","name":"Thierry Reding","email":"thierry.reding@gmail.com"},"content":"On Fri, Oct 13, 2017 at 06:26:23PM -0500, Timur Tabi wrote:\n> On 10/03/2017 05:03 PM, Stephen Boyd wrote:\n> > I don't see any value\n> > beyond system wide debug in figuring out the default pin\n> > configuration of a pin that doesn't have a consumer in Linux.\n> \n> I can agree with that.\n> \n> > Could we remove the pin direction finding part here in\n> > gpiochip_add_pin_range() and lazily resolve the pin direction\n> > when a pin is requested? We would need a similar check in the msm\n> > specific debugfs code where we skip pins that aren't requested.\n> > This is basically a revert of commit 72d320006177 (\"gpio: set up\n> > initial state from .get_direction()\").\n> > \n> > ACPI can still describe only the pin ranges that they care about\n> > exposing, but from the devicetree side it's been working well\n> > enough to not touch pins that aren't used by anything in Linux.\n> > \n> > ---8<----\n> > diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c\n> > index cd003b74512f..673028823bc5 100644\n> > --- a/drivers/gpio/gpiolib.c\n> > +++ b/drivers/gpio/gpiolib.c\n> > @@ -1210,16 +1210,7 @@ int gpiochip_add_data(struct gpio_chip *chip, void *data)\n> > \t\t * wrong direction in sysfs.\n> > \t\t */\n> > -\t\tif (chip->get_direction) {\n> > -\t\t\t/*\n> > -\t\t\t * If we have .get_direction, set up the initial\n> > -\t\t\t * direction flag from the hardware.\n> > -\t\t\t */\n> > -\t\t\tint dir = chip->get_direction(chip, i);\n> > -\n> > -\t\t\tif (!dir)\n> > -\t\t\t\tset_bit(FLAG_IS_OUT, &desc->flags);\n> > -\t\t} else if (!chip->direction_input) {\n> > +\t\tif (!chip->direction_input) {\n> > \t\t\t/*\n> > \t\t\t * If the chip lacks the .direction_input callback\n> > \t\t\t * we logically assume all lines are outputs.\n> > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c\n> > index 273badd92561..4a0aeceb42f1 100644\n> > --- a/drivers/pinctrl/qcom/pinctrl-msm.c\n> > +++ b/drivers/pinctrl/qcom/pinctrl-msm.c\n> > @@ -24,7 +24,7 @@\n> > #include \n> > #include \n> > #include \n> > -#include \n> > +#include \n> > #include \n> > #include \n> > #include \n> > @@ -494,6 +494,12 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,\n> > \t};\n> > \tg = &pctrl->soc->groups[offset];\n> > +\n> > +\tif (!gpiochip_is_requested(chip, gpio)) {\n> > +\t\tseq_printf(s, \" %-8s:\", g->name);\n> > +\t\treturn;\n> > +\t}\n> > +\n> > \tctl_reg = readl(pctrl->regs + g->ctl_reg);\n> > \tis_out = !!(ctl_reg & BIT(g->oe_bit));\n> \n> In order for this to work, I had to add this function from patch #1:\n> \n> static int msm_gpio_request(struct gpio_chip *chip, unsigned int offset)\n> {\n> \tstruct msm_pinctrl *pctrl = gpiochip_get_data(chip);\n> \tconst struct msm_pingroup *g = &pctrl->soc->groups[offset];\n> \n> \tif (!g->npins)\n> \t\treturn -ENODEV;\n> \n> \treturn gpiochip_generic_request(chip, offset);\n> }\n> \n> The problem with this is that none of the GPIOs are \"requested\", so it\n> displays an output like this:\n> \n> # cat /sys/kernel/debug/gpio\n> gpiochip0: GPIOs 0-149, parent: platform/QCOM8002:00, QCOM8002:00:\n> (null) :\n> (null) :\n> (null) :\n> [... truncated ]]\n> (null) :\n> (null) :\n> (null) :\n> (null) :\n> gpio36 :\n> gpio37 :\n> gpio38 :\n> gpio39 :\n> (null) :\n> (null) :\n> \n> It can't differentiate between GPIOs that don't exist and GPIOs that haven't\n> been requested.\n\nThis confuses me. Why would you even want to register pins that don't\nexist? It sounds to me like you're lying to gpiolib and then try to work\naround it trying to access the GPIOs that don't exist but which you told\nit were there.\n\nWhy not just tell gpiolib about only the GPIOs that exist?\n\nThierry","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"b6EN83aB\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yFXp46f77z9sRn\n\tfor ;\n\tMon, 16 Oct 2017 07:18:20 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751339AbdJOUSS (ORCPT );\n\tSun, 15 Oct 2017 16:18:18 -0400","from mail-wm0-f66.google.com ([74.125.82.66]:37127 \"EHLO\n\tmail-wm0-f66.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751337AbdJOUSR (ORCPT\n\t); Sun, 15 Oct 2017 16:18:17 -0400","by mail-wm0-f66.google.com with SMTP id r68so6130891wmr.4;\n\tSun, 15 Oct 2017 13:18:16 -0700 (PDT)","from localhost\n\t(p200300E41BE4FD00021F3CFFFE37B91B.dip0.t-ipconnect.de.\n\t[2003:e4:1be4:fd00:21f:3cff:fe37:b91b])\n\tby smtp.gmail.com with ESMTPSA id\n\tu96sm9495132wrc.68.2017.10.15.13.18.14\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tSun, 15 Oct 2017 13:18:14 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=date:from:to:cc:subject:message-id:references:mime-version\n\t:content-disposition:in-reply-to:user-agent;\n\tbh=RNXOEewUTee/6Iu+5InUJtakTLKqtyvMi/uay8sjdhY=;\n\tb=b6EN83aB7HZCrZigMslljAflV8X81PQPLuuxU+tQwXbHOyjobypqz45cHgX0s6jkQB\n\t1Oj/LeMkzX8GRJuFu9usWMYMXBl2FokkV7cavZ9bSbqh/WjkaHqbXnMJ40RAfWwBYWZi\n\tSTyuIuEW7hLuu/UK15sD7b4VUMjEJ30/aYlN1E5tYhdlwPlx8fgvvfIaWyOwIxhsm28H\n\tbb6hVBU6vzlWU/o4Q3cpJwalOOUxxypdhPSv0tQYeIdS7V0jMgM0CJFwMATF8rvMnLcO\n\tBXFIUWvnLFFrk6ZfycX6f87mNOXyTgea5aDOBUjqqhbQL3c0gcSwAR4tEuyRAy4zWxE3\n\tiRBg==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=RNXOEewUTee/6Iu+5InUJtakTLKqtyvMi/uay8sjdhY=;\n\tb=uQc06wlFqUrN/ihuQmBIZY/THeL6QOvnhXyaZcUoM9zg9fK32tPfHAIssxGst3bCOt\n\tNXcGHAov6FZ9mpnt5shhEqNVqilOC2CRXByGDsRKDldSZjYTnk+zvP5Ubi8AqWzWloxK\n\tOub14Du9wyT2GPkbr1c1ZPfJEYs7LwKhAk05D7V8okyUClScTIyz3SX4pdO1ZbuCoO/g\n\tgopEBtgV0DiS6inihRsglo0JA6Ckq6gyYgDjrpZBwm5iQfqNJ5A7uI/yQ+NwikmYLhi5\n\tauV3+HJ5iQIGpe6Wr8wEH6NDholqlOrLI4MBTjrnDrcHv1l3KDJUoJdnyDRxM62W5vpF\n\tsG6w==","X-Gm-Message-State":"AMCzsaULh1AAOsTWuKJ0a3fajHtPGKuwl0ELBo4ohckJkekgMjgbxaDz\n\tCygfPFHLrqHortQJPqyyoNE=","X-Google-Smtp-Source":"AOwi7QDNkzU3U0DFPBYTgBLjRKlQ0kbjOHOstXmqH/Xo8U7Gw5YAyKLsG+8aNykbT2Q/fa6lXfeNLw==","X-Received":"by 10.223.198.82 with SMTP id u18mr6839614wrg.5.1508098695726;\n\tSun, 15 Oct 2017 13:18:15 -0700 (PDT)","Date":"Sun, 15 Oct 2017 22:18:13 +0200","From":"Thierry Reding ","To":"Timur Tabi ","Cc":"Stephen Boyd ,\n\tLinus Walleij ,\n\tAndy Gross ,\n\tDavid Brown , anjiandi@codeaurora.org,\n\tBjorn Andersson ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\tMika Westerberg ,\n\tAndy Shevchenko ","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","Message-ID":"<20171015201811.GA13063@mithrandir>","References":"\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t\n\t\n\t<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>\n\t\n\t<255ad0dc-2d16-ae7f-0b45-500e23cff1a4@codeaurora.org>\n\t<20171003220311.GU457@codeaurora.org>\n\t<4f067c09-9ecf-9266-baa0-18575bca94eb@codeaurora.org>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha256;\n\tprotocol=\"application/pgp-signature\"; boundary=\"Q68bSM7Ycu6FN28Q\"","Content-Disposition":"inline","In-Reply-To":"<4f067c09-9ecf-9266-baa0-18575bca94eb@codeaurora.org>","User-Agent":"Mutt/1.9.1 (2017-09-22)","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1787086,"web_url":"http://patchwork.ozlabs.org/comment/1787086/","msgid":"","list_archive_url":null,"date":"2017-10-15T21:09:19","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 10/15/17 3:18 PM, Thierry Reding wrote:\n> This confuses me. Why would you even want to register pins that don't\n> exist? It sounds to me like you're lying to gpiolib and then try to work\n> around it trying to access the GPIOs that don't exist but which you told\n> it were there.\n> \n> Why not just tell gpiolib about only the GPIOs that exist?\n\nPlease look at my patches. That's exactly what they do, but no one else \nlikes that approach.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"oH3i2EW7\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"oH3i2EW7\"; dkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=timur@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yFYx12K8Gz9t2Q\n\tfor ;\n\tMon, 16 Oct 2017 08:09:25 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751235AbdJOVJX (ORCPT );\n\tSun, 15 Oct 2017 17:09:23 -0400","from smtp.codeaurora.org ([198.145.29.96]:41208 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750883AbdJOVJX (ORCPT\n\t); Sun, 15 Oct 2017 17:09:23 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid 9728C60C61; Sun, 15 Oct 2017 21:09:22 +0000 (UTC)","from [192.168.0.103] (cpe-72-177-20-249.austin.res.rr.com\n\t[72.177.20.249])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\t(Authenticated sender: timur@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id 0F93060C4D;\n\tSun, 15 Oct 2017 21:09:20 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1508101762;\n\tbh=92/RopE5g5iZOpJ218P0RBF3HdHfwHjtxvE2kt+C1/E=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=oH3i2EW7OncEFv9vzGD0o5oDSTWm9qB6/MXeuHAGZnFi1IKFeHjfF+uEo8rhoB5Mq\n\tEeYsZJicjTe/EqX0FwARXHLKuAqSEWJhxKlV3I7cznTC6DgYV5blhFTvia7kqnngNy\n\tR5gSNx8CKXp61jWUCaOuYYMsFoj2/a/MvZFBqCD4=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1508101762;\n\tbh=92/RopE5g5iZOpJ218P0RBF3HdHfwHjtxvE2kt+C1/E=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=oH3i2EW7OncEFv9vzGD0o5oDSTWm9qB6/MXeuHAGZnFi1IKFeHjfF+uEo8rhoB5Mq\n\tEeYsZJicjTe/EqX0FwARXHLKuAqSEWJhxKlV3I7cznTC6DgYV5blhFTvia7kqnngNy\n\tR5gSNx8CKXp61jWUCaOuYYMsFoj2/a/MvZFBqCD4="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org 0F93060C4D","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Thierry Reding ","Cc":"Stephen Boyd ,\n\tLinus Walleij ,\n\tAndy Gross ,\n\tDavid Brown , anjiandi@codeaurora.org,\n\tBjorn Andersson ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\tMika Westerberg ,\n\tAndy Shevchenko ","References":"\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t\n\t\n\t<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>\n\t\n\t<255ad0dc-2d16-ae7f-0b45-500e23cff1a4@codeaurora.org>\n\t<20171003220311.GU457@codeaurora.org>\n\t<4f067c09-9ecf-9266-baa0-18575bca94eb@codeaurora.org>\n\t<20171015201811.GA13063@mithrandir>","From":"Timur Tabi ","Message-ID":"","Date":"Sun, 15 Oct 2017 16:09:19 -0500","User-Agent":"Mozilla/5.0 (Macintosh; Intel Mac OS X 10.9; rv:52.0)\n\tGecko/20100101 Thunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20171015201811.GA13063@mithrandir>","Content-Type":"text/plain; charset=windows-1252; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1787440,"web_url":"http://patchwork.ozlabs.org/comment/1787440/","msgid":"<22ef3c75-bdf6-6aeb-a1dd-2d03eb46fd58@codeaurora.org>","list_archive_url":null,"date":"2017-10-16T13:42:41","subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","submitter":{"id":66858,"url":"http://patchwork.ozlabs.org/api/people/66858/","name":"Timur Tabi","email":"timur@codeaurora.org"},"content":"On 10/14/2017 05:43 PM, Linus Walleij wrote:\n> So I guess the driver needs to know what pin registers it can't\n> access so the user does not get a gun to shoot in the foot with.\n> \n> If we augment gpiolib to just handle -EACCES or something\n> (-EIO?) from the driver .get_direction() callback for these lines,\n> things should be smooth?\n\nYou mean like this:\n\ndiff --git a/drivers/pinctrl/qcom/pinctrl-msm.c \nb/drivers/pinctrl/qcom/pinctrl-msm.c\nindex ff491da64dab..ca4ae3d76eb4 100644\n--- a/drivers/pinctrl/qcom/pinctrl-msm.c\n+++ b/drivers/pinctrl/qcom/pinctrl-msm.c\n@@ -443,6 +443,14 @@ static int msm_gpio_get_direction(struct gpio_chip \n*chip, unsigned int offset)\n\n \tg = &pctrl->soc->groups[offset];\n\n+\t/*\n+\t * During initialization, gpiolib may query all GPIOs for their\n+\t * initial direction, regardless if they exist, so block access\n+\t * to those that are unavailable.\n+\t */\n+\tif (!g->npins)\n+\t\treturn -ENODEV;\n+\n \tval = readl(pctrl->regs + g->ctl_reg);\n\n \t/* 0 = output, 1 = input */\n\n\nThis is what I have in my patch already. I can return any error message \nyou like, but -ENODEV already works.\n\nThe problem is that it's insufficient. I also want the non-available \nGPIOs to be as absent as possible. I don't want them to show up in \n/sys/kernel/debug/gpio, and I don't want to be able to create them via \n/sys/class/gpio/export.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"LqKhPt53\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"ix0A2U+C\"; dkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=timur@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yFzzB6DZBz9t3R\n\tfor ;\n\tTue, 17 Oct 2017 00:42:46 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752139AbdJPNmp (ORCPT );\n\tMon, 16 Oct 2017 09:42:45 -0400","from smtp.codeaurora.org ([198.145.29.96]:55096 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751714AbdJPNmo (ORCPT\n\t); Mon, 16 Oct 2017 09:42:44 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid 20E0D6087C; Mon, 16 Oct 2017 13:42:44 +0000 (UTC)","from [10.222.143.167] (i-global254.qualcomm.com [199.106.103.254])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\t(Authenticated sender: timur@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id A23386083D;\n\tMon, 16 Oct 2017 13:42:42 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1508161364;\n\tbh=Unx3Cy+t6C5oZ9dMyLubI+ojWhevBTYH4BQLR64QfXU=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=LqKhPt53SHlBRts/4Hwc2cZp/OI4T0ZTB4zYbUBFG0PgwGGvQgtfodJ4BDD7oTaq/\n\tlm8BCSuSyXYbngaEJd/pJslfJC12eCDv/BL/n8/SUuLXEauLF/x72SfnScpbvdCQgc\n\tN6z2SNpxx6C+XaFgWdkRsrtRdzaAWoEd10w7rFS4=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1508161363;\n\tbh=Unx3Cy+t6C5oZ9dMyLubI+ojWhevBTYH4BQLR64QfXU=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=ix0A2U+Cj2dkGetu2+1wCiFHGCiGTMZUjQtynMCUgZ2srYOeE+VCU4LlasDcat8LR\n\th9kh0asWDwdtcPgGrE6xrjm1JdkZhojBLRl8EEDyvPHiaoRb6znegR9hp/CtSpjOoi\n\t2R68mLl0FDZukTW3oDKgwkJd7BnyFOPd5/GOjmzo="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org A23386083D","Subject":"Re: [PATCH 0/2] [v5] pinctrl: qcom: add support for sparse GPIOs","To":"Linus Walleij ,\n\tStephen Boyd ","Cc":"Andy Gross ,\n\tDavid Brown , anjiandi@codeaurora.org,\n\tBjorn Andersson ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-arm-msm@vger.kernel.org\" ,\n\t\"thierry.reding@gmail.com\" ,\n\tMika Westerberg ,\n\tAndy Shevchenko ","References":"\n\t<1ecdf6ee-5098-15d3-f85e-66b39a6c25f9@codeaurora.org>\n\t\n\t\n\t\n\t<619f48d2-59c7-c090-4ace-9e8db9f92064@codeaurora.org>\n\t\n\t<255ad0dc-2d16-ae7f-0b45-500e23cff1a4@codeaurora.org>\n\t<20171003220311.GU457@codeaurora.org>\n\t\n\t<20171012073922.GB18706@codeaurora.org>\n\t","From":"Timur Tabi ","Message-ID":"<22ef3c75-bdf6-6aeb-a1dd-2d03eb46fd58@codeaurora.org>","Date":"Mon, 16 Oct 2017 08:42:41 -0500","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}}]