[{"id":1766521,"web_url":"http://patchwork.ozlabs.org/comment/1766521/","msgid":"<20170911202403.hlrir7bbdi7abw5n@rob-hp-laptop>","list_archive_url":null,"date":"2017-09-11T20:24:03","subject":"Re: [PATCH v4 1/4] dt-bindings: Document the STM32 DMAMUX bindings","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Thu, Sep 07, 2017 at 01:52:45PM +0200, Pierre-Yves MORDRET wrote:\n> This patch adds the documentation of device tree bindings for the STM32\n> DMAMUX.\n> \n> Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com>\n> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>\n> ---\n>  Version history:\n>     v4:\n>         * Add multi-master ability for STM32 DMAMUX\n>         * Get rid of st,dmamux properties\n>     v3:\n>         * Change compatible to st,stm32h7-dmamux to be mode Soc specific\n>         * Add verbosity in dma-cells\n>     v2:\n>         * Move clock bindings from optional to mandatory one\n>         * Drop channelID bindings as managed dynamically from now on by\n>           DMAMUX driver.\n> ---\n> ---\n>  .../devicetree/bindings/dma/stm32-dmamux.txt       | 84 ++++++++++++++++++++++\n>  1 file changed, 84 insertions(+)\n>  create mode 100644 Documentation/devicetree/bindings/dma/stm32-dmamux.txt\n\nAcked-by: Rob Herring <robh@kernel.org>","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) 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MORDRET <pierre-yves.mordret@st.com>","Subject":"Re: [PATCH v4 1/4] dt-bindings: Document the STM32 DMAMUX bindings","Message-ID":"<20170911202403.hlrir7bbdi7abw5n@rob-hp-laptop>","References":"<1504785168-26572-1-git-send-email-pierre-yves.mordret@st.com>\n\t<1504785168-26572-2-git-send-email-pierre-yves.mordret@st.com>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<1504785168-26572-2-git-send-email-pierre-yves.mordret@st.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170911_132426_418115_3DBF45A1 ","X-CRM114-Status":"GOOD (  13.41  )","X-Spam-Score":"-1.0 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-1.0 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at 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dmaengine@vger.kernel.org,\n\tMaxime Coquelin <mcoquelin.stm32@gmail.com>,\n\tM'boumba Cedric Madianga <cedric.madianga@gmail.com>,\n\tDan Williams <dan.j.williams@intel.com>,\n\tFabrice GASNIER <fabrice.gasnier@st.com>,\n\tlinux-arm-kernel@lists.infradead.org, \n\tHerbert Xu <herbert@gondor.apana.org.au>","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1768063,"web_url":"http://patchwork.ozlabs.org/comment/1768063/","msgid":"<20170913174536.2hy6ubeef2s55t7y@rob-hp-laptop>","list_archive_url":null,"date":"2017-09-13T17:45:36","subject":"Re: [PATCH v4 3/4] dt-bindings: stm32-dma: add a property to handle\n\tSTM32 DMAMUX","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Thu, Sep 07, 2017 at 01:52:47PM +0200, Pierre-Yves MORDRET wrote:\n> STM32 DMA controller has to exposed its number of request line to be\n> addressed via STM32 DMAMUX.\n> \n> Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com>\n> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>\n> ---\n>  Version history:\n>     v4:\n>         * get rid of st,dmamux property\n>         * number of DMA requests is exposed for DMAMUX\n>     v3:\n>         * None\n>     v2:\n>         * Typo fix\n> ---\n> ---\n>  Documentation/devicetree/bindings/dma/stm32-dma.txt | 4 +++-\n>  1 file changed, 3 insertions(+), 1 deletion(-)\n\nAcked-by: Rob Herring <robh@kernel.org>","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"qp+imYow\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xspxC66Jcz9s78\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tThu, 14 Sep 2017 03:46:05 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<pierre-yves.mordret@st.com>","Subject":"Re: [PATCH v4 3/4] dt-bindings: stm32-dma: add a property to handle\n\tSTM32 DMAMUX","Message-ID":"<20170913174536.2hy6ubeef2s55t7y@rob-hp-laptop>","References":"<1504785168-26572-1-git-send-email-pierre-yves.mordret@st.com>\n\t<1504785168-26572-4-git-send-email-pierre-yves.mordret@st.com>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<1504785168-26572-4-git-send-email-pierre-yves.mordret@st.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170913_104559_027348_E1D3A440 ","X-CRM114-Status":"GOOD (  12.37  )","X-Spam-Score":"-1.0 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-1.0 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t0.5 RCVD_IN_SORBS_SPAM     RBL: SORBS: sender is a spam source\n\t[209.85.214.67 listed in dnsbl.sorbs.net]\n\t-0.0 RCVD_IN_MSPIKE_H3      RBL: Good reputation (+3)\n\t[209.85.214.67 listed in wl.mailspike.net]\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends\n\tin digit (robherring2[at]gmail.com)\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (robherring2[at]gmail.com)\n\t0.0 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level\n\tmail domains are different\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [209.85.214.67 listed in list.dnswl.org]\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.0 RCVD_IN_MSPIKE_WL      Mailspike good senders\n\t0.2 FREEMAIL_FORGED_FROMDOMAIN 2nd level domains in From and\n\tEnvelopeFrom freemail headers are different","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"Mark Rutland <mark.rutland@arm.com>, devicetree@vger.kernel.org,\n\tAmelie Delaunay <amelie.delaunay@st.com>,\n\tAlexandre Torgue <alexandre.torgue@st.com>,\n\tVinod Koul <vinod.koul@intel.com>, Russell King <linux@armlinux.org.uk>,\n\tFabien DESSENNE <fabien.dessenne@st.com>, \n\tlinux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,\n\tMaxime Coquelin <mcoquelin.stm32@gmail.com>,\n\tM'boumba Cedric Madianga <cedric.madianga@gmail.com>,\n\tDan Williams <dan.j.williams@intel.com>,\n\tFabrice GASNIER <fabrice.gasnier@st.com>,\n\tlinux-arm-kernel@lists.infradead.org, \n\tHerbert Xu <herbert@gondor.apana.org.au>","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1772518,"web_url":"http://patchwork.ozlabs.org/comment/1772518/","msgid":"<19fea8c6-5c23-025f-6048-532011055044@st.com>","list_archive_url":null,"date":"2017-09-21T07:59:07","subject":"Re: [PATCH v4 0/4] Add STM32 DMAMUX support","submitter":{"id":71499,"url":"http://patchwork.ozlabs.org/api/people/71499/","name":"Pierre Yves MORDRET","email":"pierre-yves.mordret@st.com"},"content":"Hello\n\nGentle ping for driver review since DT Bindings have been acked by Rob Herring.\n\nThanks\nPy\n\nOn 09/07/2017 01:52 PM, Pierre-Yves MORDRET wrote:\n> This patchset adds support for the STM32 DMA multiplexer.\n> It allows to map any peripheral DMA request to any channel of the product\n> DMAs.\n> This IP has been introduced with STM32H7 SoC.\n> \n> ---\n>  Version history:\n>     v4:\n>         * Add multi-master ability for STM32 DMAMUX\n>         * Get rid of st,dmamux property and custom API between STM32\n>           DMAMUX and DMA. Bindings has changed.\n>           DMAMUX will read DMA masters from Device Tree from now on.\n>           Merely one DMAMUX node is needed now.\n>         * Only STM32 DMA are allowed to be connected onto DMAMUX\n>         * channelID is computed locally within the driver and crafted in\n>           dma_psec to be passed toward DMA master.\n>           DMAMUX router sorts out which DMA master will serve the\n>           request automatically.\n>         * This version forbids the use of DMA in standalone and DMAMUX at\n>           the same time : all clients need to be connected either on DMA\n>           or DMAMUX ; no mix up\n>     v3:\n>         * change compatible to st,stm32h7-dmamux to be mode Soc specific\n>         * add verbosity in dma-cells\n> ---\n> \n> Pierre-Yves MORDRET (4):\n>   dt-bindings: Document the STM32 DMAMUX bindings\n>   dmaengine: Add STM32 DMAMUX driver\n>   dt-bindings: stm32-dma: add a property to handle STM32 DMAMUX\n>   ARM: configs: stm32: Add MDMA support in STM32 defconfig\n> \n>  .../devicetree/bindings/dma/stm32-dma.txt          |   4 +-\n>  .../devicetree/bindings/dma/stm32-dmamux.txt       |  84 ++++++\n>  arch/arm/configs/stm32_defconfig                   |   1 +\n>  drivers/dma/Kconfig                                |   9 +\n>  drivers/dma/Makefile                               |   1 +\n>  drivers/dma/stm32-dmamux.c                         | 321 +++++++++++++++++++++\n>  6 files changed, 419 insertions(+), 1 deletion(-)\n>  create mode 100644 Documentation/devicetree/bindings/dma/stm32-dmamux.txt\n>  create mode 100644 drivers/dma/stm32-dmamux.c\n>","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1504785168-26572-1-git-send-email-pierre-yves.mordret@st.com>","Content-Language":"en-US","X-Originating-IP":"[10.75.127.47]","X-ClientProxiedBy":"SFHDAG6NODE2.st.com (10.75.127.17) To SFHDAG5NODE2.st.com\n\t(10.75.127.14)","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-21_01:, , signatures=0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170921_010007_594712_C59D21FB ","X-CRM114-Status":"GOOD (  16.12  )","X-Spam-Score":"-2.6 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-2.6 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow trust [91.207.212.93 listed in list.dnswl.org]\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1772716,"web_url":"http://patchwork.ozlabs.org/comment/1772716/","msgid":"<a88a83ba-9477-36ae-87ba-a35f477a5ca1@ti.com>","list_archive_url":null,"date":"2017-09-21T11:25:58","subject":"Re: [PATCH v4 2/4] dmaengine: Add STM32 DMAMUX driver","submitter":{"id":9142,"url":"http://patchwork.ozlabs.org/api/people/9142/","name":"Peter Ujfalusi","email":"peter.ujfalusi@ti.com"},"content":"﻿\nTexas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki\n\nOn 2017-09-07 14:52, Pierre-Yves MORDRET wrote:\n> This patch implements the STM32 DMAMUX driver.\n> \n> The DMAMUX request multiplexer allows routing a DMA request line between\n> the peripherals and the DMA controllers of the product. The routing\n> function is ensured by a programmable multi-channel DMA request line\n> multiplexer. Each channel selects a unique DMA request line,\n> unconditionally or synchronously with events from its DMAMUX\n> synchronization inputs. The DMAMUX may also be used as a DMA request\n> generator from programmable events on its input trigger signals\n> \n> Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com>\n> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>\n> ---\n>  Version history:\n>     v4:\n>         * Get rid of st,dmamux property and custom API between STM32\n>           DMAMUX and DMA.\n>           DMAMUX will read DMA masters from Device Tree from now on.\n>           Merely one DMAMUX node is needed now.\n>         * Only STM32 DMA are allowed to be connected onto DMAMUX\n>         * channelID is computed locally within the driver and crafted in\n>           dma_psec to be passed toward DMA master.\n>           DMAMUX router sorts out which DMA master will serve the\n>           request automatically.\n>         * This version forbids the use of DMA in standalone and DMAMUX at\n>           the same time : all clients need to be connected either on DMA\n>           or DMAMUX ; no mix up\n\nGreat that you got it working w/o a custom API!\nI have one comment, which actually valid for the ti-dma-crossbar driver\nas well...\n\n> +static void *stm32_dmamux_route_allocate(struct of_phandle_args *dma_spec,\n> +\t\t\t\t\t struct of_dma *ofdma)\n> +{\n> +\tstruct platform_device *pdev = of_find_device_by_node(ofdma->of_node);\n> +\tstruct stm32_dmamux_data *dmamux = platform_get_drvdata(pdev);\n> +\tstruct stm32_dmamux *mux;\n> +\tu32 i, min, max, ret;\n> +\tunsigned long flags;\n> +\n> +\tif (dma_spec->args_count != 3) {\n> +\t\tdev_err(&pdev->dev, \"invalid number of dma mux args\\n\");\n> +\t\treturn ERR_PTR(-EINVAL);\n> +\t}\n> +\n> +\tif (dma_spec->args[0] > dmamux->dmamux_requests) {\n> +\t\tdev_err(&pdev->dev, \"invalid mux request number: %d\\n\",\n> +\t\t\tdma_spec->args[0]);\n> +\t\treturn ERR_PTR(-EINVAL);\n> +\t}\n> +\n> +\tmux = kzalloc(sizeof(*mux), GFP_KERNEL);\n> +\tif (!mux)\n> +\t\treturn ERR_PTR(-ENOMEM);\n> +\n> +\tspin_lock_irqsave(&dmamux->lock, flags);\n> +\tmux->chan_id = find_first_zero_bit(dmamux->dma_inuse,\n> +\t\t\t\t\t   dmamux->dma_requests);\n\nyou pick the first available chan_id here under the lock.\n\n> +\tspin_unlock_irqrestore(&dmamux->lock, flags);\n> +\tif (mux->chan_id == dmamux->dma_requests) {\n> +\t\tdev_err(&pdev->dev, \"Run out of free DMA requests\\n\");\n> +\t\tkfree(mux);\n> +\t\treturn ERR_PTR(-ENOMEM);\n> +\t}\n> +\n> +\t/* Look for DMA Master */\n> +\tfor (i = 1, min = 0, max = dmamux->dma_reqs[i];\n> +\t     i <= dmamux->dma_reqs[0];\n> +\t     min += dmamux->dma_reqs[i], max += dmamux->dma_reqs[++i])\n> +\t\tif (mux->chan_id < max)\n> +\t\t\tbreak;\n> +\tmux->master = i - 1;\n> +\n> +\t/* The of_node_put() will be done in of_dma_router_xlate function */\n> +\tdma_spec->np = of_parse_phandle(ofdma->of_node, \"dma-masters\", i - 1);\n> +\tif (!dma_spec->np) {\n> +\t\tdev_err(&pdev->dev, \"can't get dma master\\n\");\n> +\t\tkfree(mux);\n> +\t\treturn ERR_PTR(-EINVAL);\n> +\t}\n> +\n> +\t/* Set dma request */\n> +\tspin_lock_irqsave(&dmamux->lock, flags);\n> +\tif (!IS_ERR(dmamux->clk)) {\n> +\t\tret = clk_enable(dmamux->clk);\n> +\t\tif (ret < 0) {\n> +\t\t\tspin_unlock_irqrestore(&dmamux->lock, flags);\n> +\t\t\tkfree(mux);\n> +\t\t\tdev_err(&pdev->dev, \"clk_prep_enable issue: %d\\n\", ret);\n> +\t\t\treturn ERR_PTR(ret);\n> +\t\t}\n> +\t}\n> +\tspin_unlock_irqrestore(&dmamux->lock, flags);\n> +\n> +\tset_bit(mux->chan_id, dmamux->dma_inuse);\n\nBut nothing stops other parallel threads to pick the same chan_id since\nyou have released the lock (released, got the lock to protect the set\ndma request and released it again). imho the find_first_zero_bit() and\nthe set_bit() should be done within the same lock to avoid race conditions.\n\n- Péter","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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\n\tThu, 21 Sep 2017 06:26:01 -0500","from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23])\n\tby dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LBPuWA002345; \n\tThu, 21 Sep 2017 06:25:56 -0500","from DLEE107.ent.ti.com (157.170.170.37) by DLEE112.ent.ti.com\n\t(157.170.170.23) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tThu, 21 Sep 2017 06:25:56 -0500","from dflp32.itg.ti.com (10.64.6.15) by DLEE107.ent.ti.com\n\t(157.170.170.37) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Thu, 21 Sep 2017 06:25:56 -0500","from [192.168.2.6] (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LBPqnX008169;\n\tThu, 21 Sep 2017 06:25:52 -0500"],"DKIM-Signature":["v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:\n\tMessage-ID:From:References:To:Subject:Reply-To:Cc:Content-ID:\n\tContent-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc\n\t:Resent-Message-ID:List-Owner;\n\tbh=OESBbZwrLCGdmDXu5BgYYjHsxcHhwsDAh37A9uRylnU=;\n\tb=Ejn2MU/jElsR2AoVLFMp56XBVh\n\tdasF4cG+vdeZmImpSVseQCrsKaYsVj25btEy4rA+6Lkzsb2P5X3myG/vhzVSBKGqkxrTvzLp/h5OQ\n\tzYbkkbRBuwxvDmExupT7OIy+iIYWbAkgkzTHR1dMhv4L4UlGUpE9ruQUFKujy+cOVsLm8+BfS5LTO\n\t6oNsjvdoXTvITlqqviY0/jyEgA4IUtkH0C0Of7JgXlRlAVlvGbCIKVbeGs1aKDlrP+C/qZxUo9mz+\n\tMVEJS6zYBVhz4PSb45Ut/MF/jWpacgl+7feHnKtb0yeic/qveF7geKjjrehzQPSsU472mhmhgo/ie\n\thcPWbm4g==;","v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1505993161;\n\tbh=Ej8uze4cLDbMjhUO0/xNjeZHi23CBzzxBVT6luz69a0=;\n\th=Subject:To:References:From:Date:In-Reply-To;\n\tb=ETS/ycvtJnAjgK2dX5egu1Wjcf9oYUoID5jeWD5JTW5cMrpAKNLJ5XD959sDafulG\n\t8VRpYND7e02cfev9OFcBVRyehKTlhvFjZLge5DBUhbwITtMMyUUDVHQ699oEucK8ay\n\t8ObBEDPzD9awBwQ7q/xnncAadiJtoSL2CaPbWgnk="],"Subject":"Re: [PATCH v4 2/4] dmaengine: Add STM32 DMAMUX driver","To":"Pierre-Yves MORDRET <pierre-yves.mordret@st.com>, Vinod Koul\n\t<vinod.koul@intel.com>, Rob Herring <robh+dt@kernel.org>, Mark Rutland\n\t<mark.rutland@arm.com>, Maxime Coquelin <mcoquelin.stm32@gmail.com>, \n\tAlexandre Torgue <alexandre.torgue@st.com>, Russell King\n\t<linux@armlinux.org.uk>, Dan Williams <dan.j.williams@intel.com>,\n\t\"M'boumba Cedric Madianga\" <cedric.madianga@gmail.com>, Fabrice GASNIER\n\t<fabrice.gasnier@st.com>, Herbert Xu <herbert@gondor.apana.org.au>,\n\tFabien DESSENNE <fabien.dessenne@st.com>,\n\tAmelie Delaunay <amelie.delaunay@st.com>, <dmaengine@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, \n\t<linux-kernel@vger.kernel.org>","References":"<1504785168-26572-1-git-send-email-pierre-yves.mordret@st.com>\n\t<1504785168-26572-3-git-send-email-pierre-yves.mordret@st.com>","From":"Peter Ujfalusi <peter.ujfalusi@ti.com>","Message-ID":"<a88a83ba-9477-36ae-87ba-a35f477a5ca1@ti.com>","Date":"Thu, 21 Sep 2017 14:25:58 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.8.0","MIME-Version":"1.0","In-Reply-To":"<1504785168-26572-3-git-send-email-pierre-yves.mordret@st.com>","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170921_042756_694991_BE313E75 ","X-CRM114-Status":"GOOD (  18.25  )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-2.0 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [198.47.19.16 listed in list.dnswl.org]\n\t-0.0 SPF_PASS               SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED            Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1772787,"web_url":"http://patchwork.ozlabs.org/comment/1772787/","msgid":"<ab012ccc-21e4-e487-4ef1-056c36a65cd0@st.com>","list_archive_url":null,"date":"2017-09-21T12:47:59","subject":"Re: [PATCH v4 2/4] dmaengine: Add STM32 DMAMUX driver","submitter":{"id":71499,"url":"http://patchwork.ozlabs.org/api/people/71499/","name":"Pierre Yves MORDRET","email":"pierre-yves.mordret@st.com"},"content":"On 09/21/2017 01:25 PM, Peter Ujfalusi wrote:\n> \n> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki\n> \n> \n> Great that you got it working w/o a custom API!\n> I have one comment, which actually valid for the ti-dma-crossbar driver\n> as well...\n\nYes. That cleans up a little bit the sw architecture. But still this custom API\nallowed both DMAMUX and DMA at the same time since using the same channel ID\nallocator.\nOk this is another story to be addressed out of this thread ;)\n\n> \n>> +static void *stm32_dmamux_route_allocate(struct of_phandle_args *dma_spec,\n>> +\t\t\t\t\t struct of_dma *ofdma)\n>> +\n>> +\tspin_lock_irqsave(&dmamux->lock, flags);\n>> +\tmux->chan_id = find_first_zero_bit(dmamux->dma_inuse,\n>> +\t\t\t\t\t   dmamux->dma_requests);\n> \n> you pick the first available chan_id here under the lock.\n> \n>> +\tspin_unlock_irqrestore(&dmamux->lock, flags);\n>> +\tif (mux->chan_id == dmamux->dma_requests) {\n>> ...\n>> +\t/* Set dma request */\n>> +\tspin_lock_irqsave(&dmamux->lock, flags);\n>> +\tif (!IS_ERR(dmamux->clk)) {\n>> ...\n>> +\tspin_unlock_irqrestore(&dmamux->lock, flags);\n>> +\n>> +\tset_bit(mux->chan_id, dmamux->dma_inuse);\n> \n> But nothing stops other parallel threads to pick the same chan_id since\n> you have released the lock (released, got the lock to protect the set\n> dma request and released it again). imho the find_first_zero_bit() and\n> the set_bit() should be done within the same lock to avoid race conditions.\n> \n> - Péter\n> \n\nYep good catch : That's correct. Even if probability to happen is rather low, it\nmay happen.\nWill solve that.\n\nPy","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"Kn9t7C6a\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xybyw28f6z9t3m\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tThu, 21 Sep 2017 22:49:12 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dv0uj-0000yY-9V; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:\n\tMessage-ID:From:References:To:Subject:Reply-To:Cc:Content-ID:\n\tContent-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc\n\t:Resent-Message-ID:List-Owner;\n\tbh=S1QQf/tGIoLas0/Hh4yIfY9O/PUWNM7lC6tkRETmWBQ=;\n\tb=Kn9t7C6aCmEOKFmz7GV7onjJxG\n\tB23KbWBliWjYmT24W0SuxDglnsw7qYI1nEAYk4kqhzKUTyYsley0V0VwFTqygsmq6B22sh+dyQB3E\n\t2N+W2EtUoS52ZV6obJnn9yk5l9oVHO2Wc8ZbgKHLSa7kHKPZ6ywTByQDt/QMIohdjKJhFBe4fL7NM\n\tL/NOgn1uBeqtlgo6ABuzDKgOJqb+nA1wdukQ+M4D753fzCDvbeh4VAMmjheQRMeALnTq6O7cO2JxR\n\tTH0fKwOzQSEk7VBxVpZXiOsoBrdyp6swW5bcJu+HtO+o4M+yv71vD3MYDiRODYcaT1B8iqTiMnl01\n\tb8rPTtoA==;","Subject":"Re: [PATCH v4 2/4] dmaengine: Add STM32 DMAMUX driver","To":"Peter Ujfalusi <peter.ujfalusi@ti.com>, Vinod Koul <vinod.koul@intel.com>,\n\tRob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,\n\tMaxime Coquelin <mcoquelin.stm32@gmail.com>, Alexandre Torgue\n\t<alexandre.torgue@st.com>, Russell King <linux@armlinux.org.uk>,\n\tDan Williams <dan.j.williams@intel.com>, \"M'boumba Cedric Madianga\"\n\t<cedric.madianga@gmail.com>, Fabrice GASNIER <fabrice.gasnier@st.com>,\n\tHerbert Xu <herbert@gondor.apana.org.au>, Fabien DESSENNE\n\t<fabien.dessenne@st.com>,\n\tAmelie Delaunay <amelie.delaunay@st.com>, <dmaengine@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, \n\t<linux-kernel@vger.kernel.org>","References":"<1504785168-26572-1-git-send-email-pierre-yves.mordret@st.com>\n\t<1504785168-26572-3-git-send-email-pierre-yves.mordret@st.com>\n\t<a88a83ba-9477-36ae-87ba-a35f477a5ca1@ti.com>","From":"Pierre Yves MORDRET <pierre-yves.mordret@st.com>","Message-ID":"<ab012ccc-21e4-e487-4ef1-056c36a65cd0@st.com>","Date":"Thu, 21 Sep 2017 14:47:59 +0200","User-Agent":"Mozilla/5.0 (X11; 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