[{"id":1772514,"web_url":"http://patchwork.ozlabs.org/comment/1772514/","msgid":"<19fea8c6-5c23-025f-6048-532011055044@st.com>","list_archive_url":null,"date":"2017-09-21T07:59:07","subject":"Re: [PATCH v4 0/4] Add STM32 DMAMUX support","submitter":{"id":71499,"url":"http://patchwork.ozlabs.org/api/people/71499/","name":"Pierre Yves MORDRET","email":"pierre-yves.mordret@st.com"},"content":"Hello\n\nGentle ping for driver review since DT Bindings have been acked by Rob Herring.\n\nThanks\nPy\n\nOn 09/07/2017 01:52 PM, Pierre-Yves MORDRET wrote:\n> This patchset adds support for the STM32 DMA multiplexer.\n> It allows to map any peripheral DMA request to any channel of the product\n> DMAs.\n> This IP has been introduced with STM32H7 SoC.\n> \n> ---\n> Version history:\n> v4:\n> * Add multi-master ability for STM32 DMAMUX\n> * Get rid of st,dmamux property and custom API between STM32\n> DMAMUX and DMA. Bindings has changed.\n> DMAMUX will read DMA masters from Device Tree from now on.\n> Merely one DMAMUX node is needed now.\n> * Only STM32 DMA are allowed to be connected onto DMAMUX\n> * channelID is computed locally within the driver and crafted in\n> dma_psec to be passed toward DMA master.\n> DMAMUX router sorts out which DMA master will serve the\n> request automatically.\n> * This version forbids the use of DMA in standalone and DMAMUX at\n> the same time : all clients need to be connected either on DMA\n> or DMAMUX ; no mix up\n> v3:\n> * change compatible to st,stm32h7-dmamux to be mode Soc specific\n> * add verbosity in dma-cells\n> ---\n> \n> Pierre-Yves MORDRET (4):\n> dt-bindings: Document the STM32 DMAMUX bindings\n> dmaengine: Add STM32 DMAMUX driver\n> dt-bindings: stm32-dma: add a property to handle STM32 DMAMUX\n> ARM: configs: stm32: Add MDMA support in STM32 defconfig\n> \n> .../devicetree/bindings/dma/stm32-dma.txt | 4 +-\n> .../devicetree/bindings/dma/stm32-dmamux.txt | 84 ++++++\n> arch/arm/configs/stm32_defconfig | 1 +\n> drivers/dma/Kconfig | 9 +\n> drivers/dma/Makefile | 1 +\n> drivers/dma/stm32-dmamux.c | 321 +++++++++++++++++++++\n> 6 files changed, 419 insertions(+), 1 deletion(-)\n> create mode 100644 Documentation/devicetree/bindings/dma/stm32-dmamux.txt\n> create mode 100644 drivers/dma/stm32-dmamux.c\n> \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyTYb315mz9t3v\n\tfor ;\n\tThu, 21 Sep 2017 18:00:19 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751877AbdIUIAR (ORCPT\n\t);\n\tThu, 21 Sep 2017 04:00:17 -0400","from mx08-00178001.pphosted.com ([91.207.212.93]:44102 \"EHLO\n\tmx07-00178001.pphosted.com\" rhost-flags-OK-OK-OK-FAIL)\n\tby vger.kernel.org with ESMTP id S1751581AbdIUIAP (ORCPT\n\t); Thu, 21 Sep 2017 04:00:15 -0400","from pps.filterd (m0046661.ppops.net [127.0.0.1])\n\tby mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8L7x9Y4010774; Thu, 21 Sep 2017 09:59:22 +0200","from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])\n\tby mx08-00178001.pphosted.com with ESMTP id 2d3twp4qt5-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tThu, 21 Sep 2017 09:59:22 +0200","from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9])\n\tby beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 9988431;\n\tThu, 21 Sep 2017 07:59:19 +0000 (GMT)","from Webmail-eu.st.com (sfhdag5node2.st.com [10.75.127.14])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 65F1D14CE;\n\tThu, 21 Sep 2017 07:59:19 +0000 (GMT)","from [10.201.23.236] (10.75.127.47) by SFHDAG5NODE2.st.com\n\t(10.75.127.14) with Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tThu, 21 Sep 2017 09:59:16 +0200"],"Subject":"Re: [PATCH v4 0/4] Add STM32 DMAMUX support","To":"Vinod Koul , Rob Herring ,\n\tMark Rutland ,\n\tMaxime Coquelin ,\n\tAlexandre Torgue ,\n\tRussell King ,\n\tDan Williams ,\n\t\"M'boumba Cedric Madianga\" ,\n\tFabrice GASNIER ,\n\tHerbert Xu ,\n\tFabien DESSENNE ,\n\tAmelie Delaunay ,\n\t, ,\n\t, ","References":"<1504785168-26572-1-git-send-email-pierre-yves.mordret@st.com>","From":"Pierre Yves MORDRET ","Message-ID":"<19fea8c6-5c23-025f-6048-532011055044@st.com>","Date":"Thu, 21 Sep 2017 09:59:07 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1504785168-26572-1-git-send-email-pierre-yves.mordret@st.com>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-Originating-IP":"[10.75.127.47]","X-ClientProxiedBy":"SFHDAG6NODE2.st.com (10.75.127.17) To SFHDAG5NODE2.st.com\n\t(10.75.127.14)","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-21_01:, , signatures=0","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1772719,"web_url":"http://patchwork.ozlabs.org/comment/1772719/","msgid":"","list_archive_url":null,"date":"2017-09-21T11:25:58","subject":"Re: [PATCH v4 2/4] dmaengine: Add STM32 DMAMUX driver","submitter":{"id":9142,"url":"http://patchwork.ozlabs.org/api/people/9142/","name":"Peter Ujfalusi","email":"peter.ujfalusi@ti.com"},"content":"\nTexas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki\n\nOn 2017-09-07 14:52, Pierre-Yves MORDRET wrote:\n> This patch implements the STM32 DMAMUX driver.\n> \n> The DMAMUX request multiplexer allows routing a DMA request line between\n> the peripherals and the DMA controllers of the product. The routing\n> function is ensured by a programmable multi-channel DMA request line\n> multiplexer. Each channel selects a unique DMA request line,\n> unconditionally or synchronously with events from its DMAMUX\n> synchronization inputs. The DMAMUX may also be used as a DMA request\n> generator from programmable events on its input trigger signals\n> \n> Signed-off-by: M'boumba Cedric Madianga \n> Signed-off-by: Pierre-Yves MORDRET \n> ---\n> Version history:\n> v4:\n> * Get rid of st,dmamux property and custom API between STM32\n> DMAMUX and DMA.\n> DMAMUX will read DMA masters from Device Tree from now on.\n> Merely one DMAMUX node is needed now.\n> * Only STM32 DMA are allowed to be connected onto DMAMUX\n> * channelID is computed locally within the driver and crafted in\n> dma_psec to be passed toward DMA master.\n> DMAMUX router sorts out which DMA master will serve the\n> request automatically.\n> * This version forbids the use of DMA in standalone and DMAMUX at\n> the same time : all clients need to be connected either on DMA\n> or DMAMUX ; no mix up\n\nGreat that you got it working w/o a custom API!\nI have one comment, which actually valid for the ti-dma-crossbar driver\nas well...\n\n> +static void *stm32_dmamux_route_allocate(struct of_phandle_args *dma_spec,\n> +\t\t\t\t\t struct of_dma *ofdma)\n> +{\n> +\tstruct platform_device *pdev = of_find_device_by_node(ofdma->of_node);\n> +\tstruct stm32_dmamux_data *dmamux = platform_get_drvdata(pdev);\n> +\tstruct stm32_dmamux *mux;\n> +\tu32 i, min, max, ret;\n> +\tunsigned long flags;\n> +\n> +\tif (dma_spec->args_count != 3) {\n> +\t\tdev_err(&pdev->dev, \"invalid number of dma mux args\\n\");\n> +\t\treturn ERR_PTR(-EINVAL);\n> +\t}\n> +\n> +\tif (dma_spec->args[0] > dmamux->dmamux_requests) {\n> +\t\tdev_err(&pdev->dev, \"invalid mux request number: %d\\n\",\n> +\t\t\tdma_spec->args[0]);\n> +\t\treturn ERR_PTR(-EINVAL);\n> +\t}\n> +\n> +\tmux = kzalloc(sizeof(*mux), GFP_KERNEL);\n> +\tif (!mux)\n> +\t\treturn ERR_PTR(-ENOMEM);\n> +\n> +\tspin_lock_irqsave(&dmamux->lock, flags);\n> +\tmux->chan_id = find_first_zero_bit(dmamux->dma_inuse,\n> +\t\t\t\t\t dmamux->dma_requests);\n\nyou pick the first available chan_id here under the lock.\n\n> +\tspin_unlock_irqrestore(&dmamux->lock, flags);\n> +\tif (mux->chan_id == dmamux->dma_requests) {\n> +\t\tdev_err(&pdev->dev, \"Run out of free DMA requests\\n\");\n> +\t\tkfree(mux);\n> +\t\treturn ERR_PTR(-ENOMEM);\n> +\t}\n> +\n> +\t/* Look for DMA Master */\n> +\tfor (i = 1, min = 0, max = dmamux->dma_reqs[i];\n> +\t i <= dmamux->dma_reqs[0];\n> +\t min += dmamux->dma_reqs[i], max += dmamux->dma_reqs[++i])\n> +\t\tif (mux->chan_id < max)\n> +\t\t\tbreak;\n> +\tmux->master = i - 1;\n> +\n> +\t/* The of_node_put() will be done in of_dma_router_xlate function */\n> +\tdma_spec->np = of_parse_phandle(ofdma->of_node, \"dma-masters\", i - 1);\n> +\tif (!dma_spec->np) {\n> +\t\tdev_err(&pdev->dev, \"can't get dma master\\n\");\n> +\t\tkfree(mux);\n> +\t\treturn ERR_PTR(-EINVAL);\n> +\t}\n> +\n> +\t/* Set dma request */\n> +\tspin_lock_irqsave(&dmamux->lock, flags);\n> +\tif (!IS_ERR(dmamux->clk)) {\n> +\t\tret = clk_enable(dmamux->clk);\n> +\t\tif (ret < 0) {\n> +\t\t\tspin_unlock_irqrestore(&dmamux->lock, flags);\n> +\t\t\tkfree(mux);\n> +\t\t\tdev_err(&pdev->dev, \"clk_prep_enable issue: %d\\n\", ret);\n> +\t\t\treturn ERR_PTR(ret);\n> +\t\t}\n> +\t}\n> +\tspin_unlock_irqrestore(&dmamux->lock, flags);\n> +\n> +\tset_bit(mux->chan_id, dmamux->dma_inuse);\n\nBut nothing stops other parallel threads to pick the same chan_id since\nyou have released the lock (released, got the lock to protect the set\ndma request and released it again). imho the find_first_zero_bit() and\nthe set_bit() should be done within the same lock to avoid race conditions.\n\n- Péter\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"ETS/ycvt\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyZ9s74zHz9t43\n\tfor ;\n\tThu, 21 Sep 2017 21:28:33 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751846AbdIUL2T (ORCPT\n\t);\n\tThu, 21 Sep 2017 07:28:19 -0400","from fllnx209.ext.ti.com ([198.47.19.16]:55575 \"EHLO\n\tfllnx209.ext.ti.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751593AbdIUL2Q (ORCPT\n\t); Thu, 21 Sep 2017 07:28:16 -0400","from dlelxv90.itg.ti.com ([172.17.2.17])\n\tby fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LBQ1US005851; \n\tThu, 21 Sep 2017 06:26:01 -0500","from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23])\n\tby dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LBPuWA002345; \n\tThu, 21 Sep 2017 06:25:56 -0500","from DLEE107.ent.ti.com (157.170.170.37) by DLEE112.ent.ti.com\n\t(157.170.170.23) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tThu, 21 Sep 2017 06:25:56 -0500","from dflp32.itg.ti.com (10.64.6.15) by DLEE107.ent.ti.com\n\t(157.170.170.37) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Thu, 21 Sep 2017 06:25:56 -0500","from [192.168.2.6] (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LBPqnX008169;\n\tThu, 21 Sep 2017 06:25:52 -0500"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1505993161;\n\tbh=Ej8uze4cLDbMjhUO0/xNjeZHi23CBzzxBVT6luz69a0=;\n\th=Subject:To:References:From:Date:In-Reply-To;\n\tb=ETS/ycvtJnAjgK2dX5egu1Wjcf9oYUoID5jeWD5JTW5cMrpAKNLJ5XD959sDafulG\n\t8VRpYND7e02cfev9OFcBVRyehKTlhvFjZLge5DBUhbwITtMMyUUDVHQ699oEucK8ay\n\t8ObBEDPzD9awBwQ7q/xnncAadiJtoSL2CaPbWgnk=","Subject":"Re: [PATCH v4 2/4] dmaengine: Add STM32 DMAMUX driver","To":"Pierre-Yves MORDRET ,\n\tVinod Koul , Rob Herring , \n\tMark Rutland ,\n\tMaxime Coquelin ,\n\tAlexandre Torgue ,\n\tRussell King ,\n\tDan Williams ,\n\t\"M'boumba Cedric Madianga\" ,\n\tFabrice GASNIER ,\n\tHerbert Xu ,\n\tFabien DESSENNE ,\n\tAmelie Delaunay ,\n\t, ,\n\t, ","References":"<1504785168-26572-1-git-send-email-pierre-yves.mordret@st.com>\n\t<1504785168-26572-3-git-send-email-pierre-yves.mordret@st.com>","From":"Peter Ujfalusi ","Message-ID":"","Date":"Thu, 21 Sep 2017 14:25:58 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.8.0","MIME-Version":"1.0","In-Reply-To":"<1504785168-26572-3-git-send-email-pierre-yves.mordret@st.com>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"quoted-printable","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1772788,"web_url":"http://patchwork.ozlabs.org/comment/1772788/","msgid":"","list_archive_url":null,"date":"2017-09-21T12:47:59","subject":"Re: [PATCH v4 2/4] dmaengine: Add STM32 DMAMUX driver","submitter":{"id":71499,"url":"http://patchwork.ozlabs.org/api/people/71499/","name":"Pierre Yves MORDRET","email":"pierre-yves.mordret@st.com"},"content":"On 09/21/2017 01:25 PM, Peter Ujfalusi wrote:\n> \n> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki\n> \n> \n> Great that you got it working w/o a custom API!\n> I have one comment, which actually valid for the ti-dma-crossbar driver\n> as well...\n\nYes. That cleans up a little bit the sw architecture. But still this custom API\nallowed both DMAMUX and DMA at the same time since using the same channel ID\nallocator.\nOk this is another story to be addressed out of this thread ;)\n\n> \n>> +static void *stm32_dmamux_route_allocate(struct of_phandle_args *dma_spec,\n>> +\t\t\t\t\t struct of_dma *ofdma)\n>> +\n>> +\tspin_lock_irqsave(&dmamux->lock, flags);\n>> +\tmux->chan_id = find_first_zero_bit(dmamux->dma_inuse,\n>> +\t\t\t\t\t dmamux->dma_requests);\n> \n> you pick the first available chan_id here under the lock.\n> \n>> +\tspin_unlock_irqrestore(&dmamux->lock, flags);\n>> +\tif (mux->chan_id == dmamux->dma_requests) {\n>> ...\n>> +\t/* Set dma request */\n>> +\tspin_lock_irqsave(&dmamux->lock, flags);\n>> +\tif (!IS_ERR(dmamux->clk)) {\n>> ...\n>> +\tspin_unlock_irqrestore(&dmamux->lock, flags);\n>> +\n>> +\tset_bit(mux->chan_id, dmamux->dma_inuse);\n> \n> But nothing stops other parallel threads to pick the same chan_id since\n> you have released the lock (released, got the lock to protect the set\n> dma request and released it again). imho the find_first_zero_bit() and\n> the set_bit() should be done within the same lock to avoid race conditions.\n> \n> - Péter\n> \n\nYep good catch : That's correct. Even if probability to happen is rather low, it\nmay happen.\nWill solve that.\n\nPy\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xybyx1ss6z9t43\n\tfor ;\n\tThu, 21 Sep 2017 22:49:13 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751550AbdIUMtL (ORCPT\n\t);\n\tThu, 21 Sep 2017 08:49:11 -0400","from mx08-00178001.pphosted.com ([91.207.212.93]:2607 \"EHLO\n\tmx07-00178001.pphosted.com\" rhost-flags-OK-OK-OK-FAIL)\n\tby vger.kernel.org with ESMTP id S1751387AbdIUMtK (ORCPT\n\t); Thu, 21 Sep 2017 08:49:10 -0400","from pps.filterd (m0046660.ppops.net [127.0.0.1])\n\tby mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8LChhvG007536; Thu, 21 Sep 2017 14:48:11 +0200","from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])\n\tby mx08-00178001.pphosted.com with ESMTP id 2d4a2v1gxa-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tThu, 21 Sep 2017 14:48:11 +0200","from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9])\n\tby beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 157B338;\n\tThu, 21 Sep 2017 12:48:09 +0000 (GMT)","from Webmail-eu.st.com (sfhdag5node2.st.com [10.75.127.14])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A4BC726F0;\n\tThu, 21 Sep 2017 12:48:09 +0000 (GMT)","from [10.201.23.236] (10.75.127.47) by SFHDAG5NODE2.st.com\n\t(10.75.127.14) with Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tThu, 21 Sep 2017 14:48:08 +0200"],"Subject":"Re: [PATCH v4 2/4] dmaengine: Add STM32 DMAMUX driver","To":"Peter Ujfalusi , Vinod Koul ,\n\tRob Herring , Mark Rutland ,\n\tMaxime Coquelin ,\n\tAlexandre Torgue ,\n\tRussell King ,\n\tDan Williams ,\n\t\"M'boumba Cedric Madianga\" ,\n\tFabrice GASNIER ,\n\tHerbert Xu ,\n\tFabien DESSENNE ,\n\tAmelie Delaunay ,\n\t, ,\n\t, ","References":"<1504785168-26572-1-git-send-email-pierre-yves.mordret@st.com>\n\t<1504785168-26572-3-git-send-email-pierre-yves.mordret@st.com>\n\t","From":"Pierre Yves MORDRET ","Message-ID":"","Date":"Thu, 21 Sep 2017 14:47:59 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=\"utf-8\"","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","X-Originating-IP":"[10.75.127.47]","X-ClientProxiedBy":"SFHDAG7NODE3.st.com (10.75.127.21) To SFHDAG5NODE2.st.com\n\t(10.75.127.14)","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-21_02:, , signatures=0","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]