[{"id":1807828,"web_url":"http://patchwork.ozlabs.org/comment/1807828/","msgid":"<4460193.XjJsJKMKHF@diego>","list_archive_url":null,"date":"2017-11-20T21:25:18","subject":"Re: [U-Boot] [PATCH 00/10] rockchip: add tpl and OPTEE support for\n\trk3229","submitter":{"id":10645,"url":"http://patchwork.ozlabs.org/api/people/10645/","name":"Heiko Stuebner","email":"heiko@sntech.de"},"content":"Hi Kever,\n\nAm Mittwoch, 6. September 2017, 10:14:27 CET schrieb Kever Yang:\n> Add some generic options for TPL support for arm 32bit, and then\n> and TPL support for rk3229(cortex-A7), and then add OPTEE support\n> in SPL.\n\nI was now finally able to test this series and I'm getting mixed results.\nI was following the instructions in the evb-rk3229 README file.\n\n\nOn the uboot side it seems to work nicely when applied against 2017.09.\n\nBut when I try to rebase it on top of the next branch of u-boot-rockchip\nI end up with the TPL claiming a \"Missing DTB\", so it looks like it needs\na respin to follow the recent changes.\n\nOn the optee-side I also seem to do something wrong or so.\nWhen using the binaries from the rkbin github repository I end up with\n[0] and [1].\nWhen compiling the most-recent optee it fails with [2].\n\nWith some intermediate optee or the one from Tony Xie's repository\nit compiles and uboot seems to start, but then fails when the kernel tries\nto bring up the secondary cpus [3]. And interestingly while it seems to go\nthrough optee, I don't see any optee-messages.\n\nIf you could point me into the right direction, I would be very grateful :-)\n\n\nThanks\nHeiko\n\n\n[0]\nTPL Inittimer init done\nReturning to boot ROM...\n\nU-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\nTrying to boot from MMC1\nINF TEE-CORE:init_primary_helper:319: Initializing (1.0.1-65-gf1567d3-dev #22 Fri Mar 24 06:16:54 UTC 2017 arm)\nINF TEE-CORE:init_primary_helper:320: Release version: 1.9\nINF TEE-CORE:init_teecore:79: teecore inits done\n[hangs here]\n\n[1]\nTPL Inittimer init done\nReturning to boot ROM...\n\nU-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\nTrying to boot from MMC1\nINF [0x0] TEE-CORE:init_primary_helper:366: Initializing (1.1.0-120-gb4aded8-dev #3 Wed Dec 28 01:56:52 UTC 2016 arm)\nINF [0x0] TEE-CORE:init_primary_helper:367: Release version: 1.6\nINF [0x0] TEE-CORE:init_teecore:83: teecore inits done\n[hangs here]\n\n[2]\nmake CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x\n CHK out/arm-plat-rockchip/conf.mk\n UPD out/arm-plat-rockchip/conf.mk\n CHK out/arm-plat-rockchip/include/generated/conf.h\n UPD out/arm-plat-rockchip/include/generated/conf.h\n CHK out/arm-plat-rockchip/core/include/generated/asm-defines.h\nmake: *** No rule, to create „core/include/tee/tee_cryp_provider.h“, needed by\n „out/arm-plat-rockchip/core/arch/arm/kernel/user_ta.o“.\n\n[3]\nTPL Inittimer init done\nReturning to boot ROM...\n\nU-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\nTrying to boot from MMC1\n\n\nU-Boot 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 21:29:43 +0100)\n\nModel: Nexbox A95X R1\nDRAM: 1022 MiB\n[...]\nStarting kernel ...\n\n[ 0.000000] Booting Linux on physical CPU 0xf00\n[ 0.000000] Linux version 4.14.0-13997-g55102e6ed32a-dirty (hstuebner@phil) (gcc version 7.2.0 (Debian 7.2.0-11)) #437 SMP Mon Nov 20 11:33:35 CET 2017\n[ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d\n[ 0.000000] CPU: div instructions available: patching division code\n[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache\n[ 0.000000] OF: fdt: Machine model: Nexbox A95X R1\n[ 0.000000] earlycon: uart8250 at MMIO32 0x11030000 (options '')\n[ 0.000000] bootconsole [uart8250] enabled\n[ 0.000000] Memory policy: Data cache writealloc\n[ 0.000000] efi: Getting EFI parameters from FDT:\n[ 0.000000] efi: UEFI not found.\n[ 0.000000] cma: Reserved 64 MiB at 0x9c000000\n[ 0.000000] psci: probing for conduit method from DT.\n[ 0.000000] psci: PSCIv1.0 detected in firmware.\n[ 0.000000] psci: Using standard PSCI v0.2 function IDs\n[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.\n[ 0.000000] random: fast init done\n[ 0.000000] percpu: Embedded 17 pages/cpu @ef7a4000 s39116 r8192 d22324 u69632\n[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260096\n[...]\n[ 0.000000] CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00\n[ 0.000000] Setting up static identity map for 0x60300000 - 0x603000a0\n[ 0.000000] Hierarchical SRCU implementation.\n[ 0.000000] EFI services will not be available.\n[ 0.000000] smp: Bringing up secondary CPUs ...\n[hangs here]","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3ygnpw1WL9z9sPr\n\tfor ;\n\tTue, 21 Nov 2017 12:21:12 +1100 (AEDT)","by lists.denx.de (Postfix, from userid 105)\n\tid E9AA7C21F7C; Tue, 21 Nov 2017 01:21:01 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 79DEEC21DC3;\n\tTue, 21 Nov 2017 01:20:58 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 1B468C21F57; Mon, 20 Nov 2017 21:25:26 +0000 (UTC)","from gloria.sntech.de (gloria.sntech.de [95.129.55.99])\n\tby lists.denx.de (Postfix) with ESMTPS id B67C5C21EFF\n\tfor ; Mon, 20 Nov 2017 21:25:25 +0000 (UTC)","from ip923422a5.dynamic.kabel-deutschland.de ([146.52.34.165]\n\thelo=diego.localnet) by gloria.sntech.de with esmtpsa\n\t(TLS1.1:DHE_RSA_AES_256_CBC_SHA1:256)\n\t(Exim 4.80) (envelope-from )\n\tid 1eGtZ8-0001Ud-RD; Mon, 20 Nov 2017 22:25:19 +0100"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC,\n\tRCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","From":"Heiko =?iso-8859-1?q?St=FCbner?= ","To":"Kever Yang ,\n\tJoseph Chen ","Date":"Mon, 20 Nov 2017 22:25:18 +0100","Message-ID":"<4460193.XjJsJKMKHF@diego>","User-Agent":"KMail/5.2.3 (Linux/4.13.0-1-amd64; KDE/5.37.0; x86_64; ; )","In-Reply-To":"<1504664087-26473-1-git-send-email-kever.yang@rock-chips.com>","References":"<1504664087-26473-1-git-send-email-kever.yang@rock-chips.com>","MIME-Version":"1.0","X-Mailman-Approved-At":"Tue, 21 Nov 2017 01:20:57 +0000","Cc":"u-boot@lists.denx.de, Alexander Graf ,\n\tStefan Agner ,\n\tAlexandru Gagniuc ,\n\tJagan Teki , \n\tvagrant@debian.org, Jacob Chen ,\n\tAndy Yan ,\n\tMaxime Ripard ","Subject":"Re: [U-Boot] [PATCH 00/10] rockchip: add tpl and OPTEE support for\n\trk3229","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1808190,"web_url":"http://patchwork.ozlabs.org/comment/1808190/","msgid":"<3a9eb658-8504-fbd8-75ff-e21e574e5593@ti.com>","list_archive_url":null,"date":"2017-11-21T15:43:57","subject":"Re: [U-Boot] [PATCH 00/10] rockchip: add tpl and OPTEE support for\n\trk3229","submitter":{"id":67226,"url":"http://patchwork.ozlabs.org/api/people/67226/","name":"Andrew Davis","email":"afd@ti.com"},"content":"On 11/20/2017 03:25 PM, Heiko Stübner wrote:\n> Hi Kever,\n> \n> Am Mittwoch, 6. September 2017, 10:14:27 CET schrieb Kever Yang:\n>> Add some generic options for TPL support for arm 32bit, and then\n>> and TPL support for rk3229(cortex-A7), and then add OPTEE support\n>> in SPL.\n> \n> I was now finally able to test this series and I'm getting mixed results.\n> I was following the instructions in the evb-rk3229 README file.\n> \n> \n> On the uboot side it seems to work nicely when applied against 2017.09.\n> \n> But when I try to rebase it on top of the next branch of u-boot-rockchip\n> I end up with the TPL claiming a \"Missing DTB\", so it looks like it needs\n> a respin to follow the recent changes.\n> \n> On the optee-side I also seem to do something wrong or so.\n> When using the binaries from the rkbin github repository I end up with\n> [0] and [1].\n> When compiling the most-recent optee it fails with [2].\n> \n> With some intermediate optee or the one from Tony Xie's repository\n> it compiles and uboot seems to start, but then fails when the kernel tries\n> to bring up the secondary cpus [3]. And interestingly while it seems to go\n> through optee, I don't see any optee-messages.\n> \n> If you could point me into the right direction, I would be very grateful :-)\n> \n> \n> Thanks\n> Heiko\n> \n> \n> [0]\n> TPL Inittimer init done\n> Returning to boot ROM...\n> \n> U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\n> Trying to boot from MMC1\n> INF TEE-CORE:init_primary_helper:319: Initializing (1.0.1-65-gf1567d3-dev #22 Fri Mar 24 06:16:54 UTC 2017 arm)\n> INF TEE-CORE:init_primary_helper:320: Release version: 1.9\n> INF TEE-CORE:init_teecore:79: teecore inits done\n> [hangs here]\n> \n> [1]\n> TPL Inittimer init done\n> Returning to boot ROM...\n> \n> U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\n> Trying to boot from MMC1\n> INF [0x0] TEE-CORE:init_primary_helper:366: Initializing (1.1.0-120-gb4aded8-dev #3 Wed Dec 28 01:56:52 UTC 2016 arm)\n> INF [0x0] TEE-CORE:init_primary_helper:367: Release version: 1.6\n> INF [0x0] TEE-CORE:init_teecore:83: teecore inits done\n> [hangs here]\n> \n> [2]\n> make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x\n> CHK out/arm-plat-rockchip/conf.mk\n> UPD out/arm-plat-rockchip/conf.mk\n> CHK out/arm-plat-rockchip/include/generated/conf.h\n> UPD out/arm-plat-rockchip/include/generated/conf.h\n> CHK out/arm-plat-rockchip/core/include/generated/asm-defines.h\n> make: *** No rule, to create „core/include/tee/tee_cryp_provider.h“, needed by\n> „out/arm-plat-rockchip/core/arch/arm/kernel/user_ta.o“.\n> \n\nmake clean; git clean -fx..; then try again\n\n> [3]\n> TPL Inittimer init done\n> Returning to boot ROM...\n> \n> U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\n> Trying to boot from MMC1\n> \n> \n> U-Boot 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 21:29:43 +0100)\n> \n> Model: Nexbox A95X R1\n> DRAM: 1022 MiB\n> [...]\n> Starting kernel ...\n> \n> [ 0.000000] Booting Linux on physical CPU 0xf00\n> [ 0.000000] Linux version 4.14.0-13997-g55102e6ed32a-dirty (hstuebner@phil) (gcc version 7.2.0 (Debian 7.2.0-11)) #437 SMP Mon Nov 20 11:33:35 CET 2017\n> [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d\n> [ 0.000000] CPU: div instructions available: patching division code\n> [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache\n> [ 0.000000] OF: fdt: Machine model: Nexbox A95X R1\n> [ 0.000000] earlycon: uart8250 at MMIO32 0x11030000 (options '')\n> [ 0.000000] bootconsole [uart8250] enabled\n> [ 0.000000] Memory policy: Data cache writealloc\n> [ 0.000000] efi: Getting EFI parameters from FDT:\n> [ 0.000000] efi: UEFI not found.\n> [ 0.000000] cma: Reserved 64 MiB at 0x9c000000\n> [ 0.000000] psci: probing for conduit method from DT.\n> [ 0.000000] psci: PSCIv1.0 detected in firmware.\n> [ 0.000000] psci: Using standard PSCI v0.2 function IDs\n> [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.\n> [ 0.000000] random: fast init done\n> [ 0.000000] percpu: Embedded 17 pages/cpu @ef7a4000 s39116 r8192 d22324 u69632\n> [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260096\n> [...]\n> [ 0.000000] CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00\n> [ 0.000000] Setting up static identity map for 0x60300000 - 0x603000a0\n> [ 0.000000] Hierarchical SRCU implementation.\n> [ 0.000000] EFI services will not be available.\n> [ 0.000000] smp: Bringing up secondary CPUs ...\n> [hangs here]\n> \n\nI've been here plenty of times when brining up OP-TEE on TI platforms,\nfor me it's OP-TEE parking the secondary CPUs in a bad way. I'm not sure\nabout the Rockchip arch, are the extra cores brought up with PSCI?\nAnyway can you get JTAG on this device, see where the other cores are stuck.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"t0mEcvLX\";\n\tdkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3yh9fW4QgPz9s0g\n\tfor ;\n\tWed, 22 Nov 2017 03:15:15 +1100 (AEDT)","by lists.denx.de (Postfix, from userid 105)\n\tid 3B080C21F0F; Tue, 21 Nov 2017 16:14:57 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 16E98C21EE7;\n\tTue, 21 Nov 2017 16:14:25 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid ABFA7C21C29; Tue, 21 Nov 2017 15:44:15 +0000 (UTC)","from fllnx210.ext.ti.com (fllnx210.ext.ti.com [198.47.19.17])\n\tby lists.denx.de (Postfix) with ESMTPS id 0D82CC21C29\n\tfor ; Tue, 21 Nov 2017 15:44:14 +0000 (UTC)","from dlelxv90.itg.ti.com ([172.17.2.17])\n\tby fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id vALFhw2D018881; \n\tTue, 21 Nov 2017 09:43:58 -0600","from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25])\n\tby dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vALFhvFV022284; \n\tTue, 21 Nov 2017 09:43:57 -0600","from DFLE105.ent.ti.com (10.64.6.26) by DFLE104.ent.ti.com\n\t(10.64.6.25) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tTue, 21 Nov 2017 09:43:57 -0600","from dlep33.itg.ti.com (157.170.170.75) by DFLE105.ent.ti.com\n\t(10.64.6.26) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Tue, 21 Nov 2017 09:43:57 -0600","from [128.247.59.224] (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vALFhvqV032201;\n\tTue, 21 Nov 2017 09:43:57 -0600"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC,\n\tT_DKIM_INVALID\n\tautolearn=unavailable autolearn_force=no version=3.4.0","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1511279038;\n\tbh=en8TPMSd06O+o8bLY1OegUfBfTsyonjVrx8xTqBGuOQ=;\n\th=Subject:To:CC:References:From:Date:In-Reply-To;\n\tb=t0mEcvLX2eu5lRgeXfr2zsMbDTVNIWaDaV+NvvxijltMIogfBqc6W/mdM376ObC61\n\th3nTe5njmG3VHSJD0q1PF1lKA5j6KHtS10LIE/LN0PnrMEdo4RgQoHM3L6lMKyqXTu\n\tBpNsBCWhFoLujHsjbmqJ32evOL7E8KS1uLcOh1EI=","To":"=?utf-8?q?Heiko_St=C3=BCbner?= , Kever Yang\n\t, Joseph Chen ","References":"<1504664087-26473-1-git-send-email-kever.yang@rock-chips.com>\n\t<4460193.XjJsJKMKHF@diego>","From":"\"Andrew F. Davis\" ","Message-ID":"<3a9eb658-8504-fbd8-75ff-e21e574e5593@ti.com>","Date":"Tue, 21 Nov 2017 09:43:57 -0600","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.4.0","MIME-Version":"1.0","In-Reply-To":"<4460193.XjJsJKMKHF@diego>","Content-Language":"en-US","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","X-Mailman-Approved-At":"Tue, 21 Nov 2017 16:14:23 +0000","Cc":"u-boot@lists.denx.de, Alexander Graf ,\n\tStefan Agner ,\n\tAlexandru Gagniuc ,\n\tJagan Teki , \n\tvagrant@debian.org, Jacob Chen ,\n\tAndy Yan ,\n\tMaxime Ripard ","Subject":"Re: [U-Boot] [PATCH 00/10] rockchip: add tpl and OPTEE support for\n\trk3229","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1808609,"web_url":"http://patchwork.ozlabs.org/comment/1808609/","msgid":"","list_archive_url":null,"date":"2017-11-22T09:10:19","subject":"Re: [U-Boot] [PATCH 00/10] rockchip: add tpl and OPTEE support for\n\trk3229","submitter":{"id":71760,"url":"http://patchwork.ozlabs.org/api/people/71760/","name":"陈健洪","email":"chenjh@rock-chips.com"},"content":"在 2017/11/21 23:43, Andrew F. Davis 写道:\n> On 11/20/2017 03:25 PM, Heiko Stübner wrote:\n>> Hi Kever,\n>>\n>> Am Mittwoch, 6. September 2017, 10:14:27 CET schrieb Kever Yang:\n>>> Add some generic options for TPL support for arm 32bit, and then\n>>> and TPL support for rk3229(cortex-A7), and then add OPTEE support\n>>> in SPL.\n>> I was now finally able to test this series and I'm getting mixed results.\n>> I was following the instructions in the evb-rk3229 README file.\n>>\n>>\n>> On the uboot side it seems to work nicely when applied against 2017.09.\n>>\n>> But when I try to rebase it on top of the next branch of u-boot-rockchip\n>> I end up with the TPL claiming a \"Missing DTB\", so it looks like it needs\n>> a respin to follow the recent changes.\n>>\n>> On the optee-side I also seem to do something wrong or so.\n>> When using the binaries from the rkbin github repository I end up with\n>> [0] and [1].\n>> When compiling the most-recent optee it fails with [2].\n>>\n>> With some intermediate optee or the one from Tony Xie's repository\n>> it compiles and uboot seems to start, but then fails when the kernel tries\n>> to bring up the secondary cpus [3]. And interestingly while it seems to go\n>> through optee, I don't see any optee-messages.\n>>\n>> If you could point me into the right direction, I would be very grateful :-)\n>>\n>>\n>> Thanks\n>> Heiko\n>>\n>>\n>> [0]\n>> TPL Inittimer init done\n>> Returning to boot ROM...\n>>\n>> U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\n>> Trying to boot from MMC1\n>> INF TEE-CORE:init_primary_helper:319: Initializing (1.0.1-65-gf1567d3-dev #22 Fri Mar 24 06:16:54 UTC 2017 arm)\n>> INF TEE-CORE:init_primary_helper:320: Release version: 1.9\n>> INF TEE-CORE:init_teecore:79: teecore inits done\n>> [hangs here]\n>>\n>> [1]\n>> TPL Inittimer init done\n>> Returning to boot ROM...\n>>\n>> U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\n>> Trying to boot from MMC1\n>> INF [0x0] TEE-CORE:init_primary_helper:366: Initializing (1.1.0-120-gb4aded8-dev #3 Wed Dec 28 01:56:52 UTC 2016 arm)\n>> INF [0x0] TEE-CORE:init_primary_helper:367: Release version: 1.6\n>> INF [0x0] TEE-CORE:init_teecore:83: teecore inits done\n>> [hangs here]\n>>\n>> [2]\n>> make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x\n>> CHK out/arm-plat-rockchip/conf.mk\n>> UPD out/arm-plat-rockchip/conf.mk\n>> CHK out/arm-plat-rockchip/include/generated/conf.h\n>> UPD out/arm-plat-rockchip/include/generated/conf.h\n>> CHK out/arm-plat-rockchip/core/include/generated/asm-defines.h\n>> make: *** No rule, to create „core/include/tee/tee_cryp_provider.h“, needed by\n>> „out/arm-plat-rockchip/core/arch/arm/kernel/user_ta.o“.\n>>\n> make clean; git clean -fx..; then try again\n>\n>> [3]\n>> TPL Inittimer init done\n>> Returning to boot ROM...\n>>\n>> U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\n>> Trying to boot from MMC1\n>>\n>>\n>> U-Boot 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 21:29:43 +0100)\n>>\n>> Model: Nexbox A95X R1\n>> DRAM: 1022 MiB\n>> [...]\n>> Starting kernel ...\n>>\n>> [ 0.000000] Booting Linux on physical CPU 0xf00\n>> [ 0.000000] Linux version 4.14.0-13997-g55102e6ed32a-dirty (hstuebner@phil) (gcc version 7.2.0 (Debian 7.2.0-11)) #437 SMP Mon Nov 20 11:33:35 CET 2017\n>> [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d\n>> [ 0.000000] CPU: div instructions available: patching division code\n>> [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache\n>> [ 0.000000] OF: fdt: Machine model: Nexbox A95X R1\n>> [ 0.000000] earlycon: uart8250 at MMIO32 0x11030000 (options '')\n>> [ 0.000000] bootconsole [uart8250] enabled\n>> [ 0.000000] Memory policy: Data cache writealloc\n>> [ 0.000000] efi: Getting EFI parameters from FDT:\n>> [ 0.000000] efi: UEFI not found.\n>> [ 0.000000] cma: Reserved 64 MiB at 0x9c000000\n>> [ 0.000000] psci: probing for conduit method from DT.\n>> [ 0.000000] psci: PSCIv1.0 detected in firmware.\n>> [ 0.000000] psci: Using standard PSCI v0.2 function IDs\n>> [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.\n>> [ 0.000000] random: fast init done\n>> [ 0.000000] percpu: Embedded 17 pages/cpu @ef7a4000 s39116 r8192 d22324 u69632\n>> [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260096\n>> [...]\n>> [ 0.000000] CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00\n>> [ 0.000000] Setting up static identity map for 0x60300000 - 0x603000a0\n>> [ 0.000000] Hierarchical SRCU implementation.\n>> [ 0.000000] EFI services will not be available.\n>> [ 0.000000] smp: Bringing up secondary CPUs ...\n>> [hangs here]\n>>\n> I've been here plenty of times when brining up OP-TEE on TI platforms,\n> for me it's OP-TEE parking the secondary CPUs in a bad way. I'm not sure\n> about the Rockchip arch, are the extra cores brought up with PSCI?\n> Anyway can you get JTAG on this device, see where the other cores are stuck.\n>\n\nIf your OP-TEE is from Tony Xie's repository, I think the reason maybe \nthat cntfrq register is not been initialized. core0 stucks at udelay() \nin the OP-TEE when it tries to bring up core1. So can you try to \ninitialize cntfrq as 24000000 in the SPL/TPL ? maybe it helps.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3yhffw20Q9z9s7f\n\tfor ;\n\tWed, 22 Nov 2017 22:02:14 +1100 (AEDT)","by lists.denx.de (Postfix, from userid 105)\n\tid 8A426C21D9F; Wed, 22 Nov 2017 11:02:07 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 2DBF3C21C73;\n\tWed, 22 Nov 2017 11:02:04 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 1F809C21DB5; Wed, 22 Nov 2017 09:08:52 +0000 (UTC)","from regular1.263xmail.com (regular1.263xmail.com [211.150.99.134])\n\tby lists.denx.de (Postfix) with ESMTPS id 0168AC21C5D\n\tfor ; Wed, 22 Nov 2017 09:08:47 +0000 (UTC)","from chenjh?rock-chips.com (unknown [192.168.167.139])\n\tby regular1.263xmail.com (Postfix) with ESMTP id 499419158;\n\tWed, 22 Nov 2017 17:08:41 +0800 (CST)","from [172.16.12.76] (localhost [127.0.0.1])\n\tby smtp.263.net (Postfix) with ESMTPA id 1ED6B815;\n\tWed, 22 Nov 2017 17:08:33 +0800 (CST)","from [172.16.12.76] (unknown [58.22.7.114])\n\tby smtp.263.net (Postfix) whith ESMTP id 7464UOCKF;\n\tWed, 22 Nov 2017 17:08:40 +0800 (CST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.6 required=5.0 tests=KHOP_BIG_TO_CC,\n\tRCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0","X-263anti-spam":"KSV:0;","X-MAIL-GRAY":"0","X-MAIL-DELIVERY":"1","X-KSVirus-check":"0","X-ABS-CHECKED":"4","X-RL-SENDER":"chenjh@rock-chips.com","X-FST-TO":"maxime.ripard@free-electrons.com","X-SENDER-IP":"58.22.7.114","X-LOGIN-NAME":"chenjh@rock-chips.com","X-UNIQUE-TAG":"","X-ATTACHMENT-NUM":"0","X-SENDER":"chenjh@rock-chips.com","X-DNS-TYPE":"0","To":"\"Andrew F. Davis\" , =?utf-8?q?Heiko_St=C3=BCbner?=\n\t, Kever Yang ","References":"<1504664087-26473-1-git-send-email-kever.yang@rock-chips.com>\n\t<4460193.XjJsJKMKHF@diego>\n\t<3a9eb658-8504-fbd8-75ff-e21e574e5593@ti.com>","From":"Joseph Chen ","Message-ID":"","Date":"Wed, 22 Nov 2017 17:10:19 +0800","User-Agent":"Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<3a9eb658-8504-fbd8-75ff-e21e574e5593@ti.com>","X-Mailman-Approved-At":"Wed, 22 Nov 2017 11:02:02 +0000","Cc":"u-boot@lists.denx.de, Alexander Graf ,\n\tStefan Agner ,\n\tAlexandru Gagniuc ,\n\tJagan Teki , \n\tvagrant@debian.org, Jacob Chen ,\n\tAndy Yan ,\n\tMaxime Ripard ","Subject":"Re: [U-Boot] [PATCH 00/10] rockchip: add tpl and OPTEE support for\n\trk3229","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=\"utf-8\"; Format=\"flowed\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1808610,"web_url":"http://patchwork.ozlabs.org/comment/1808610/","msgid":"<14828669.2QrqUhyY6C@phil>","list_archive_url":null,"date":"2017-11-22T10:00:12","subject":"Re: [U-Boot] [PATCH 00/10] rockchip: add tpl and OPTEE support for\n\trk3229","submitter":{"id":10645,"url":"http://patchwork.ozlabs.org/api/people/10645/","name":"Heiko Stuebner","email":"heiko@sntech.de"},"content":"Am Dienstag, 21. November 2017, 09:43:57 CET schrieb Andrew F. Davis:\n> On 11/20/2017 03:25 PM, Heiko Stübner wrote:\n> > Hi Kever,\n> > \n> > Am Mittwoch, 6. September 2017, 10:14:27 CET schrieb Kever Yang:\n> >> Add some generic options for TPL support for arm 32bit, and then\n> >> and TPL support for rk3229(cortex-A7), and then add OPTEE support\n> >> in SPL.\n> > \n> > I was now finally able to test this series and I'm getting mixed results.\n> > I was following the instructions in the evb-rk3229 README file.\n> > \n> > \n> > On the uboot side it seems to work nicely when applied against 2017.09.\n> > \n> > But when I try to rebase it on top of the next branch of u-boot-rockchip\n> > I end up with the TPL claiming a \"Missing DTB\", so it looks like it needs\n> > a respin to follow the recent changes.\n> > \n> > On the optee-side I also seem to do something wrong or so.\n> > When using the binaries from the rkbin github repository I end up with\n> > [0] and [1].\n> > When compiling the most-recent optee it fails with [2].\n> > \n> > With some intermediate optee or the one from Tony Xie's repository\n> > it compiles and uboot seems to start, but then fails when the kernel tries\n> > to bring up the secondary cpus [3]. And interestingly while it seems to go\n> > through optee, I don't see any optee-messages.\n> > \n> > If you could point me into the right direction, I would be very grateful :-)\n> > \n> > \n> > Thanks\n> > Heiko\n> > \n> > \n> > [0]\n> > TPL Inittimer init done\n> > Returning to boot ROM...\n> > \n> > U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\n> > Trying to boot from MMC1\n> > INF TEE-CORE:init_primary_helper:319: Initializing (1.0.1-65-gf1567d3-dev #22 Fri Mar 24 06:16:54 UTC 2017 arm)\n> > INF TEE-CORE:init_primary_helper:320: Release version: 1.9\n> > INF TEE-CORE:init_teecore:79: teecore inits done\n> > [hangs here]\n> > \n> > [1]\n> > TPL Inittimer init done\n> > Returning to boot ROM...\n> > \n> > U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\n> > Trying to boot from MMC1\n> > INF [0x0] TEE-CORE:init_primary_helper:366: Initializing (1.1.0-120-gb4aded8-dev #3 Wed Dec 28 01:56:52 UTC 2016 arm)\n> > INF [0x0] TEE-CORE:init_primary_helper:367: Release version: 1.6\n> > INF [0x0] TEE-CORE:init_teecore:83: teecore inits done\n> > [hangs here]\n> > \n> > [2]\n> > make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x\n> > CHK out/arm-plat-rockchip/conf.mk\n> > UPD out/arm-plat-rockchip/conf.mk\n> > CHK out/arm-plat-rockchip/include/generated/conf.h\n> > UPD out/arm-plat-rockchip/include/generated/conf.h\n> > CHK out/arm-plat-rockchip/core/include/generated/asm-defines.h\n> > make: *** No rule, to create „core/include/tee/tee_cryp_provider.h“, needed by\n> > „out/arm-plat-rockchip/core/arch/arm/kernel/user_ta.o“.\n> > \n> \n> make clean; git clean -fx..; then try again\n> \n> > [3]\n> > TPL Inittimer init done\n> > Returning to boot ROM...\n> > \n> > U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\n> > Trying to boot from MMC1\n> > \n> > \n> > U-Boot 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 21:29:43 +0100)\n> > \n> > Model: Nexbox A95X R1\n> > DRAM: 1022 MiB\n> > [...]\n> > Starting kernel ...\n> > \n> > [ 0.000000] Booting Linux on physical CPU 0xf00\n> > [ 0.000000] Linux version 4.14.0-13997-g55102e6ed32a-dirty (hstuebner@phil) (gcc version 7.2.0 (Debian 7.2.0-11)) #437 SMP Mon Nov 20 11:33:35 CET 2017\n> > [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d\n> > [ 0.000000] CPU: div instructions available: patching division code\n> > [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache\n> > [ 0.000000] OF: fdt: Machine model: Nexbox A95X R1\n> > [ 0.000000] earlycon: uart8250 at MMIO32 0x11030000 (options '')\n> > [ 0.000000] bootconsole [uart8250] enabled\n> > [ 0.000000] Memory policy: Data cache writealloc\n> > [ 0.000000] efi: Getting EFI parameters from FDT:\n> > [ 0.000000] efi: UEFI not found.\n> > [ 0.000000] cma: Reserved 64 MiB at 0x9c000000\n> > [ 0.000000] psci: probing for conduit method from DT.\n> > [ 0.000000] psci: PSCIv1.0 detected in firmware.\n> > [ 0.000000] psci: Using standard PSCI v0.2 function IDs\n> > [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.\n> > [ 0.000000] random: fast init done\n> > [ 0.000000] percpu: Embedded 17 pages/cpu @ef7a4000 s39116 r8192 d22324 u69632\n> > [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260096\n> > [...]\n> > [ 0.000000] CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00\n> > [ 0.000000] Setting up static identity map for 0x60300000 - 0x603000a0\n> > [ 0.000000] Hierarchical SRCU implementation.\n> > [ 0.000000] EFI services will not be available.\n> > [ 0.000000] smp: Bringing up secondary CPUs ...\n> > [hangs here]\n> > \n> \n> I've been here plenty of times when brining up OP-TEE on TI platforms,\n> for me it's OP-TEE parking the secondary CPUs in a bad way. I'm not sure\n> about the Rockchip arch, are the extra cores brought up with PSCI?\n\nYep, the rk3229 is the first 32bit Rockchip soc using PSCI (implemented\nin OP-TEE). As Joseph indicated in the other mail, it might be a timer-issue\nafter all.\n\n> Anyway can you get JTAG on this device, see where the other cores are stuck.\n\nThere is no easy JTAG on TV box I'm using right now, as there exists no real\nwidely available dev-board for the rk3229 right now.\n\nSo I'm still hoping for some insights from Kever though ;-)","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3yhfgw6dmtz9s7g\n\tfor ;\n\tWed, 22 Nov 2017 22:03:08 +1100 (AEDT)","by lists.denx.de (Postfix, from userid 105)\n\tid 7F65FC21E05; Wed, 22 Nov 2017 11:02:28 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 623CEC21DB5;\n\tWed, 22 Nov 2017 11:02:05 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid D48ACC21C4B; Wed, 22 Nov 2017 10:00:22 +0000 (UTC)","from gloria.sntech.de (gloria.sntech.de [95.129.55.99])\n\tby lists.denx.de (Postfix) with ESMTPS id 84F06C21C34\n\tfor ; Wed, 22 Nov 2017 10:00:22 +0000 (UTC)","from ip923422a5.dynamic.kabel-deutschland.de ([146.52.34.165]\n\thelo=phil.localnet) by gloria.sntech.de with esmtpsa\n\t(TLS1.1:DHE_RSA_AES_256_CBC_SHA1:256)\n\t(Exim 4.80) (envelope-from )\n\tid 1eHRpF-00073u-O7; Wed, 22 Nov 2017 11:00:13 +0100"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC\n\tautolearn=unavailable autolearn_force=no version=3.4.0","From":"Heiko Stuebner ","To":"\"Andrew F. Davis\" ","Date":"Wed, 22 Nov 2017 11:00:12 +0100","Message-ID":"<14828669.2QrqUhyY6C@phil>","User-Agent":"KMail/5.2.3 (Linux/4.13.0-1-amd64; KDE/5.37.0; x86_64; ; )","In-Reply-To":"<3a9eb658-8504-fbd8-75ff-e21e574e5593@ti.com>","References":"<1504664087-26473-1-git-send-email-kever.yang@rock-chips.com>\n\t<4460193.XjJsJKMKHF@diego>\n\t<3a9eb658-8504-fbd8-75ff-e21e574e5593@ti.com>","MIME-Version":"1.0","X-Mailman-Approved-At":"Wed, 22 Nov 2017 11:02:02 +0000","Cc":"u-boot@lists.denx.de, Alexander Graf ,\n\tJoseph Chen ,\n\tStefan Agner , \n\tAlexandru Gagniuc ,\n\tJagan Teki , \n\tvagrant@debian.org, Jacob Chen ,\n\tAndy Yan ,\n\tMaxime Ripard ","Subject":"Re: [U-Boot] [PATCH 00/10] rockchip: add tpl and OPTEE support for\n\trk3229","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1808611,"web_url":"http://patchwork.ozlabs.org/comment/1808611/","msgid":"<5547624.h4OH9bvIe4@phil>","list_archive_url":null,"date":"2017-11-22T10:01:19","subject":"Re: [U-Boot] [PATCH 00/10] rockchip: add tpl and OPTEE support for\n\trk3229","submitter":{"id":10645,"url":"http://patchwork.ozlabs.org/api/people/10645/","name":"Heiko Stuebner","email":"heiko@sntech.de"},"content":"Am Mittwoch, 22. November 2017, 17:10:19 CET schrieb Joseph Chen:\n> \n> 在 2017/11/21 23:43, Andrew F. Davis 写道:\n> > On 11/20/2017 03:25 PM, Heiko Stübner wrote:\n> >> Hi Kever,\n> >>\n> >> Am Mittwoch, 6. September 2017, 10:14:27 CET schrieb Kever Yang:\n> >>> Add some generic options for TPL support for arm 32bit, and then\n> >>> and TPL support for rk3229(cortex-A7), and then add OPTEE support\n> >>> in SPL.\n> >> I was now finally able to test this series and I'm getting mixed results.\n> >> I was following the instructions in the evb-rk3229 README file.\n> >>\n> >>\n> >> On the uboot side it seems to work nicely when applied against 2017.09.\n> >>\n> >> But when I try to rebase it on top of the next branch of u-boot-rockchip\n> >> I end up with the TPL claiming a \"Missing DTB\", so it looks like it needs\n> >> a respin to follow the recent changes.\n> >>\n> >> On the optee-side I also seem to do something wrong or so.\n> >> When using the binaries from the rkbin github repository I end up with\n> >> [0] and [1].\n> >> When compiling the most-recent optee it fails with [2].\n> >>\n> >> With some intermediate optee or the one from Tony Xie's repository\n> >> it compiles and uboot seems to start, but then fails when the kernel tries\n> >> to bring up the secondary cpus [3]. And interestingly while it seems to go\n> >> through optee, I don't see any optee-messages.\n> >>\n> >> If you could point me into the right direction, I would be very grateful :-)\n> >>\n> >>\n> >> Thanks\n> >> Heiko\n> >>\n> >>\n> >> [0]\n> >> TPL Inittimer init done\n> >> Returning to boot ROM...\n> >>\n> >> U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\n> >> Trying to boot from MMC1\n> >> INF TEE-CORE:init_primary_helper:319: Initializing (1.0.1-65-gf1567d3-dev #22 Fri Mar 24 06:16:54 UTC 2017 arm)\n> >> INF TEE-CORE:init_primary_helper:320: Release version: 1.9\n> >> INF TEE-CORE:init_teecore:79: teecore inits done\n> >> [hangs here]\n> >>\n> >> [1]\n> >> TPL Inittimer init done\n> >> Returning to boot ROM...\n> >>\n> >> U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\n> >> Trying to boot from MMC1\n> >> INF [0x0] TEE-CORE:init_primary_helper:366: Initializing (1.1.0-120-gb4aded8-dev #3 Wed Dec 28 01:56:52 UTC 2016 arm)\n> >> INF [0x0] TEE-CORE:init_primary_helper:367: Release version: 1.6\n> >> INF [0x0] TEE-CORE:init_teecore:83: teecore inits done\n> >> [hangs here]\n> >>\n> >> [2]\n> >> make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x\n> >> CHK out/arm-plat-rockchip/conf.mk\n> >> UPD out/arm-plat-rockchip/conf.mk\n> >> CHK out/arm-plat-rockchip/include/generated/conf.h\n> >> UPD out/arm-plat-rockchip/include/generated/conf.h\n> >> CHK out/arm-plat-rockchip/core/include/generated/asm-defines.h\n> >> make: *** No rule, to create „core/include/tee/tee_cryp_provider.h“, needed by\n> >> „out/arm-plat-rockchip/core/arch/arm/kernel/user_ta.o“.\n> >>\n> > make clean; git clean -fx..; then try again\n> >\n> >> [3]\n> >> TPL Inittimer init done\n> >> Returning to boot ROM...\n> >>\n> >> U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\n> >> Trying to boot from MMC1\n> >>\n> >>\n> >> U-Boot 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 21:29:43 +0100)\n> >>\n> >> Model: Nexbox A95X R1\n> >> DRAM: 1022 MiB\n> >> [...]\n> >> Starting kernel ...\n> >>\n> >> [ 0.000000] Booting Linux on physical CPU 0xf00\n> >> [ 0.000000] Linux version 4.14.0-13997-g55102e6ed32a-dirty (hstuebner@phil) (gcc version 7.2.0 (Debian 7.2.0-11)) #437 SMP Mon Nov 20 11:33:35 CET 2017\n> >> [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d\n> >> [ 0.000000] CPU: div instructions available: patching division code\n> >> [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache\n> >> [ 0.000000] OF: fdt: Machine model: Nexbox A95X R1\n> >> [ 0.000000] earlycon: uart8250 at MMIO32 0x11030000 (options '')\n> >> [ 0.000000] bootconsole [uart8250] enabled\n> >> [ 0.000000] Memory policy: Data cache writealloc\n> >> [ 0.000000] efi: Getting EFI parameters from FDT:\n> >> [ 0.000000] efi: UEFI not found.\n> >> [ 0.000000] cma: Reserved 64 MiB at 0x9c000000\n> >> [ 0.000000] psci: probing for conduit method from DT.\n> >> [ 0.000000] psci: PSCIv1.0 detected in firmware.\n> >> [ 0.000000] psci: Using standard PSCI v0.2 function IDs\n> >> [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.\n> >> [ 0.000000] random: fast init done\n> >> [ 0.000000] percpu: Embedded 17 pages/cpu @ef7a4000 s39116 r8192 d22324 u69632\n> >> [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260096\n> >> [...]\n> >> [ 0.000000] CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00\n> >> [ 0.000000] Setting up static identity map for 0x60300000 - 0x603000a0\n> >> [ 0.000000] Hierarchical SRCU implementation.\n> >> [ 0.000000] EFI services will not be available.\n> >> [ 0.000000] smp: Bringing up secondary CPUs ...\n> >> [hangs here]\n> >>\n> > I've been here plenty of times when brining up OP-TEE on TI platforms,\n> > for me it's OP-TEE parking the secondary CPUs in a bad way. I'm not sure\n> > about the Rockchip arch, are the extra cores brought up with PSCI?\n> > Anyway can you get JTAG on this device, see where the other cores are stuck.\n> >\n> \n> If your OP-TEE is from Tony Xie's repository, I think the reason maybe \n> that cntfrq register is not been initialized. core0 stucks at udelay() \n> in the OP-TEE when it tries to bring up core1. So can you try to \n> initialize cntfrq as 24000000 in the SPL/TPL ? maybe it helps.\n\nThat might be a good lead, as yesterday evening I noticed similar issues\nwith the architected timer when starting the linux kernel, which hangs\nat some point and only manages to continue once I disable the arch-timer\nin the devicetree.\n\nI tried Tony's repository directly and also the official op-tee where his\npatches got merged to.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3yhfhc2QbXz9s7f\n\tfor ;\n\tWed, 22 Nov 2017 22:03:44 +1100 (AEDT)","by lists.denx.de (Postfix, from userid 105)\n\tid 0B1E8C21E09; Wed, 22 Nov 2017 11:02:50 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id AE43DC21E14;\n\tWed, 22 Nov 2017 11:02:06 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid D9A0FC21C4B; Wed, 22 Nov 2017 10:01:24 +0000 (UTC)","from gloria.sntech.de (gloria.sntech.de [95.129.55.99])\n\tby lists.denx.de (Postfix) with ESMTPS id 9DA0EC21C34\n\tfor ; Wed, 22 Nov 2017 10:01:24 +0000 (UTC)","from ip923422a5.dynamic.kabel-deutschland.de ([146.52.34.165]\n\thelo=phil.localnet) by gloria.sntech.de with esmtpsa\n\t(TLS1.1:DHE_RSA_AES_256_CBC_SHA1:256)\n\t(Exim 4.80) (envelope-from )\n\tid 1eHRqK-00074t-Ev; Wed, 22 Nov 2017 11:01:20 +0100"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0","From":"Heiko Stuebner ","To":"Joseph Chen ","Date":"Wed, 22 Nov 2017 11:01:19 +0100","Message-ID":"<5547624.h4OH9bvIe4@phil>","User-Agent":"KMail/5.2.3 (Linux/4.13.0-1-amd64; KDE/5.37.0; x86_64; ; )","In-Reply-To":"","References":"<1504664087-26473-1-git-send-email-kever.yang@rock-chips.com>\n\t<3a9eb658-8504-fbd8-75ff-e21e574e5593@ti.com>\n\t","MIME-Version":"1.0","X-Mailman-Approved-At":"Wed, 22 Nov 2017 11:02:02 +0000","Cc":"u-boot@lists.denx.de, Alexander Graf ,\n\tStefan Agner ,\n\tAlexandru Gagniuc ,\n\tJagan Teki , \n\tvagrant@debian.org, Jacob Chen ,\n\tAndy Yan ,\n\tMaxime Ripard ","Subject":"Re: [U-Boot] [PATCH 00/10] rockchip: add tpl and OPTEE support for\n\trk3229","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1809264,"web_url":"http://patchwork.ozlabs.org/comment/1809264/","msgid":"<2a394dc8-e5e6-48c4-487f-6e21bd0fd6ed@rock-chips.com>","list_archive_url":null,"date":"2017-11-23T00:35:28","subject":"Re: [U-Boot] [PATCH 00/10] rockchip: add tpl and OPTEE support for\n\trk3229","submitter":{"id":64532,"url":"http://patchwork.ozlabs.org/api/people/64532/","name":"Kever Yang","email":"kever.yang@rock-chips.com"},"content":"Heiko,\n\n I test with Rockchip op-tee from rkbin and it works fine, let me \ntest with\n\nupstream op-tee again and get back to you.\n\n\nThanks,\n- Kever\nOn 11/22/2017 06:00 PM, Heiko Stuebner wrote:\n> Am Dienstag, 21. November 2017, 09:43:57 CET schrieb Andrew F. Davis:\n>> On 11/20/2017 03:25 PM, Heiko Stübner wrote:\n>>> Hi Kever,\n>>>\n>>> Am Mittwoch, 6. September 2017, 10:14:27 CET schrieb Kever Yang:\n>>>> Add some generic options for TPL support for arm 32bit, and then\n>>>> and TPL support for rk3229(cortex-A7), and then add OPTEE support\n>>>> in SPL.\n>>> I was now finally able to test this series and I'm getting mixed results.\n>>> I was following the instructions in the evb-rk3229 README file.\n>>>\n>>>\n>>> On the uboot side it seems to work nicely when applied against 2017.09.\n>>>\n>>> But when I try to rebase it on top of the next branch of u-boot-rockchip\n>>> I end up with the TPL claiming a \"Missing DTB\", so it looks like it needs\n>>> a respin to follow the recent changes.\n>>>\n>>> On the optee-side I also seem to do something wrong or so.\n>>> When using the binaries from the rkbin github repository I end up with\n>>> [0] and [1].\n>>> When compiling the most-recent optee it fails with [2].\n>>>\n>>> With some intermediate optee or the one from Tony Xie's repository\n>>> it compiles and uboot seems to start, but then fails when the kernel tries\n>>> to bring up the secondary cpus [3]. And interestingly while it seems to go\n>>> through optee, I don't see any optee-messages.\n>>>\n>>> If you could point me into the right direction, I would be very grateful :-)\n>>>\n>>>\n>>> Thanks\n>>> Heiko\n>>>\n>>>\n>>> [0]\n>>> TPL Inittimer init done\n>>> Returning to boot ROM...\n>>>\n>>> U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\n>>> Trying to boot from MMC1\n>>> INF TEE-CORE:init_primary_helper:319: Initializing (1.0.1-65-gf1567d3-dev #22 Fri Mar 24 06:16:54 UTC 2017 arm)\n>>> INF TEE-CORE:init_primary_helper:320: Release version: 1.9\n>>> INF TEE-CORE:init_teecore:79: teecore inits done\n>>> [hangs here]\n>>>\n>>> [1]\n>>> TPL Inittimer init done\n>>> Returning to boot ROM...\n>>>\n>>> U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\n>>> Trying to boot from MMC1\n>>> INF [0x0] TEE-CORE:init_primary_helper:366: Initializing (1.1.0-120-gb4aded8-dev #3 Wed Dec 28 01:56:52 UTC 2016 arm)\n>>> INF [0x0] TEE-CORE:init_primary_helper:367: Release version: 1.6\n>>> INF [0x0] TEE-CORE:init_teecore:83: teecore inits done\n>>> [hangs here]\n>>>\n>>> [2]\n>>> make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x\n>>> CHK out/arm-plat-rockchip/conf.mk\n>>> UPD out/arm-plat-rockchip/conf.mk\n>>> CHK out/arm-plat-rockchip/include/generated/conf.h\n>>> UPD out/arm-plat-rockchip/include/generated/conf.h\n>>> CHK out/arm-plat-rockchip/core/include/generated/asm-defines.h\n>>> make: *** No rule, to create „core/include/tee/tee_cryp_provider.h“, needed by\n>>> „out/arm-plat-rockchip/core/arch/arm/kernel/user_ta.o“.\n>>>\n>> make clean; git clean -fx..; then try again\n>>\n>>> [3]\n>>> TPL Inittimer init done\n>>> Returning to boot ROM...\n>>>\n>>> U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\n>>> Trying to boot from MMC1\n>>>\n>>>\n>>> U-Boot 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 21:29:43 +0100)\n>>>\n>>> Model: Nexbox A95X R1\n>>> DRAM: 1022 MiB\n>>> [...]\n>>> Starting kernel ...\n>>>\n>>> [ 0.000000] Booting Linux on physical CPU 0xf00\n>>> [ 0.000000] Linux version 4.14.0-13997-g55102e6ed32a-dirty (hstuebner@phil) (gcc version 7.2.0 (Debian 7.2.0-11)) #437 SMP Mon Nov 20 11:33:35 CET 2017\n>>> [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d\n>>> [ 0.000000] CPU: div instructions available: patching division code\n>>> [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache\n>>> [ 0.000000] OF: fdt: Machine model: Nexbox A95X R1\n>>> [ 0.000000] earlycon: uart8250 at MMIO32 0x11030000 (options '')\n>>> [ 0.000000] bootconsole [uart8250] enabled\n>>> [ 0.000000] Memory policy: Data cache writealloc\n>>> [ 0.000000] efi: Getting EFI parameters from FDT:\n>>> [ 0.000000] efi: UEFI not found.\n>>> [ 0.000000] cma: Reserved 64 MiB at 0x9c000000\n>>> [ 0.000000] psci: probing for conduit method from DT.\n>>> [ 0.000000] psci: PSCIv1.0 detected in firmware.\n>>> [ 0.000000] psci: Using standard PSCI v0.2 function IDs\n>>> [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.\n>>> [ 0.000000] random: fast init done\n>>> [ 0.000000] percpu: Embedded 17 pages/cpu @ef7a4000 s39116 r8192 d22324 u69632\n>>> [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260096\n>>> [...]\n>>> [ 0.000000] CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00\n>>> [ 0.000000] Setting up static identity map for 0x60300000 - 0x603000a0\n>>> [ 0.000000] Hierarchical SRCU implementation.\n>>> [ 0.000000] EFI services will not be available.\n>>> [ 0.000000] smp: Bringing up secondary CPUs ...\n>>> [hangs here]\n>>>\n>> I've been here plenty of times when brining up OP-TEE on TI platforms,\n>> for me it's OP-TEE parking the secondary CPUs in a bad way. I'm not sure\n>> about the Rockchip arch, are the extra cores brought up with PSCI?\n> Yep, the rk3229 is the first 32bit Rockchip soc using PSCI (implemented\n> in OP-TEE). As Joseph indicated in the other mail, it might be a timer-issue\n> after all.\n>\n>> Anyway can you get JTAG on this device, see where the other cores are stuck.\n> There is no easy JTAG on TV box I'm using right now, as there exists no real\n> widely available dev-board for the rk3229 right now.\n>\n> So I'm still hoping for some insights from Kever though ;-)\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3yjKcf3T0wz9sNd\n\tfor ;\n\tFri, 24 Nov 2017 00:17:38 +1100 (AEDT)","by lists.denx.de (Postfix, from userid 105)\n\tid 2E528C21E57; Thu, 23 Nov 2017 13:17:33 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id F15C5C21DE9;\n\tThu, 23 Nov 2017 13:17:29 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 80A56C21DA2; Thu, 23 Nov 2017 00:35:48 +0000 (UTC)","from regular1.263xmail.com (regular1.263xmail.com [211.150.99.136])\n\tby lists.denx.de (Postfix) with ESMTPS id 103CDC21DA6\n\tfor ; Thu, 23 Nov 2017 00:35:45 +0000 (UTC)","from kever.yang?rock-chips.com (unknown [192.168.165.105])\n\tby regular1.263xmail.com (Postfix) with ESMTP id 03CEB35;\n\tThu, 23 Nov 2017 08:35:38 +0800 (CST)","from [192.168.60.65] (localhost [127.0.0.1])\n\tby smtp.263.net (Postfix) with ESMTPA id 987F3308;\n\tThu, 23 Nov 2017 08:35:29 +0800 (CST)","from [192.168.60.65] (unknown [103.29.142.67])\n\tby smtp.263.net (Postfix) whith ESMTP id 83430JZ9HY;\n\tThu, 23 Nov 2017 08:35:36 +0800 (CST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-263anti-spam":"KSV:0;","X-MAIL-GRAY":"0","X-MAIL-DELIVERY":"1","X-KSVirus-check":"0","X-ABS-CHECKED":"4","X-RL-SENDER":"kever.yang@rock-chips.com","X-FST-TO":"eddie.cai.linux@gmail.com","X-SENDER-IP":"103.29.142.67","X-LOGIN-NAME":"kever.yang@rock-chips.com","X-UNIQUE-TAG":"<623f3905be0c7e77663acd6dc60a6502>","X-ATTACHMENT-NUM":"0","X-SENDER":"yk@rock-chips.com","X-DNS-TYPE":"0","To":"Heiko Stuebner , \"Andrew F. Davis\" ","References":"<1504664087-26473-1-git-send-email-kever.yang@rock-chips.com>\n\t<4460193.XjJsJKMKHF@diego>\n\t<3a9eb658-8504-fbd8-75ff-e21e574e5593@ti.com>\n\t<14828669.2QrqUhyY6C@phil>","From":"Kever Yang ","Message-ID":"<2a394dc8-e5e6-48c4-487f-6e21bd0fd6ed@rock-chips.com>","Date":"Thu, 23 Nov 2017 08:35:28 +0800","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.8.0","MIME-Version":"1.0","In-Reply-To":"<14828669.2QrqUhyY6C@phil>","X-Mailman-Approved-At":"Thu, 23 Nov 2017 13:17:28 +0000","Cc":"u-boot@lists.denx.de, Alexander Graf ,\n\tJoseph Chen ,\n\tStefan Agner , \n\tAlexandru Gagniuc ,\n\tJagan Teki , \n\tvagrant@debian.org, Jacob Chen ,\n\tAndy Yan ","Subject":"Re: [U-Boot] [PATCH 00/10] rockchip: add tpl and OPTEE support for\n\trk3229","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=\"utf-8\"; Format=\"flowed\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1823047,"web_url":"http://patchwork.ozlabs.org/comment/1823047/","msgid":"<8da9855e-bcd7-56e8-d26e-2ba96c653bba@rock-chips.com>","list_archive_url":null,"date":"2017-12-15T10:00:32","subject":"Re: [U-Boot] [PATCH 00/10] rockchip: add tpl and OPTEE support for\n\trk3229","submitter":{"id":64532,"url":"http://patchwork.ozlabs.org/api/people/64532/","name":"Kever Yang","email":"kever.yang@rock-chips.com"},"content":"Heiko,\n\n\nOn 11/21/2017 05:25 AM, Heiko Stübner wrote:\n> Hi Kever,\n>\n> Am Mittwoch, 6. September 2017, 10:14:27 CET schrieb Kever Yang:\n>> Add some generic options for TPL support for arm 32bit, and then\n>> and TPL support for rk3229(cortex-A7), and then add OPTEE support\n>> in SPL.\n> I was now finally able to test this series and I'm getting mixed results.\n> I was following the instructions in the evb-rk3229 README file.\n>\n>\n> On the uboot side it seems to work nicely when applied against 2017.09.\n>\n> But when I try to rebase it on top of the next branch of u-boot-rockchip\n> I end up with the TPL claiming a \"Missing DTB\", so it looks like it needs\n> a respin to follow the recent changes.\n>\n> On the optee-side I also seem to do something wrong or so.\n> When using the binaries from the rkbin github repository I end up with\n> [0] and [1].\nthe U-Boot proper update the text_base to 0x61000000 instead\nof 0x60000000, but I guess the optee rkbin using fixed 0x60000000;\n\n> When compiling the most-recent optee it fails with [2].\n\nI met the same problem, remove the 'out' folder and make again, it will \nsuccess.\n> With some intermediate optee or the one from Tony Xie's repository\n> it compiles and uboot seems to start, but then fails when the kernel tries\n> to bring up the secondary cpus [3]. And interestingly while it seems to go\n> through optee, I don't see any optee-messages.\n>\n> If you could point me into the right direction, I would be very grateful :-)\n>\n>\n> Thanks\n> Heiko\n>\n>\n> [0]\n> TPL Inittimer init done\n> Returning to boot ROM...\n>\n> U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\n> Trying to boot from MMC1\n> INF TEE-CORE:init_primary_helper:319: Initializing (1.0.1-65-gf1567d3-dev #22 Fri Mar 24 06:16:54 UTC 2017 arm)\n> INF TEE-CORE:init_primary_helper:320: Release version: 1.9\n> INF TEE-CORE:init_teecore:79: teecore inits done\n> [hangs here]\n>\n> [1]\n> TPL Inittimer init done\n> Returning to boot ROM...\n>\n> U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\n> Trying to boot from MMC1\n> INF [0x0] TEE-CORE:init_primary_helper:366: Initializing (1.1.0-120-gb4aded8-dev #3 Wed Dec 28 01:56:52 UTC 2016 arm)\n> INF [0x0] TEE-CORE:init_primary_helper:367: Release version: 1.6\n> INF [0x0] TEE-CORE:init_teecore:83: teecore inits done\n> [hangs here]\n>\n> [2]\n> make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x\n> CHK out/arm-plat-rockchip/conf.mk\n> UPD out/arm-plat-rockchip/conf.mk\n> CHK out/arm-plat-rockchip/include/generated/conf.h\n> UPD out/arm-plat-rockchip/include/generated/conf.h\n> CHK out/arm-plat-rockchip/core/include/generated/asm-defines.h\n> make: *** No rule, to create „core/include/tee/tee_cryp_provider.h“, needed by\n> „out/arm-plat-rockchip/core/arch/arm/kernel/user_ta.o“.\n>\n> [3]\n> TPL Inittimer init done\n> Returning to boot ROM...\n>\n> U-Boot SPL 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 19:24:42)\n> Trying to boot from MMC1\n>\n>\n> U-Boot 2017.09-rc4-00031-gf82145695e-dirty (Nov 20 2017 - 21:29:43 +0100)\n>\n> Model: Nexbox A95X R1\n> DRAM: 1022 MiB\n> [...]\n> Starting kernel ...\n>\n> [ 0.000000] Booting Linux on physical CPU 0xf00\n> [ 0.000000] Linux version 4.14.0-13997-g55102e6ed32a-dirty (hstuebner@phil) (gcc version 7.2.0 (Debian 7.2.0-11)) #437 SMP Mon Nov 20 11:33:35 CET 2017\n> [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d\n> [ 0.000000] CPU: div instructions available: patching division code\n> [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache\n> [ 0.000000] OF: fdt: Machine model: Nexbox A95X R1\n> [ 0.000000] earlycon: uart8250 at MMIO32 0x11030000 (options '')\n> [ 0.000000] bootconsole [uart8250] enabled\n> [ 0.000000] Memory policy: Data cache writealloc\n> [ 0.000000] efi: Getting EFI parameters from FDT:\n> [ 0.000000] efi: UEFI not found.\n> [ 0.000000] cma: Reserved 64 MiB at 0x9c000000\n> [ 0.000000] psci: probing for conduit method from DT.\n> [ 0.000000] psci: PSCIv1.0 detected in firmware.\n> [ 0.000000] psci: Using standard PSCI v0.2 function IDs\n> [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.\n> [ 0.000000] random: fast init done\n> [ 0.000000] percpu: Embedded 17 pages/cpu @ef7a4000 s39116 r8192 d22324 u69632\n> [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 260096\n> [...]\n> [ 0.000000] CPU0: thread -1, cpu 0, socket 15, mpidr 80000f00\n> [ 0.000000] Setting up static identity map for 0x60300000 - 0x603000a0\n> [ 0.000000] Hierarchical SRCU implementation.\n> [ 0.000000] EFI services will not be available.\n> [ 0.000000] smp: Bringing up secondary CPUs ...\n> [hangs here]\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3yypBX1JCnz9t2W\n\tfor ;\n\tFri, 15 Dec 2017 22:30:10 +1100 (AEDT)","by lists.denx.de (Postfix, from userid 105)\n\tid 12F0CC21F1A; Fri, 15 Dec 2017 11:29:50 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id D998BC21E31;\n\tFri, 15 Dec 2017 11:29:46 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid EC66EC21E0E; Fri, 15 Dec 2017 10:01:07 +0000 (UTC)","from regular1.263xmail.com (regular1.263xmail.com [211.150.99.133])\n\tby lists.denx.de (Postfix) with ESMTPS id 36F23C21DB1\n\tfor ; Fri, 15 Dec 2017 10:01:06 +0000 (UTC)","from kever.yang?rock-chips.com (unknown [192.168.165.141])\n\tby regular1.263xmail.com (Postfix) with ESMTP id 109F59021;\n\tFri, 15 Dec 2017 18:01:01 +0800 (CST)","from [192.168.60.65] (localhost [127.0.0.1])\n\tby smtp.263.net (Postfix) with ESMTPA id 9E751416;\n\tFri, 15 Dec 2017 18:00:34 +0800 (CST)","from [192.168.60.65] (unknown [103.29.142.67])\n\tby smtp.263.net (Postfix) whith ESMTP id 72393SG8ZB;\n\tFri, 15 Dec 2017 18:00:57 +0800 (CST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC,\n\tRCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-263anti-spam":"KSV:0;","X-MAIL-GRAY":"0","X-MAIL-DELIVERY":"1","X-KSVirus-check":"0","X-ABS-CHECKED":"4","X-RL-SENDER":"kever.yang@rock-chips.com","X-FST-TO":"maxime.ripard@free-electrons.com","X-SENDER-IP":"103.29.142.67","X-LOGIN-NAME":"kever.yang@rock-chips.com","X-UNIQUE-TAG":"<70594041b6430af2c1321d8aadd01b15>","X-ATTACHMENT-NUM":"0","X-SENDER":"yk@rock-chips.com","X-DNS-TYPE":"0","To":"=?utf-8?q?Heiko_St=C3=BCbner?= ,\n\tJoseph Chen ","References":"<1504664087-26473-1-git-send-email-kever.yang@rock-chips.com>\n\t<4460193.XjJsJKMKHF@diego>","From":"Kever Yang ","Message-ID":"<8da9855e-bcd7-56e8-d26e-2ba96c653bba@rock-chips.com>","Date":"Fri, 15 Dec 2017 18:00:32 +0800","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.8.0","MIME-Version":"1.0","In-Reply-To":"<4460193.XjJsJKMKHF@diego>","X-Mailman-Approved-At":"Fri, 15 Dec 2017 11:29:45 +0000","Cc":"u-boot@lists.denx.de, Alexander Graf ,\n\tStefan Agner ,\n\tAlexandru Gagniuc ,\n\tJagan Teki , \n\tvagrant@debian.org, Jacob Chen ,\n\tAndy Yan ,\n\tMaxime Ripard ","Subject":"Re: [U-Boot] [PATCH 00/10] rockchip: add tpl and OPTEE support for\n\trk3229","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=\"utf-8\"; Format=\"flowed\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]