[{"id":1762740,"web_url":"http://patchwork.ozlabs.org/comment/1762740/","msgid":"","list_archive_url":null,"date":"2017-09-04T15:59:18","subject":"Re: [PATCH v2 02/29] asm-generic: add .data.rel.ro sections to\n\t__ro_after_init","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> When running in PIC mode, the compiler will emit const structures\n> containing runtime relocatable quantities into .data.rel.ro.* sections,\n> so that the linker can be smart about placing them together in a segment\n> that is read-write initially, and is remapped read-only afterwards. This\n> is exactly what __ro_after_init aims to provide, so move these sections\n> together.\n> \n> Acked-by: Arnd Bergmann \n> Signed-off-by: Ard Biesheuvel \n\nAcked-by: Nicolas Pitre \n\n> ---\n> include/asm-generic/vmlinux.lds.h | 2 +-\n> 1 file changed, 1 insertion(+), 1 deletion(-)\n> \n> diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h\n> index da0be9a8d1de..d16537b0b102 100644\n> --- a/include/asm-generic/vmlinux.lds.h\n> +++ b/include/asm-generic/vmlinux.lds.h\n> @@ -261,7 +261,7 @@\n> #ifndef RO_AFTER_INIT_DATA\n> #define RO_AFTER_INIT_DATA\t\t\t\t\t\t\\\n> \tVMLINUX_SYMBOL(__start_ro_after_init) = .;\t\t\t\\\n> -\t*(.data..ro_after_init)\t\t\t\t\t\t\\\n> +\t*(.data..ro_after_init .data.rel.ro.*)\t\t\t\t\\\n> \tVMLINUX_SYMBOL(__end_ro_after_init) = .;\n> #endif\n> \n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762742,"web_url":"http://patchwork.ozlabs.org/comment/1762742/","msgid":"","list_archive_url":null,"date":"2017-09-04T16:05:40","subject":"Re: [PATCH v2 03/29] ARM: assembler: introduce adr_l, ldr_l and\n\tstr_l macros","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> Like arm64, ARM supports position independent code sequences that\n> produce symbol references with a greater reach than the ordinary\n> adr/ldr instructions.\n> \n> Currently, we use open coded instruction sequences involving literals\n> and arithmetic operations. Instead, we can use movw/movt pairs on v7\n> CPUs, circumventing the D-cache entirely. For older CPUs, we can emit\n> the literal into a subsection, allowing it to be emitted out of line\n> while retaining the ability to perform arithmetic on label offsets.\n> \n> E.g., on pre-v7 CPUs, we can emit a PC-relative reference as follows:\n> \n> ldr , 222f\n> 111: add , , pc\n> .subsection 1\n> 222: .long - (111b + 8)\n> .previous\n> \n> This is allowed by the assembler because, unlike ordinary sections,\n> subsections are combined into a single section into the object file,\n> and so the label references are not true cross-section references that\n> are visible as relocations. Note that we could even do something like\n> \n> add , pc, #(222f - 111f) & ~0xfff\n> ldr , [, #(222f - 111f) & 0xfff]\n> 111: add , , pc\n> .subsection 1\n> 222: .long - (111b + 8)\n> .previous\n> \n> if it turns out that the 4 KB range of the ldr instruction is insufficient\n> to reach the literal in the subsection, although this is currently not a\n> problem (of the 98 objects built from .S files in a multi_v7_defconfig\n> build, only 11 have .text sections that are over 1 KB, and the largest one\n> [entry-armv.o] is 3308 bytes)\n> \n> Subsections have been available in binutils since 2004 at least, so\n> they should not cause any issues with older toolchains.\n> \n> So use the above to implement the macros mov_l, adr_l, ldr_l and str_l,\n> all of which will use movw/movt pairs on v7 and later CPUs, and use\n> PC-relative literals otherwise.\n> \n> Cc: Russell King \n> Signed-off-by: Ard Biesheuvel \n\nREviewed-by: Nicolas Pitre \n\n> ---\n> arch/arm/include/asm/assembler.h | 76 ++++++++++++++++++++\n> 1 file changed, 76 insertions(+)\n> \n> diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h\n> index ad301f107dd2..341e4ed1ef84 100644\n> --- a/arch/arm/include/asm/assembler.h\n> +++ b/arch/arm/include/asm/assembler.h\n> @@ -518,4 +518,80 @@ THUMB(\torr\t\\reg , \\reg , #PSR_T_BIT\t)\n> #endif\n> \t.endm\n> \n> +\t.macro\t\t__adldst_l, op, reg, sym, tmp\n> +\t.if\t\t__LINUX_ARM_ARCH__ < 7\n> +\tldr\t\t\\tmp, 111f\n> +\t.subsection\t1\n> +\t.align\t\t2\n> +111:\t.long\t\t\\sym - (222f + 8)\n> +\t.previous\n> +\t.else\n> +\t/*\n> +\t * In Thumb-2 builds, the PC bias depends on whether we are currently\n> +\t * emitting into a .arm or a .thumb section. So emit a nop and take\n> +\t * its size, so we can infer the execution mode and PC bias from it.\n> +\t */\n> + ARM(\t.set\t\t.Lnopsize, 4\t\t\t)\n> + THUMB(\t.pushsection\t\".discard.nop\", \"x\", %note\t)\n> + THUMB(\t111:\t\tnop\t\t\t\t)\n> + THUMB(\t.set\t\t.Lnopsize, . - 111b\t\t)\n> + THUMB(\t.popsection\t\t\t\t\t)\n> +\n> +\tmovw\t\t\\tmp, #:lower16:\\sym - (222f + 2 * .Lnopsize)\n> +\tmovt\t\t\\tmp, #:upper16:\\sym - (222f + 2 * .Lnopsize)\n> +\t.endif\n> +222:\n> +\t.ifc\t\t\\op, add\n> +\tadd\t\t\\reg, \\tmp, pc\n> +\t.elseif\t\t.Lnopsize == 2\t\t@ Thumb-2 mode\n> +\tadd\t\t\\tmp, \\tmp, pc\n> +\t\\op\t\t\\reg, [\\tmp]\n> +\t.else\n> +\t\\op\t\t\\reg, [pc, \\tmp]\n> +\t.endif\n> +\t.endm\n> +\n> +\t/*\n> +\t * mov_l - move a constant value or [relocated] address into a register\n> +\t */\n> +\t.macro\t\tmov_l, dst:req, imm:req\n> +\t.if\t\t__LINUX_ARM_ARCH__ < 7\n> +\tldr\t\t\\dst, =\\imm\n> +\t.else\n> +\tmovw\t\t\\dst, #:lower16:\\imm\n> +\tmovt\t\t\\dst, #:upper16:\\imm\n> +\t.endif\n> +\t.endm\n> +\n> +\t/*\n> +\t * adr_l - adr pseudo-op with unlimited range\n> +\t *\n> +\t * @dst: destination register\n> +\t * @sym: name of the symbol\n> +\t */\n> +\t.macro\t\tadr_l, dst:req, sym:req\n> +\t__adldst_l\tadd, \\dst, \\sym, \\dst\n> +\t.endm\n> +\n> +\t/*\n> +\t * ldr_l - ldr pseudo-op with unlimited range\n> +\t *\n> +\t * @dst: destination register\n> +\t * @sym: name of the symbol\n> +\t */\n> +\t.macro\t\tldr_l, dst:req, sym:req\n> +\t__adldst_l\tldr, \\dst, \\sym, \\dst\n> +\t.endm\n> +\n> +\t/*\n> +\t * str_l - str pseudo-op with unlimited range\n> +\t *\n> +\t * @src: source register\n> +\t * @sym: name of the symbol\n> +\t * @tmp: mandatory scratch register\n> +\t */\n> +\t.macro\t\tstr_l, src:req, sym:req, tmp:req\n> +\t__adldst_l\tstr, \\src, \\sym, \\tmp\n> +\t.endm\n> +\n> #endif /* __ASM_ASSEMBLER_H__ */\n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762744,"web_url":"http://patchwork.ozlabs.org/comment/1762744/","msgid":"","list_archive_url":null,"date":"2017-09-04T16:06:50","subject":"Re: [PATCH v2 04/29] ARM: head-common.S: use PC-relative insn\n\tsequence for __proc_info","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> Replace the open coded PC relative offset calculations with a pair\n> of adr_l invocations. This ensures these quantities are invariant\n> under runtime relocation.\n> \n> Cc: Russell King \n> Signed-off-by: Ard Biesheuvel \n\nAcked-by: Nicolas Pitre \n\n\n> ---\n> arch/arm/kernel/head-common.S | 22 ++++++--------------\n> 1 file changed, 6 insertions(+), 16 deletions(-)\n> \n> diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S\n> index 8733012d231f..06035488130c 100644\n> --- a/arch/arm/kernel/head-common.S\n> +++ b/arch/arm/kernel/head-common.S\n> @@ -150,11 +150,12 @@ ENDPROC(lookup_processor_type)\n> *\tr9 = cpuid (preserved)\n> */\n> __lookup_processor_type:\n> -\tadr\tr3, __lookup_processor_type_data\n> -\tldmia\tr3, {r4 - r6}\n> -\tsub\tr3, r3, r4\t\t\t@ get offset between virt&phys\n> -\tadd\tr5, r5, r3\t\t\t@ convert virt addresses to\n> -\tadd\tr6, r6, r3\t\t\t@ physical address space\n> +\t/*\n> +\t * Look in for information about the __proc_info\n> +\t * structure.\n> +\t */\n> +\tadr_l\tr5, __proc_info_begin\n> +\tadr_l\tr6, __proc_info_end\n> 1:\tldmia\tr5, {r3, r4}\t\t\t@ value, mask\n> \tand\tr4, r4, r9\t\t\t@ mask wanted bits\n> \tteq\tr3, r4\n> @@ -166,17 +167,6 @@ __lookup_processor_type:\n> 2:\tret\tlr\n> ENDPROC(__lookup_processor_type)\n> \n> -/*\n> - * Look in for information about the __proc_info structure.\n> - */\n> -\t.align\t2\n> -\t.type\t__lookup_processor_type_data, %object\n> -__lookup_processor_type_data:\n> -\t.long\t.\n> -\t.long\t__proc_info_begin\n> -\t.long\t__proc_info_end\n> -\t.size\t__lookup_processor_type_data, . - __lookup_processor_type_data\n> -\n> __error_lpae:\n> #ifdef CONFIG_DEBUG_LL\n> \tadr\tr0, str_lpae\n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762745,"web_url":"http://patchwork.ozlabs.org/comment/1762745/","msgid":"","list_archive_url":null,"date":"2017-09-04T16:08:25","subject":"Re: [PATCH v2 05/29] ARM: head-common.S: use PC-relative insn\n\tsequence for idmap creation","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> Replace the open coded PC relative offset calculations involving\n> __turn_mmu_on and __turn_mmu_on_end with a pair of adr_l invocations.\n> This ensures these quantities are invariant under runtime relocation.\n> \n> Cc: Russell King \n> Signed-off-by: Ard Biesheuvel \n\nAcked-by: Nicolas Pitre \n\n> ---\n> arch/arm/kernel/head.S | 12 ++----------\n> 1 file changed, 2 insertions(+), 10 deletions(-)\n> \n> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S\n> index 04286fd9e09c..0a98aec0e39d 100644\n> --- a/arch/arm/kernel/head.S\n> +++ b/arch/arm/kernel/head.S\n> @@ -227,11 +227,8 @@ __create_page_tables:\n> \t * Create identity mapping to cater for __enable_mmu.\n> \t * This identity mapping will be removed by paging_init().\n> \t */\n> -\tadr\tr0, __turn_mmu_on_loc\n> -\tldmia\tr0, {r3, r5, r6}\n> -\tsub\tr0, r0, r3\t\t\t@ virt->phys offset\n> -\tadd\tr5, r5, r0\t\t\t@ phys __turn_mmu_on\n> -\tadd\tr6, r6, r0\t\t\t@ phys __turn_mmu_on_end\n> +\tadr_l\tr5, __turn_mmu_on\t\t@ _pa(__turn_mmu_on)\n> +\tadr_l\tr6, __turn_mmu_on_end\t\t@ _pa(__turn_mmu_on_end)\n> \tmov\tr5, r5, lsr #SECTION_SHIFT\n> \tmov\tr6, r6, lsr #SECTION_SHIFT\n> \n> @@ -354,11 +351,6 @@ __create_page_tables:\n> \tret\tlr\n> ENDPROC(__create_page_tables)\n> \t.ltorg\n> -\t.align\n> -__turn_mmu_on_loc:\n> -\t.long\t.\n> -\t.long\t__turn_mmu_on\n> -\t.long\t__turn_mmu_on_end\n> \n> #if defined(CONFIG_SMP)\n> \t.text\n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762748,"web_url":"http://patchwork.ozlabs.org/comment/1762748/","msgid":"","list_archive_url":null,"date":"2017-09-04T16:09:55","subject":"Re: [PATCH v2 06/29] ARM: head.S: use PC-relative insn sequence for\n\tsecondary_data","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> Replace the open coded PC relative offset calculations with adr_l\n> and ldr_l invocations. This ensures these quantities are invariant\n> under runtime relocation.\n> \n> Cc: Russell King \n> Signed-off-by: Ard Biesheuvel \n\nAcked-by: Nicolas Pitre \n\n> ---\n> arch/arm/kernel/head.S | 19 ++++---------------\n> 1 file changed, 4 insertions(+), 15 deletions(-)\n> \n> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S\n> index 0a98aec0e39d..6e9df3663a57 100644\n> --- a/arch/arm/kernel/head.S\n> +++ b/arch/arm/kernel/head.S\n> @@ -386,10 +386,8 @@ ENTRY(secondary_startup)\n> \t/*\n> \t * Use the page tables supplied from __cpu_up.\n> \t */\n> -\tadr\tr4, __secondary_data\n> -\tldmia\tr4, {r5, r7, r12}\t\t@ address to jump to after\n> -\tsub\tlr, r4, r5\t\t\t@ mmu has been enabled\n> -\tadd\tr3, r7, lr\n> +\tadr_l\tr3, secondary_data\n> +\tmov_l\tr12, __secondary_switched\n> \tldrd\tr4, [r3, #0]\t\t\t@ get secondary_data.pgdir\n> ARM_BE8(eor\tr4, r4, r5)\t\t\t@ Swap r5 and r4 in BE:\n> ARM_BE8(eor\tr5, r4, r5)\t\t\t@ it can be done in 3 steps\n> @@ -404,22 +402,13 @@ ARM_BE8(eor\tr4, r4, r5)\t\t\t@ without using a temp reg.\n> ENDPROC(secondary_startup)\n> ENDPROC(secondary_startup_arm)\n> \n> -\t/*\n> -\t * r6 = &secondary_data\n> -\t */\n> ENTRY(__secondary_switched)\n> -\tldr\tsp, [r7, #12]\t\t\t@ get secondary_data.stack\n> +\tldr_l\tr7, secondary_data + 12\t\t@ get secondary_data.stack\n> +\tmov\tsp, r7\n> \tmov\tfp, #0\n> \tb\tsecondary_start_kernel\n> ENDPROC(__secondary_switched)\n> \n> -\t.align\n> -\n> -\t.type\t__secondary_data, %object\n> -__secondary_data:\n> -\t.long\t.\n> -\t.long\tsecondary_data\n> -\t.long\t__secondary_switched\n> #endif /* defined(CONFIG_SMP) */\n> \n> \n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762751,"web_url":"http://patchwork.ozlabs.org/comment/1762751/","msgid":"","list_archive_url":null,"date":"2017-09-04T16:15:32","subject":"Re: [PATCH v2 07/29] ARM: kernel: use relative references for UP/SMP\n\talternatives","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> To avoid absolute references that are subject to runtime relocation\n> when running a kernel built with CONFIG_RELOCATABLE=y, use relative\n> references in the smp.alt entries.\n> \n> Cc: Russell King \n> Signed-off-by: Ard Biesheuvel \n\nAcked-by: Nicolas Pitre \n\n> ---\n> arch/arm/include/asm/assembler.h | 4 ++--\n> arch/arm/include/asm/processor.h | 2 +-\n> arch/arm/kernel/head.S | 10 +++++-----\n> 3 files changed, 8 insertions(+), 8 deletions(-)\n> \n> diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h\n> index 341e4ed1ef84..a0906c1fc65d 100644\n> --- a/arch/arm/include/asm/assembler.h\n> +++ b/arch/arm/include/asm/assembler.h\n> @@ -260,7 +260,7 @@\n> */\n> #define ALT_UP(instr...)\t\t\t\t\t\\\n> \t.pushsection \".alt.smp.init\", \"a\"\t\t\t;\\\n> -\t.long\t9998b\t\t\t\t\t\t;\\\n> +\t.long\t9998b - .\t\t\t\t\t;\\\n> 9997:\tinstr\t\t\t\t\t\t\t;\\\n> \t.if . - 9997b == 2\t\t\t\t\t;\\\n> \t\tnop\t\t\t\t\t\t;\\\n> @@ -272,7 +272,7 @@\n> #define ALT_UP_B(label)\t\t\t\t\t\\\n> \t.equ\tup_b_offset, label - 9998b\t\t\t;\\\n> \t.pushsection \".alt.smp.init\", \"a\"\t\t\t;\\\n> -\t.long\t9998b\t\t\t\t\t\t;\\\n> +\t.long\t9998b - .\t\t\t\t\t;\\\n> \tW(b)\t. + up_b_offset\t\t\t\t\t;\\\n> \t.popsection\n> #else\n> diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h\n> index c3d5fc124a05..3667b395bb17 100644\n> --- a/arch/arm/include/asm/processor.h\n> +++ b/arch/arm/include/asm/processor.h\n> @@ -92,7 +92,7 @@ unsigned long get_wchan(struct task_struct *p);\n> #define __ALT_SMP_ASM(smp, up)\t\t\t\t\t\t\\\n> \t\"9998:\t\" smp \"\\n\"\t\t\t\t\t\t\\\n> \t\"\t.pushsection \\\".alt.smp.init\\\", \\\"a\\\"\\n\"\t\t\\\n> -\t\"\t.long\t9998b\\n\"\t\t\t\t\t\\\n> +\t\"\t.long\t9998b - .\\n\"\t\t\t\t\t\\\n> \t\"\t\" up \"\\n\"\t\t\t\t\t\t\\\n> \t\"\t.popsection\\n\"\n> #else\n> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S\n> index 6e9df3663a57..ec22f42fd8bb 100644\n> --- a/arch/arm/kernel/head.S\n> +++ b/arch/arm/kernel/head.S\n> @@ -548,14 +548,15 @@ smp_on_up:\n> __do_fixup_smp_on_up:\n> \tcmp\tr4, r5\n> \treths\tlr\n> -\tldmia\tr4!, {r0, r6}\n> - ARM(\tstr\tr6, [r0, r3]\t)\n> - THUMB(\tadd\tr0, r0, r3\t)\n> +\tldmia\tr4, {r0, r6}\n> + ARM(\tstr\tr6, [r0, r4]\t)\n> + THUMB(\tadd\tr0, r0, r4\t)\n> +\tadd\tr4, r4, #8\n> #ifdef __ARMEB__\n> THUMB(\tmov\tr6, r6, ror #16\t)\t@ Convert word order for big-endian.\n> #endif\n> THUMB(\tstrh\tr6, [r0], #2\t)\t@ For Thumb-2, store as two halfwords\n> - THUMB(\tmov\tr6, r6, lsr #16\t)\t@ to be robust against misaligned r3.\n> + THUMB(\tmov\tr6, r6, lsr #16\t)\t@ to be robust against misaligned r0.\n> THUMB(\tstrh\tr6, [r0]\t)\n> \tb\t__do_fixup_smp_on_up\n> ENDPROC(__do_fixup_smp_on_up)\n> @@ -564,7 +565,6 @@ ENTRY(fixup_smp)\n> \tstmfd\tsp!, {r4 - r6, lr}\n> \tmov\tr4, r0\n> \tadd\tr5, r0, r1\n> -\tmov\tr3, #0\n> \tbl\t__do_fixup_smp_on_up\n> \tldmfd\tsp!, {r4 - r6, pc}\n> ENDPROC(fixup_smp)\n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762755,"web_url":"http://patchwork.ozlabs.org/comment/1762755/","msgid":"","list_archive_url":null,"date":"2017-09-04T16:19:10","subject":"Re: [PATCH v2 08/29] ARM: head: use PC-relative insn sequence for\n\t__smp_alt","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> Replace the open coded PC relative offset calculations with a pair\n> of adr_l invocations. This ensures these quantities are invariant\n> under runtime relocation.\n\nYou probably should add that this patch must be applied on top of \"ARM: \nkernel: use relative references for UP/SMP alternatives\" because of the \nexpected r3 value prior to that patch.\n\nAcked-by: Nicolas Pitre \n\n> Cc: Russell King \n> Signed-off-by: Ard Biesheuvel \n> ---\n> arch/arm/kernel/head.S | 12 ++----------\n> 1 file changed, 2 insertions(+), 10 deletions(-)\n> \n> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S\n> index ec22f42fd8bb..db6b823f20a4 100644\n> --- a/arch/arm/kernel/head.S\n> +++ b/arch/arm/kernel/head.S\n> @@ -523,19 +523,11 @@ ARM_BE8(rev\tr0, r0)\t\t\t@ byteswap if big endian\n> \tretne\tlr\n> \n> __fixup_smp_on_up:\n> -\tadr\tr0, 1f\n> -\tldmia\tr0, {r3 - r5}\n> -\tsub\tr3, r0, r3\n> -\tadd\tr4, r4, r3\n> -\tadd\tr5, r5, r3\n> +\tadr_l\tr4, __smpalt_begin\n> +\tadr_l\tr5, __smpalt_end\n> \tb\t__do_fixup_smp_on_up\n> ENDPROC(__fixup_smp)\n> \n> -\t.align\n> -1:\t.word\t.\n> -\t.word\t__smpalt_begin\n> -\t.word\t__smpalt_end\n> -\n> \t.pushsection .data\n> \t.globl\tsmp_on_up\n> smp_on_up:\n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762758,"web_url":"http://patchwork.ozlabs.org/comment/1762758/","msgid":"","list_archive_url":null,"date":"2017-09-04T16:20:21","subject":"Re: [PATCH v2 08/29] ARM: head: use PC-relative insn sequence for\n\t__smp_alt","submitter":{"id":26857,"url":"http://patchwork.ozlabs.org/api/people/26857/","name":"Ard Biesheuvel","email":"ard.biesheuvel@linaro.org"},"content":"On 4 September 2017 at 17:19, Nicolas Pitre wrote:\n> On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n>\n>> Replace the open coded PC relative offset calculations with a pair\n>> of adr_l invocations. This ensures these quantities are invariant\n>> under runtime relocation.\n>\n> You probably should add that this patch must be applied on top of \"ARM:\n> kernel: use relative references for UP/SMP alternatives\" because of the\n> expected r3 value prior to that patch.\n>\n> Acked-by: Nicolas Pitre \n>\n\nYes, that is why I needed to reorder them. I will add a mention to the\ncommit log.\n\nThanks,","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"jEKnk6Mf\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"Maf/XU65\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xmFT42Llyz9t2W\n\tfor ;\n\tTue, 5 Sep 2017 02:20:56 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dou7I-0006LY-Im; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762759,"web_url":"http://patchwork.ozlabs.org/comment/1762759/","msgid":"","list_archive_url":null,"date":"2017-09-04T16:20:47","subject":"Re: [PATCH v2 09/29] ARM: sleep.S: use PC-relative insn sequence\n\tfor sleep_save_sp/mpidr_hash","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> Replace the open coded PC relative offset calculations with adr_l and\n> ldr_l invocations. Note that ALT_SMP() expects a single instruction\n> so move the macro invocation after it.\n> \n> Signed-off-by: Ard Biesheuvel \n\nAcked-by: Nicolas Pitre \n\n> ---\n> arch/arm/kernel/sleep.S | 19 +++++--------------\n> 1 file changed, 5 insertions(+), 14 deletions(-)\n> \n> diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S\n> index 0f6c1000582c..f4920b5d0fc4 100644\n> --- a/arch/arm/kernel/sleep.S\n> +++ b/arch/arm/kernel/sleep.S\n> @@ -71,8 +71,9 @@ ENTRY(__cpu_suspend)\n> \tldr\tr3, =sleep_save_sp\n> \tstmfd\tsp!, {r0, r1}\t\t@ save suspend func arg and pointer\n> \tldr\tr3, [r3, #SLEEP_SAVE_SP_VIRT]\n> -\tALT_SMP(ldr r0, =mpidr_hash)\n> +\tALT_SMP(W(nop))\t\t\t@ don't use adr_l inside ALT_SMP()\n> \tALT_UP_B(1f)\n> +\tadr_l\tr0, mpidr_hash\n> \t/* This ldmia relies on the memory layout of the mpidr_hash struct */\n> \tldmia\tr0, {r1, r6-r8}\t@ r1 = mpidr mask (r6,r7,r8) = l[0,1,2] shifts\n> \tcompute_mpidr_hash\tr0, r6, r7, r8, r2, r1\n> @@ -137,9 +138,8 @@ ARM_BE8(setend be)\t\t\t@ ensure we are in BE mode\n> \tmov\tr1, #0\n> \tALT_SMP(mrc p15, 0, r0, c0, c0, 5)\n> \tALT_UP_B(1f)\n> -\tadr\tr2, mpidr_hash_ptr\n> -\tldr\tr3, [r2]\n> -\tadd\tr2, r2, r3\t\t@ r2 = struct mpidr_hash phys address\n> +\tadr_l\tr2, mpidr_hash\t\t@ r2 = struct mpidr_hash phys address\n> +\n> \t/*\n> \t * This ldmia relies on the memory layout of the mpidr_hash\n> \t * struct mpidr_hash.\n> @@ -147,10 +147,7 @@ ARM_BE8(setend be)\t\t\t@ ensure we are in BE mode\n> \tldmia\tr2, { r3-r6 }\t@ r3 = mpidr mask (r4,r5,r6) = l[0,1,2] shifts\n> \tcompute_mpidr_hash\tr1, r4, r5, r6, r0, r3\n> 1:\n> -\tadr\tr0, _sleep_save_sp\n> -\tldr\tr2, [r0]\n> -\tadd\tr0, r0, r2\n> -\tldr\tr0, [r0, #SLEEP_SAVE_SP_PHYS]\n> +\tldr_l\tr0, sleep_save_sp + SLEEP_SAVE_SP_PHYS\n> \tldr\tr0, [r0, r1, lsl #2]\n> \n> \t@ load phys pgd, stack, resume fn\n> @@ -164,12 +161,6 @@ ENDPROC(cpu_resume)\n> ENDPROC(cpu_resume_arm)\n> #endif\n> \n> -\t.align 2\n> -_sleep_save_sp:\n> -\t.long\tsleep_save_sp - .\n> -mpidr_hash_ptr:\n> -\t.long\tmpidr_hash - .\t\t\t@ mpidr_hash struct offset\n> -\n> \t.data\n> \t.type\tsleep_save_sp, #object\n> ENTRY(sleep_save_sp)\n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762780,"web_url":"http://patchwork.ozlabs.org/comment/1762780/","msgid":"","list_archive_url":null,"date":"2017-09-04T16:47:16","subject":"Re: [PATCH v2 10/29] ARM: head.S: use PC-relative insn sequences\n\tfor __fixup_pv_table","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> Replace the open coded PC relative offset calculations with adr_l\n> and mov_l invocations. This ensures these quantities are invariant\n> under runtime relocation.\n> \n> Cc: Russell King \n> Signed-off-by: Ard Biesheuvel \n\nAcked-by: Nicolas Pitre \n\n\n> ---\n> arch/arm/kernel/head.S | 27 ++++++--------------\n> 1 file changed, 8 insertions(+), 19 deletions(-)\n> \n> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S\n> index db6b823f20a4..f607e290ef4b 100644\n> --- a/arch/arm/kernel/head.S\n> +++ b/arch/arm/kernel/head.S\n> @@ -578,14 +578,11 @@ ENDPROC(fixup_smp)\n> */\n> \t__HEAD\n> __fixup_pv_table:\n> -\tadr\tr0, 1f\n> -\tldmia\tr0, {r3-r7}\n> +\tadr_l\tr6, __pv_phys_pfn_offset\n> +\tadr_l\tr7, __pv_offset\t\t\t@ __pa(__pv_offset)\n> +\tmov_l\tr3, __pv_offset\t\t\t@ __va(__pv_offset)\n> \tmvn\tip, #0\n> -\tsubs\tr3, r0, r3\t@ PHYS_OFFSET - PAGE_OFFSET\n> -\tadd\tr4, r4, r3\t@ adjust table start address\n> -\tadd\tr5, r5, r3\t@ adjust table end address\n> -\tadd\tr6, r6, r3\t@ adjust __pv_phys_pfn_offset address\n> -\tadd\tr7, r7, r3\t@ adjust __pv_offset address\n> +\tsubs\tr3, r7, r3\t@ PHYS_OFFSET - PAGE_OFFSET\n> \tmov\tr0, r8, lsr #PAGE_SHIFT\t@ convert to PFN\n> \tstr\tr0, [r6]\t@ save computed PHYS_OFFSET to __pv_phys_pfn_offset\n> \tstrcc\tip, [r7, #HIGH_OFFSET]\t@ save to __pv_offset high bits\n> @@ -594,20 +591,15 @@ __fixup_pv_table:\n> THUMB(\tit\tne\t\t@ cross section branch )\n> \tbne\t__error\n> \tstr\tr3, [r7, #LOW_OFFSET]\t@ save to __pv_offset low bits\n> +\tadr_l\tr4, __pv_table_begin\n> +\tadr_l\tr5, __pv_table_end\n> \tb\t__fixup_a_pv_table\n> ENDPROC(__fixup_pv_table)\n> -\n> -\t.align\n> -1:\t.long\t.\n> -\t.long\t__pv_table_begin\n> -\t.long\t__pv_table_end\n> -2:\t.long\t__pv_phys_pfn_offset\n> -\t.long\t__pv_offset\n> +\t.ltorg\n> \n> \t.text\n> __fixup_a_pv_table:\n> -\tadr\tr0, 3f\n> -\tldr\tr6, [r0]\n> +\tmov_l\tr6, __pv_offset\n> \tadd\tr6, r6, r3\n> \tldr\tr0, [r6, #HIGH_OFFSET]\t@ pv_offset high word\n> \tldr\tr6, [r6, #LOW_OFFSET]\t@ pv_offset low word\n> @@ -676,9 +668,6 @@ ARM_BE8(rev16\tip, ip)\n> #endif\n> ENDPROC(__fixup_a_pv_table)\n> \n> -\t.align\n> -3:\t.long __pv_offset\n> -\n> ENTRY(fixup_pv_table)\n> \tstmfd\tsp!, {r4 - r7, lr}\n> \tmov\tr3, #0\t\t\t@ no offset\n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762782,"web_url":"http://patchwork.ozlabs.org/comment/1762782/","msgid":"","list_archive_url":null,"date":"2017-09-04T16:50:32","subject":"Re: [PATCH v2 11/29] ARM: head.S: use PC relative insn sequence to\n\tcalculate PHYS_OFFSET","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> Replace the open coded arithmetic with a simple adr_l/sub pair. This\n> ensures these quantities are invariant under runtime relocation.\n> \n> Cc: Russell King \n> Signed-off-by: Ard Biesheuvel \n\nOf course there won't be anything to relocate in a XIP kernel. But \nconsistency is good and this looks nicer.\n\nAcked-by: Nicolas Pitre \n\n> ---\n> arch/arm/kernel/head.S | 10 ++--------\n> 1 file changed, 2 insertions(+), 8 deletions(-)\n> \n> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S\n> index f607e290ef4b..62c961849035 100644\n> --- a/arch/arm/kernel/head.S\n> +++ b/arch/arm/kernel/head.S\n> @@ -106,10 +106,8 @@ ENTRY(stext)\n> #endif\n> \n> #ifndef CONFIG_XIP_KERNEL\n> -\tadr\tr3, 2f\n> -\tldmia\tr3, {r4, r8}\n> -\tsub\tr4, r3, r4\t\t\t@ (PHYS_OFFSET - PAGE_OFFSET)\n> -\tadd\tr8, r8, r4\t\t\t@ PHYS_OFFSET\n> +\tadr_l\tr8, _text\t\t\t@ __pa(_text)\n> +\tsub\tr8, r8, #TEXT_OFFSET\t\t@ PHYS_OFFSET\n> #else\n> \tldr\tr8, =PLAT_PHYS_OFFSET\t\t@ always constant in this case\n> #endif\n> @@ -161,10 +159,6 @@ ENTRY(stext)\n> 1:\tb\t__enable_mmu\n> ENDPROC(stext)\n> \t.ltorg\n> -#ifndef CONFIG_XIP_KERNEL\n> -2:\t.long\t.\n> -\t.long\tPAGE_OFFSET\n> -#endif\n> \n> /*\n> * Setup the initial page tables. We only setup the barest\n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"C7dk0LFa\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"TTW9uHXc\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xmG7n5g1mz9sR9\n\tfor ;\n\tTue, 5 Sep 2017 02:51:01 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1douaQ-0004Qy-Rv; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762785,"web_url":"http://patchwork.ozlabs.org/comment/1762785/","msgid":"","list_archive_url":null,"date":"2017-09-04T16:57:23","subject":"Re: [PATCH v2 12/29] ARM: kvm: replace open coded VA->PA\n\tcalculations with adr_l call","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> Replace the open coded calculations of the actual physical address\n> of the KVM stub vector table with a single adr_l invocation.\n> \n> Cc: Marc Zyngier \n> Signed-off-by: Ard Biesheuvel \n\nAcked-by: Nicolas Pitre \n\n> ---\n> arch/arm/boot/compressed/head.S | 15 ++-------\n> arch/arm/kernel/hyp-stub.S | 33 +++++++-------------\n> arch/arm/kvm/init.S | 8 +----\n> 3 files changed, 15 insertions(+), 41 deletions(-)\n> \n> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S\n> index 8a756870c238..5884e8151376 100644\n> --- a/arch/arm/boot/compressed/head.S\n> +++ b/arch/arm/boot/compressed/head.S\n> @@ -427,15 +427,10 @@ dtb_check_done:\n> \n> \t\t/*\n> \t\t * Compute the address of the hyp vectors after relocation.\n> -\t\t * This requires some arithmetic since we cannot directly\n> -\t\t * reference __hyp_stub_vectors in a PC-relative way.\n> \t\t * Call __hyp_set_vectors with the new address so that we\n> \t\t * can HVC again after the copy.\n> \t\t */\n> -0:\t\tadr\tr0, 0b\n> -\t\tmovw\tr1, #:lower16:__hyp_stub_vectors - 0b\n> -\t\tmovt\tr1, #:upper16:__hyp_stub_vectors - 0b\n> -\t\tadd\tr0, r0, r1\n> +\t\tadr_l\tr0, __hyp_stub_vectors\n> \t\tsub\tr0, r0, r5\n> \t\tadd\tr0, r0, r10\n> \t\tbl\t__hyp_set_vectors\n> @@ -568,17 +563,11 @@ not_relocated:\tmov\tr0, #0\n> \t\tcmp\tr0, #HYP_MODE\t\t@ if not booted in HYP mode...\n> \t\tbne\t__enter_kernel\t\t@ boot kernel directly\n> \n> -\t\tadr\tr12, .L__hyp_reentry_vectors_offset\n> -\t\tldr\tr0, [r12]\n> -\t\tadd\tr0, r0, r12\n> -\n> +\t\tadr_l\tr0, __hyp_reentry_vectors\n> \t\tbl\t__hyp_set_vectors\n> \t\t__HVC(0)\t\t\t@ otherwise bounce to hyp mode\n> \n> \t\tb\t.\t\t\t@ should never be reached\n> -\n> -\t\t.align\t2\n> -.L__hyp_reentry_vectors_offset:\t.long\t__hyp_reentry_vectors - .\n> #else\n> \t\tb\t__enter_kernel\n> #endif\n> diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S\n> index ec7e7377d423..3c2d1738d3f4 100644\n> --- a/arch/arm/kernel/hyp-stub.S\n> +++ b/arch/arm/kernel/hyp-stub.S\n> @@ -36,41 +36,38 @@ ENTRY(__boot_cpu_mode)\n> .text\n> \n> \t/*\n> -\t * Save the primary CPU boot mode. Requires 3 scratch registers.\n> +\t * Save the primary CPU boot mode. Requires 2 scratch registers.\n> \t */\n> -\t.macro\tstore_primary_cpu_mode\treg1, reg2, reg3\n> +\t.macro\tstore_primary_cpu_mode\treg1, reg2\n> \tmrs\t\\reg1, cpsr\n> \tand\t\\reg1, \\reg1, #MODE_MASK\n> -\tadr\t\\reg2, .L__boot_cpu_mode_offset\n> -\tldr\t\\reg3, [\\reg2]\n> -\tstr\t\\reg1, [\\reg2, \\reg3]\n> +\tstr_l\t\\reg1, __boot_cpu_mode, \\reg2\n> \t.endm\n> \n> \t/*\n> \t * Compare the current mode with the one saved on the primary CPU.\n> \t * If they don't match, record that fact. The Z bit indicates\n> \t * if there's a match or not.\n> -\t * Requires 3 additionnal scratch registers.\n> +\t * Requires 2 additional scratch registers.\n> \t */\n> -\t.macro\tcompare_cpu_mode_with_primary mode, reg1, reg2, reg3\n> -\tadr\t\\reg2, .L__boot_cpu_mode_offset\n> -\tldr\t\\reg3, [\\reg2]\n> -\tldr\t\\reg1, [\\reg2, \\reg3]\n> +\t.macro\tcompare_cpu_mode_with_primary mode, reg1, reg2\n> +\tadr_l\t\\reg2, __boot_cpu_mode\n> +\tldr\t\\reg1, [\\reg2]\n> \tcmp\t\\mode, \\reg1\t\t@ matches primary CPU boot mode?\n> \torrne\t\\reg1, \\reg1, #BOOT_CPU_MODE_MISMATCH\n> -\tstrne\t\\reg1, [\\reg2, \\reg3]\t@ record what happened and give up\n> +\tstrne\t\\reg1, [\\reg2]\t\t@ record what happened and give up\n> \t.endm\n> \n> #else\t/* ZIMAGE */\n> \n> -\t.macro\tstore_primary_cpu_mode\treg1:req, reg2:req, reg3:req\n> +\t.macro\tstore_primary_cpu_mode\treg1:req, reg2:req\n> \t.endm\n> \n> /*\n> * The zImage loader only runs on one CPU, so we don't bother with mult-CPU\n> * consistency checking:\n> */\n> -\t.macro\tcompare_cpu_mode_with_primary mode, reg1, reg2, reg3\n> +\t.macro\tcompare_cpu_mode_with_primary mode, reg1, reg2\n> \tcmp\t\\mode, \\mode\n> \t.endm\n> \n> @@ -85,7 +82,7 @@ ENTRY(__boot_cpu_mode)\n> */\n> @ Call this from the primary CPU\n> ENTRY(__hyp_stub_install)\n> -\tstore_primary_cpu_mode\tr4, r5, r6\n> +\tstore_primary_cpu_mode\tr4, r5\n> ENDPROC(__hyp_stub_install)\n> \n> \t@ fall through...\n> @@ -99,7 +96,7 @@ ENTRY(__hyp_stub_install_secondary)\n> \t * If the secondary has booted with a different mode, give up\n> \t * immediately.\n> \t */\n> -\tcompare_cpu_mode_with_primary\tr4, r5, r6, r7\n> +\tcompare_cpu_mode_with_primary\tr4, r5, r6\n> \tretne\tlr\n> \n> \t/*\n> @@ -264,12 +261,6 @@ ENTRY(__hyp_reset_vectors)\n> \tret\tlr\n> ENDPROC(__hyp_reset_vectors)\n> \n> -#ifndef ZIMAGE\n> -.align 2\n> -.L__boot_cpu_mode_offset:\n> -\t.long\t__boot_cpu_mode - .\n> -#endif\n> -\n> .align 5\n> ENTRY(__hyp_stub_vectors)\n> __hyp_stub_reset:\tW(b)\t.\n> diff --git a/arch/arm/kvm/init.S b/arch/arm/kvm/init.S\n> index 5386528665b5..d777c6fbd869 100644\n> --- a/arch/arm/kvm/init.S\n> +++ b/arch/arm/kvm/init.S\n> @@ -143,13 +143,7 @@ reset:\n> \tbic\tr1, r1, r0\n> \tmcr\tp15, 4, r1, c1, c0, 0\t@ HSCTLR\n> \n> -\t/*\n> -\t * Install stub vectors, using ardb's VA->PA trick.\n> -\t */\n> -0:\tadr\tr0, 0b\t\t\t\t\t@ PA(0)\n> -\tmovw\tr1, #:lower16:__hyp_stub_vectors - 0b @ VA(stub) - VA(0)\n> -\tmovt\tr1, #:upper16:__hyp_stub_vectors - 0b\n> -\tadd\tr1, r1, r0\t\t\t\t@ PA(stub)\n> +\tadr_l\tr1, __hyp_stub_vectors\t\t\t@ PA(stub)\n> \tmcr\tp15, 4, r1, c12, c0, 0\t@ HVBAR\n> \tb\texit\n> \n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762786,"web_url":"http://patchwork.ozlabs.org/comment/1762786/","msgid":"","list_archive_url":null,"date":"2017-09-04T16:59:24","subject":"Re: [PATCH v2 13/29] arm-soc: exynos: replace open coded VA->PA\n\tconversions","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> This replaces a couple of open coded calculations to obtain the\n> physical address of a far symbol with calls to the new adr_l etc\n> macros.\n> \n> Signed-off-by: Ard Biesheuvel \n\nAcked-by: Nicolas Pitre \n\n\n> ---\n> arch/arm/mach-exynos/headsmp.S | 9 +------\n> arch/arm/mach-exynos/sleep.S | 26 ++++----------------\n> 2 files changed, 6 insertions(+), 29 deletions(-)\n> \n> diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S\n> index d3d24ab351ae..25de5aff1c41 100644\n> --- a/arch/arm/mach-exynos/headsmp.S\n> +++ b/arch/arm/mach-exynos/headsmp.S\n> @@ -23,10 +23,7 @@ ENTRY(exynos4_secondary_startup)\n> ARM_BE8(setend\tbe)\n> \tmrc\tp15, 0, r0, c0, c0, 5\n> \tand\tr0, r0, #15\n> -\tadr\tr4, 1f\n> -\tldmia\tr4, {r5, r6}\n> -\tsub\tr4, r4, r5\n> -\tadd\tr6, r6, r4\n> +\tadr_l\tr6, pen_release\n> pen:\tldr\tr7, [r6]\n> \tcmp\tr7, r0\n> \tbne\tpen\n> @@ -37,7 +34,3 @@ pen:\tldr\tr7, [r6]\n> \t */\n> \tb\tsecondary_startup\n> ENDPROC(exynos4_secondary_startup)\n> -\n> -\t.align 2\n> -1:\t.long\t.\n> -\t.long\tpen_release\n> diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S\n> index cf950790fbdc..003465699263 100644\n> --- a/arch/arm/mach-exynos/sleep.S\n> +++ b/arch/arm/mach-exynos/sleep.S\n> @@ -17,6 +17,7 @@\n> \n> #include \n> #include \n> +#include \n> #include \n> #include \"smc.h\"\n> \n> @@ -62,19 +63,13 @@ ENTRY(exynos_cpu_resume_ns)\n> \tcmp\tr0, r1\n> \tbne\tskip_cp15\n> \n> -\tadr\tr0, _cp15_save_power\n> -\tldr\tr1, [r0]\n> -\tldr\tr1, [r0, r1]\n> -\tadr\tr0, _cp15_save_diag\n> -\tldr\tr2, [r0]\n> -\tldr\tr2, [r0, r2]\n> +\tldr_l\tr1, cp15_save_power\n> +\tldr_l\tr2, cp15_save_diag\n> \tmov\tr0, #SMC_CMD_C15RESUME\n> \tdsb\n> \tsmc\t#0\n> #ifdef CONFIG_CACHE_L2X0\n> -\tadr\tr0, 1f\n> -\tldr\tr2, [r0]\n> -\tadd\tr0, r2, r0\n> +\tadr_l\tr0, l2x0_saved_regs\n> \n> \t/* Check that the address has been initialised. */\n> \tldr\tr1, [r0, #L2X0_R_PHY_BASE]\n> @@ -93,9 +88,7 @@ ENTRY(exynos_cpu_resume_ns)\n> \tsmc\t#0\n> \n> \t/* Reload saved regs pointer because smc corrupts registers. */\n> -\tadr\tr0, 1f\n> -\tldr\tr2, [r0]\n> -\tadd\tr0, r2, r0\n> +\tadr_l\tr0, l2x0_saved_regs\n> \n> \tldr\tr1, [r0, #L2X0_R_PWR_CTRL]\n> \tldr\tr2, [r0, #L2X0_R_AUX_CTRL]\n> @@ -114,15 +107,6 @@ skip_cp15:\n> \tb\tcpu_resume\n> ENDPROC(exynos_cpu_resume_ns)\n> \n> -\t.align\n> -_cp15_save_power:\n> -\t.long\tcp15_save_power - .\n> -_cp15_save_diag:\n> -\t.long\tcp15_save_diag - .\n> -#ifdef CONFIG_CACHE_L2X0\n> -1:\t.long\tl2x0_saved_regs - .\n> -#endif /* CONFIG_CACHE_L2X0 */\n> -\n> \t.data\n> \t.globl cp15_save_diag\n> cp15_save_diag:\n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762788,"web_url":"http://patchwork.ozlabs.org/comment/1762788/","msgid":"","list_archive_url":null,"date":"2017-09-04T17:00:37","subject":"Re: [PATCH v2 14/29] arm-soc: mvebu: replace open coded VA->PA\n\tconversion","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> This replaces an open coded calculation to obtain the physical\n> address of a far symbol with a call to the new ldr_l etc macro.\n> \n> Signed-off-by: Ard Biesheuvel \n\nAcked-by: Nicolas Pitre \n\n> ---\n> arch/arm/mach-mvebu/coherency_ll.S | 8 +-------\n> 1 file changed, 1 insertion(+), 7 deletions(-)\n> \n> diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S\n> index 8b2fbc8b6bc6..df0ccb5cef1d 100644\n> --- a/arch/arm/mach-mvebu/coherency_ll.S\n> +++ b/arch/arm/mach-mvebu/coherency_ll.S\n> @@ -42,9 +42,7 @@ ENTRY(ll_get_coherency_base)\n> \tldr\tr1, =coherency_base\n> \tcmp\tr1, #0\n> \tbeq\t2f\n> -\tadr\tr1, 3f\n> -\tldr\tr3, [r1]\n> -\tldr\tr1, [r1, r3]\n> +\tldr_l\tr1, coherency_phys_base\n> \tb\t2f\n> 1:\n> \t/*\n> @@ -160,7 +158,3 @@ ENTRY(ll_disable_coherency)\n> \tdsb\n> \tret\tlr\n> ENDPROC(ll_disable_coherency)\n> -\n> -\t.align 2\n> -3:\n> -\t.long\tcoherency_phys_base - .\n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762794,"web_url":"http://patchwork.ozlabs.org/comment/1762794/","msgid":"","list_archive_url":null,"date":"2017-09-04T17:09:04","subject":"Re: [PATCH v2 02/29] asm-generic: add .data.rel.ro sections to\n\t__ro_after_init","submitter":{"id":10641,"url":"http://patchwork.ozlabs.org/api/people/10641/","name":"Kees Cook","email":"keescook@chromium.org"},"content":"On Sun, Sep 3, 2017 at 5:07 AM, Ard Biesheuvel\n wrote:\n> When running in PIC mode, the compiler will emit const structures\n> containing runtime relocatable quantities into .data.rel.ro.* sections,\n> so that the linker can be smart about placing them together in a segment\n> that is read-write initially, and is remapped read-only afterwards. This\n> is exactly what __ro_after_init aims to provide, so move these sections\n> together.\n>\n> Acked-by: Arnd Bergmann \n> Signed-off-by: Ard Biesheuvel \n\nAcked-by: Kees Cook \n\n-Kees\n\n> ---\n> include/asm-generic/vmlinux.lds.h | 2 +-\n> 1 file changed, 1 insertion(+), 1 deletion(-)\n>\n> diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h\n> index da0be9a8d1de..d16537b0b102 100644\n> --- a/include/asm-generic/vmlinux.lds.h\n> +++ b/include/asm-generic/vmlinux.lds.h\n> @@ -261,7 +261,7 @@\n> #ifndef RO_AFTER_INIT_DATA\n> #define RO_AFTER_INIT_DATA \\\n> VMLINUX_SYMBOL(__start_ro_after_init) = .; \\\n> - *(.data..ro_after_init) \\\n> + *(.data..ro_after_init .data.rel.ro.*) \\\n> VMLINUX_SYMBOL(__end_ro_after_init) = .;\n> #endif\n>\n> --\n> 2.11.0\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762798,"web_url":"http://patchwork.ozlabs.org/comment/1762798/","msgid":"","list_archive_url":null,"date":"2017-09-04T17:17:40","subject":"Re: [PATCH v2 16/29] ARM: kernel: switch to relative exception\n\ttables","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> To avoid having to relocate the contents of extable entries at\n> runtime when running with KASLR enabled, wire up the existing\n> support for emitting them as relative references. This ensures\n> these quantities are invariant under runtime relocation.\n> \n> Cc: Russell King \n> Signed-off-by: Ard Biesheuvel \n\nCould it be better to have a macro that encapsulates exception entries \ne.g.:\n\n\t.macro ex_entry insn fixup\n\t.long\t\\insn - ., \\fixup - .\n\t.endif\n\nso that if ever this changes again or for whatever reason someone needs \nabsolute entries then this won't have to be done everywhere. The section \nswitch could be included in such a macro too. And it is so easy to \nforget to do the \"- .\" when adding new entries.\n\n\n\n\n\n> ---\n> arch/arm/include/asm/Kbuild | 1 -\n> arch/arm/include/asm/assembler.h | 6 +++---\n> arch/arm/include/asm/extable.h | 19 +++++++++++++++++\n> arch/arm/include/asm/futex.h | 2 +-\n> arch/arm/include/asm/uaccess.h | 8 +++----\n> arch/arm/include/asm/word-at-a-time.h | 2 +-\n> arch/arm/kernel/entry-armv.S | 6 +++---\n> arch/arm/kernel/swp_emulate.c | 4 ++--\n> arch/arm/lib/backtrace.S | 8 +++----\n> arch/arm/lib/getuser.S | 22 ++++++++++----------\n> arch/arm/lib/putuser.S | 12 +++++------\n> arch/arm/mm/alignment.c | 14 ++++++-------\n> arch/arm/mm/extable.c | 2 +-\n> arch/arm/nwfpe/entry.S | 2 +-\n> scripts/sortextable.c | 2 +-\n> 15 files changed, 64 insertions(+), 46 deletions(-)\n> \n> diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild\n> index 721ab5ecfb9b..f2d67fa34eb3 100644\n> --- a/arch/arm/include/asm/Kbuild\n> +++ b/arch/arm/include/asm/Kbuild\n> @@ -3,7 +3,6 @@ generic-y += current.h\n> generic-y += early_ioremap.h\n> generic-y += emergency-restart.h\n> generic-y += exec.h\n> -generic-y += extable.h\n> generic-y += irq_regs.h\n> generic-y += kdebug.h\n> generic-y += local.h\n> diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h\n> index a0906c1fc65d..ae43859a9000 100644\n> --- a/arch/arm/include/asm/assembler.h\n> +++ b/arch/arm/include/asm/assembler.h\n> @@ -247,7 +247,7 @@\n> 9999:\tx;\t\t\t\t\t\\\n> \t.pushsection __ex_table,\"a\";\t\t\\\n> \t.align\t3;\t\t\t\t\\\n> -\t.long\t9999b,9001f;\t\t\t\\\n> +\t.long\t9999b - ., 9001f - .;\t\t\\\n> \t.popsection\n> \n> #ifdef CONFIG_SMP\n> @@ -383,7 +383,7 @@ THUMB(\torr\t\\reg , \\reg , #PSR_T_BIT\t)\n> \n> \t.pushsection __ex_table,\"a\"\n> \t.align\t3\n> -\t.long\t9999b, \\abort\n> +\t.long\t9999b - ., \\abort - .\n> \t.popsection\n> \t.endm\n> \n> @@ -424,7 +424,7 @@ THUMB(\torr\t\\reg , \\reg , #PSR_T_BIT\t)\n> \n> \t.pushsection __ex_table,\"a\"\n> \t.align\t3\n> -\t.long\t9999b, \\abort\n> +\t.long\t9999b - ., \\abort - .\n> \t.popsection\n> \t.endr\n> \t.endm\n> diff --git a/arch/arm/include/asm/extable.h b/arch/arm/include/asm/extable.h\n> new file mode 100644\n> index 000000000000..c85d1f4404b7\n> --- /dev/null\n> +++ b/arch/arm/include/asm/extable.h\n> @@ -0,0 +1,19 @@\n> +#ifndef __ASM_EXTABLE_H\n> +#define __ASM_EXTABLE_H\n> +\n> +/*\n> + * The exception table consists of pairs of relative offsets: the first\n> + * is the relative offset to an instruction that is allowed to fault,\n> + * and the second is the relative offset at which the program should\n> + * continue. No registers are modified, so it is entirely up to the\n> + * continuation code to figure out what to do.\n> + */\n> +\n> +struct exception_table_entry {\n> +\tint insn, fixup;\n> +};\n> +\n> +#define ARCH_HAS_RELATIVE_EXTABLE\n> +\n> +extern int fixup_exception(struct pt_regs *regs);\n> +#endif\n> diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h\n> index 6795368ad023..31760d0ab76b 100644\n> --- a/arch/arm/include/asm/futex.h\n> +++ b/arch/arm/include/asm/futex.h\n> @@ -11,7 +11,7 @@\n> \t\"3:\\n\"\t\t\t\t\t\t\t\\\n> \t\"\t.pushsection __ex_table,\\\"a\\\"\\n\"\t\t\\\n> \t\"\t.align\t3\\n\"\t\t\t\t\t\\\n> -\t\"\t.long\t1b, 4f, 2b, 4f\\n\"\t\t\t\\\n> +\t\"\t.long\t1b - ., 4f - ., 2b - ., 4f - .\\n\"\t\\\n> \t\"\t.popsection\\n\"\t\t\t\t\t\\\n> \t\"\t.pushsection .text.fixup,\\\"ax\\\"\\n\"\t\t\\\n> \t\"\t.align\t2\\n\"\t\t\t\t\t\\\n> diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h\n> index 0bf2347495f1..62b9bb7d991a 100644\n> --- a/arch/arm/include/asm/uaccess.h\n> +++ b/arch/arm/include/asm/uaccess.h\n> @@ -295,7 +295,7 @@ do {\t\t\t\t\t\t\t\t\t\\\n> \t\"\t.popsection\\n\"\t\t\t\t\t\\\n> \t\"\t.pushsection __ex_table,\\\"a\\\"\\n\"\t\t\\\n> \t\"\t.align\t3\\n\"\t\t\t\t\t\\\n> -\t\"\t.long\t1b, 3b\\n\"\t\t\t\t\\\n> +\t\"\t.long\t1b - ., 3b - .\\n\"\t\t\t\\\n> \t\"\t.popsection\"\t\t\t\t\t\\\n> \t: \"+r\" (err), \"=&r\" (x)\t\t\t\t\t\\\n> \t: \"r\" (addr), \"i\" (-EFAULT)\t\t\t\t\\\n> @@ -385,7 +385,7 @@ do {\t\t\t\t\t\t\t\t\t\\\n> \t\"\t.popsection\\n\"\t\t\t\t\t\\\n> \t\"\t.pushsection __ex_table,\\\"a\\\"\\n\"\t\t\\\n> \t\"\t.align\t3\\n\"\t\t\t\t\t\\\n> -\t\"\t.long\t1b, 3b\\n\"\t\t\t\t\\\n> +\t\"\t.long\t1b - ., 3b - .\\n\"\t\t\t\\\n> \t\"\t.popsection\"\t\t\t\t\t\\\n> \t: \"+r\" (err)\t\t\t\t\t\t\\\n> \t: \"r\" (x), \"r\" (__pu_addr), \"i\" (-EFAULT)\t\t\\\n> @@ -435,8 +435,8 @@ do {\t\t\t\t\t\t\t\t\t\\\n> \t\"\t.popsection\\n\"\t\t\t\t\t\\\n> \t\"\t.pushsection __ex_table,\\\"a\\\"\\n\"\t\t\\\n> \t\"\t.align\t3\\n\"\t\t\t\t\t\\\n> -\t\"\t.long\t1b, 4b\\n\"\t\t\t\t\\\n> -\t\"\t.long\t2b, 4b\\n\"\t\t\t\t\\\n> +\t\"\t.long\t1b - ., 4b - .\\n\"\t\t\t\\\n> +\t\"\t.long\t2b - ., 4b - .\\n\"\t\t\t\\\n> \t\"\t.popsection\"\t\t\t\t\t\\\n> \t: \"+r\" (err), \"+r\" (__pu_addr)\t\t\t\t\\\n> \t: \"r\" (x), \"i\" (-EFAULT)\t\t\t\t\\\n> diff --git a/arch/arm/include/asm/word-at-a-time.h b/arch/arm/include/asm/word-at-a-time.h\n> index 5831dce4b51c..d433c686d9ca 100644\n> --- a/arch/arm/include/asm/word-at-a-time.h\n> +++ b/arch/arm/include/asm/word-at-a-time.h\n> @@ -86,7 +86,7 @@ static inline unsigned long load_unaligned_zeropad(const void *addr)\n> \t\"\t.popsection\\n\"\n> \t\"\t.pushsection __ex_table,\\\"a\\\"\\n\"\n> \t\"\t.align\t3\\n\"\n> -\t\"\t.long\t1b, 3b\\n\"\n> +\t\"\t.long\t1b - ., 3b - .\\n\"\n> \t\"\t.popsection\"\n> \t: \"=&r\" (ret), \"=&r\" (offset)\n> \t: \"r\" (addr), \"Qo\" (*(unsigned long *)addr));\n> diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S\n> index c731f0d2b2af..1c7c12123b18 100644\n> --- a/arch/arm/kernel/entry-armv.S\n> +++ b/arch/arm/kernel/entry-armv.S\n> @@ -570,10 +570,10 @@ ENDPROC(__und_usr)\n> \tret\tr9\n> \t.popsection\n> \t.pushsection __ex_table,\"a\"\n> -\t.long\t1b, 4b\n> +\t.long\t1b - ., 4b - .\n> #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7\n> -\t.long\t2b, 4b\n> -\t.long\t3b, 4b\n> +\t.long\t2b - ., 4b - .\n> +\t.long\t3b - ., 4b - .\n> #endif\n> \t.popsection\n> \n> diff --git a/arch/arm/kernel/swp_emulate.c b/arch/arm/kernel/swp_emulate.c\n> index 3bda08bee674..a783e9c0b266 100644\n> --- a/arch/arm/kernel/swp_emulate.c\n> +++ b/arch/arm/kernel/swp_emulate.c\n> @@ -50,8 +50,8 @@\n> \t\"\t.previous\\n\"\t\t\t\t\t\\\n> \t\"\t.section\t __ex_table,\\\"a\\\"\\n\"\t\t\\\n> \t\"\t.align\t\t3\\n\"\t\t\t\t\\\n> -\t\"\t.long\t\t0b, 3b\\n\"\t\t\t\\\n> -\t\"\t.long\t\t1b, 3b\\n\"\t\t\t\\\n> +\t\"\t.long\t\t0b - ., 3b - .\\n\"\t\t\\\n> +\t\"\t.long\t\t1b - ., 3b - .\\n\"\t\t\\\n> \t\"\t.previous\"\t\t\t\t\t\\\n> \t: \"=&r\" (res), \"+r\" (data), \"=&r\" (temp)\t\t\\\n> \t: \"r\" (addr), \"i\" (-EAGAIN), \"i\" (-EFAULT)\t\t\\\n> diff --git a/arch/arm/lib/backtrace.S b/arch/arm/lib/backtrace.S\n> index 7d7952e5a3b1..84a8df7aa63c 100644\n> --- a/arch/arm/lib/backtrace.S\n> +++ b/arch/arm/lib/backtrace.S\n> @@ -107,10 +107,10 @@ ENDPROC(c_backtrace)\n> \t\t\n> \t\t.pushsection __ex_table,\"a\"\n> \t\t.align\t3\n> -\t\t.long\t1001b, 1006b\n> -\t\t.long\t1002b, 1006b\n> -\t\t.long\t1003b, 1006b\n> -\t\t.long\t1004b, 1006b\n> +\t\t.long\t1001b - ., 1006b - .\n> +\t\t.long\t1002b - ., 1006b - .\n> +\t\t.long\t1003b - ., 1006b - .\n> +\t\t.long\t1004b - ., 1006b - .\n> \t\t.popsection\n> \n> .Lbad:\t\t.asciz\t\"Backtrace aborted due to bad frame pointer <%p>\\n\"\n> diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S\n> index df73914e81c8..d47b4776d308 100644\n> --- a/arch/arm/lib/getuser.S\n> +++ b/arch/arm/lib/getuser.S\n> @@ -133,17 +133,17 @@ ENDPROC(__get_user_bad)\n> ENDPROC(__get_user_bad8)\n> \n> .pushsection __ex_table, \"a\"\n> -\t.long\t1b, __get_user_bad\n> -\t.long\t2b, __get_user_bad\n> -\t.long\t3b, __get_user_bad\n> -\t.long\t4b, __get_user_bad\n> -\t.long\t5b, __get_user_bad8\n> -\t.long\t6b, __get_user_bad8\n> +\t.long\t1b - ., __get_user_bad - .\n> +\t.long\t2b - ., __get_user_bad - .\n> +\t.long\t3b - ., __get_user_bad - .\n> +\t.long\t4b - ., __get_user_bad - .\n> +\t.long\t5b - ., __get_user_bad8 - .\n> +\t.long\t6b - ., __get_user_bad8 - .\n> #ifdef __ARMEB__\n> -\t.long 7b, __get_user_bad\n> -\t.long\t8b, __get_user_bad8\n> -\t.long\t9b, __get_user_bad8\n> -\t.long\t10b, __get_user_bad8\n> -\t.long\t11b, __get_user_bad8\n> +\t.long 7b - ., __get_user_bad - .\n> +\t.long\t8b - ., __get_user_bad8 - .\n> +\t.long\t9b - ., __get_user_bad8 - .\n> +\t.long\t10b - ., __get_user_bad8 - .\n> +\t.long\t11b - ., __get_user_bad8 - .\n> #endif\n> .popsection\n> diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S\n> index 38d660d3705f..6b854197ff48 100644\n> --- a/arch/arm/lib/putuser.S\n> +++ b/arch/arm/lib/putuser.S\n> @@ -89,10 +89,10 @@ __put_user_bad:\n> ENDPROC(__put_user_bad)\n> \n> .pushsection __ex_table, \"a\"\n> -\t.long\t1b, __put_user_bad\n> -\t.long\t2b, __put_user_bad\n> -\t.long\t3b, __put_user_bad\n> -\t.long\t4b, __put_user_bad\n> -\t.long\t5b, __put_user_bad\n> -\t.long\t6b, __put_user_bad\n> +\t.long\t1b - ., __put_user_bad - .\n> +\t.long\t2b - ., __put_user_bad - .\n> +\t.long\t3b - ., __put_user_bad - .\n> +\t.long\t4b - ., __put_user_bad - .\n> +\t.long\t5b - ., __put_user_bad - .\n> +\t.long\t6b - ., __put_user_bad - .\n> .popsection\n> diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c\n> index 2c96190e018b..2c74cb826b6a 100644\n> --- a/arch/arm/mm/alignment.c\n> +++ b/arch/arm/mm/alignment.c\n> @@ -209,7 +209,7 @@ union offset_union {\n> \t\"\t.popsection\\n\"\t\t\t\t\\\n> \t\"\t.pushsection __ex_table,\\\"a\\\"\\n\"\t\\\n> \t\"\t.align\t3\\n\"\t\t\t\t\\\n> -\t\"\t.long\t1b, 3b\\n\"\t\t\t\\\n> +\t\"\t.long\t1b - ., 3b - .\\n\"\t\t\\\n> \t\"\t.popsection\\n\"\t\t\t\t\\\n> \t: \"=r\" (err), \"=&r\" (val), \"=r\" (addr)\t\t\\\n> \t: \"0\" (err), \"2\" (addr))\n> @@ -269,8 +269,8 @@ union offset_union {\n> \t\t\"\t.popsection\\n\"\t\t\t\t\\\n> \t\t\"\t.pushsection __ex_table,\\\"a\\\"\\n\"\t\\\n> \t\t\"\t.align\t3\\n\"\t\t\t\t\\\n> -\t\t\"\t.long\t1b, 4b\\n\"\t\t\t\\\n> -\t\t\"\t.long\t2b, 4b\\n\"\t\t\t\\\n> +\t\t\"\t.long\t1b - ., 4b - .\\n\"\t\t\\\n> +\t\t\"\t.long\t2b - ., 4b - .\\n\"\t\t\\\n> \t\t\"\t.popsection\\n\"\t\t\t\t\\\n> \t\t: \"=r\" (err), \"=&r\" (v), \"=&r\" (a)\t\t\\\n> \t\t: \"0\" (err), \"1\" (v), \"2\" (a));\t\t\t\\\n> @@ -309,10 +309,10 @@ union offset_union {\n> \t\t\"\t.popsection\\n\"\t\t\t\t\\\n> \t\t\"\t.pushsection __ex_table,\\\"a\\\"\\n\"\t\\\n> \t\t\"\t.align\t3\\n\"\t\t\t\t\\\n> -\t\t\"\t.long\t1b, 6b\\n\"\t\t\t\\\n> -\t\t\"\t.long\t2b, 6b\\n\"\t\t\t\\\n> -\t\t\"\t.long\t3b, 6b\\n\"\t\t\t\\\n> -\t\t\"\t.long\t4b, 6b\\n\"\t\t\t\\\n> +\t\t\"\t.long\t1b - ., 6b - .\\n\"\t\t\\\n> +\t\t\"\t.long\t2b - ., 6b - .\\n\"\t\t\\\n> +\t\t\"\t.long\t3b - ., 6b - .\\n\"\t\t\\\n> +\t\t\"\t.long\t4b - ., 6b - .\\n\"\t\t\\\n> \t\t\"\t.popsection\\n\"\t\t\t\t\\\n> \t\t: \"=r\" (err), \"=&r\" (v), \"=&r\" (a)\t\t\\\n> \t\t: \"0\" (err), \"1\" (v), \"2\" (a));\t\t\t\\\n> diff --git a/arch/arm/mm/extable.c b/arch/arm/mm/extable.c\n> index f436f7439e46..6a8b85bf0cac 100644\n> --- a/arch/arm/mm/extable.c\n> +++ b/arch/arm/mm/extable.c\n> @@ -10,7 +10,7 @@ int fixup_exception(struct pt_regs *regs)\n> \n> \tfixup = search_exception_tables(instruction_pointer(regs));\n> \tif (fixup) {\n> -\t\tregs->ARM_pc = fixup->fixup;\n> +\t\tregs->ARM_pc = (unsigned long)&fixup->fixup + fixup->fixup;\n> #ifdef CONFIG_THUMB2_KERNEL\n> \t\t/* Clear the IT state to avoid nasty surprises in the fixup */\n> \t\tregs->ARM_cpsr &= ~PSR_IT_MASK;\n> diff --git a/arch/arm/nwfpe/entry.S b/arch/arm/nwfpe/entry.S\n> index 39c20afad7ed..c4fe13b31705 100644\n> --- a/arch/arm/nwfpe/entry.S\n> +++ b/arch/arm/nwfpe/entry.S\n> @@ -121,5 +121,5 @@ next:\n> \n> \t.pushsection __ex_table,\"a\"\n> \t.align\t3\n> -\t.long\t.Lx1, .Lfix\n> +\t.long\t.Lx1 - ., .Lfix - .\n> \t.popsection\n> diff --git a/scripts/sortextable.c b/scripts/sortextable.c\n> index 365a907f98b3..56a4c6714da7 100644\n> --- a/scripts/sortextable.c\n> +++ b/scripts/sortextable.c\n> @@ -314,6 +314,7 @@ do_file(char const *const fname)\n> \t\tbreak;\n> \n> \tcase EM_S390:\n> +\tcase EM_ARM:\n> \tcase EM_AARCH64:\n> \tcase EM_PARISC:\n> \tcase EM_PPC:\n> @@ -322,7 +323,6 @@ do_file(char const *const fname)\n> \t\tbreak;\n> \tcase EM_ARCOMPACT:\n> \tcase EM_ARCV2:\n> -\tcase EM_ARM:\n> \tcase EM_MICROBLAZE:\n> \tcase EM_MIPS:\n> \tcase EM_XTENSA:\n> -- \n> 2.11.0\n> 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16/29] ARM: kernel: switch to relative exception\n\ttables","In-Reply-To":"<20170903120757.14968-17-ard.biesheuvel@linaro.org>","Message-ID":"","References":"<20170903120757.14968-1-ard.biesheuvel@linaro.org>\n\t<20170903120757.14968-17-ard.biesheuvel@linaro.org>","User-Agent":"Alpine 2.21 (LFD 202 2017-01-01)","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170904_101803_422242_0E93D67A ","X-CRM114-Status":"GOOD ( 20.77 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Mark Rutland , Kees Cook , \n\tArnd Bergmann , kernel-hardening@lists.openwall.com,\n\tMarc Zyngier ,\n\tRussell King , \n\tDave Martin , Tony Lindgren , \n\tMatt Fleming ,\n\tThomas Garnier , \n\tlinux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762803,"web_url":"http://patchwork.ozlabs.org/comment/1762803/","msgid":"","list_archive_url":null,"date":"2017-09-04T17:01:33","subject":"Re: [PATCH v2 15/29] arm-soc: various: replace open coded VA->PA\n\tcalculation of pen_release","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> This replaces a few copies of the open coded calculations of the\n> physical address of 'pen_release' in the secondary startup code\n> of a couple of platforms. This ensures these quantities are invariant\n> under runtime relocation.\n> \n> Cc: Russell King \n> Signed-off-by: Ard Biesheuvel \nAcked-by: Nicolas Pitre \n\n\n> ---\n> arch/arm/mach-prima2/headsmp.S | 11 +++--------\n> arch/arm/mach-spear/headsmp.S | 11 +++--------\n> arch/arm/mach-sti/headsmp.S | 10 +++-------\n> arch/arm/plat-versatile/headsmp.S | 9 +--------\n> 4 files changed, 10 insertions(+), 31 deletions(-)\n> \n> diff --git a/arch/arm/mach-prima2/headsmp.S b/arch/arm/mach-prima2/headsmp.S\n> index 209d9fc5c16c..070df700bb38 100644\n> --- a/arch/arm/mach-prima2/headsmp.S\n> +++ b/arch/arm/mach-prima2/headsmp.S\n> @@ -9,6 +9,8 @@\n> #include \n> #include \n> \n> +#include \n> +\n> /*\n> * SIRFSOC specific entry point for secondary CPUs. This provides\n> * a \"holding pen\" into which all secondary cores are held until we're\n> @@ -17,10 +19,7 @@\n> ENTRY(sirfsoc_secondary_startup)\n> mrc p15, 0, r0, c0, c0, 5\n> and r0, r0, #15\n> - adr r4, 1f\n> - ldmia r4, {r5, r6}\n> - sub r4, r4, r5\n> - add r6, r6, r4\n> + adr_l r6, pen_release\n> pen: ldr r7, [r6]\n> cmp r7, r0\n> bne pen\n> @@ -31,7 +30,3 @@ pen: ldr r7, [r6]\n> */\n> b secondary_startup\n> ENDPROC(sirfsoc_secondary_startup)\n> -\n> - .align\n> -1: .long .\n> - .long pen_release\n> diff --git a/arch/arm/mach-spear/headsmp.S b/arch/arm/mach-spear/headsmp.S\n> index c52192dc3d9f..4da01b103f33 100644\n> --- a/arch/arm/mach-spear/headsmp.S\n> +++ b/arch/arm/mach-spear/headsmp.S\n> @@ -13,6 +13,8 @@\n> #include \n> #include \n> \n> +#include \n> +\n> \t__INIT\n> \n> /*\n> @@ -23,10 +25,7 @@\n> ENTRY(spear13xx_secondary_startup)\n> \tmrc\tp15, 0, r0, c0, c0, 5\n> \tand\tr0, r0, #15\n> -\tadr\tr4, 1f\n> -\tldmia\tr4, {r5, r6}\n> -\tsub\tr4, r4, r5\n> -\tadd\tr6, r6, r4\n> +\tadr_l\tr6, pen_release\n> pen:\tldr\tr7, [r6]\n> \tcmp\tr7, r0\n> \tbne\tpen\n> @@ -40,8 +39,4 @@ pen:\tldr\tr7, [r6]\n> \t * should now contain the SVC stack for this core\n> \t */\n> \tb\tsecondary_startup\n> -\n> -\t.align\n> -1:\t.long\t.\n> -\t.long\tpen_release\n> ENDPROC(spear13xx_secondary_startup)\n> diff --git a/arch/arm/mach-sti/headsmp.S b/arch/arm/mach-sti/headsmp.S\n> index e0ad451700d5..cdf3442f397b 100644\n> --- a/arch/arm/mach-sti/headsmp.S\n> +++ b/arch/arm/mach-sti/headsmp.S\n> @@ -16,6 +16,8 @@\n> #include \n> #include \n> \n> +#include \n> +\n> /*\n> * ST specific entry point for secondary CPUs. This provides\n> * a \"holding pen\" into which all secondary cores are held until we're\n> @@ -24,10 +26,7 @@\n> ENTRY(sti_secondary_startup)\n> \tmrc\tp15, 0, r0, c0, c0, 5\n> \tand\tr0, r0, #15\n> -\tadr\tr4, 1f\n> -\tldmia\tr4, {r5, r6}\n> -\tsub\tr4, r4, r5\n> -\tadd\tr6, r6, r4\n> +\tadr_l\tr6, pen_release\n> pen:\tldr\tr7, [r6]\n> \tcmp\tr7, r0\n> \tbne\tpen\n> @@ -38,6 +37,3 @@ pen:\tldr\tr7, [r6]\n> \t */\n> \tb\tsecondary_startup\n> ENDPROC(sti_secondary_startup)\n> -\n> -1:\t.long\t.\n> -\t.long\tpen_release\n> diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S\n> index 40f27e52de75..0f2a5eddac5a 100644\n> --- a/arch/arm/plat-versatile/headsmp.S\n> +++ b/arch/arm/plat-versatile/headsmp.S\n> @@ -21,10 +21,7 @@ ENTRY(versatile_secondary_startup)\n> ARM_BE8(setend\tbe)\n> \tmrc\tp15, 0, r0, c0, c0, 5\n> \tbic\tr0, #0xff000000\n> -\tadr\tr4, 1f\n> -\tldmia\tr4, {r5, r6}\n> -\tsub\tr4, r4, r5\n> -\tadd\tr6, r6, r4\n> +\tadr_l\tr6, pen_release\n> pen:\tldr\tr7, [r6]\n> \tcmp\tr7, r0\n> \tbne\tpen\n> @@ -34,8 +31,4 @@ pen:\tldr\tr7, [r6]\n> \t * should now contain the SVC stack for this core\n> \t */\n> \tb\tsecondary_startup\n> -\n> -\t.align\n> -1:\t.long\t.\n> -\t.long\tpen_release\n> ENDPROC(versatile_secondary_startup)\n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762805,"web_url":"http://patchwork.ozlabs.org/comment/1762805/","msgid":"","list_archive_url":null,"date":"2017-09-04T17:30:26","subject":"Re: [PATCH v2 16/29] ARM: kernel: switch to relative exception\n\ttables","submitter":{"id":26857,"url":"http://patchwork.ozlabs.org/api/people/26857/","name":"Ard Biesheuvel","email":"ard.biesheuvel@linaro.org"},"content":"On 4 September 2017 at 18:17, Nicolas Pitre wrote:\n> On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n>\n>> To avoid having to relocate the contents of extable entries at\n>> runtime when running with KASLR enabled, wire up the existing\n>> support for emitting them as relative references. This ensures\n>> these quantities are invariant under runtime relocation.\n>>\n>> Cc: Russell King \n>> Signed-off-by: Ard Biesheuvel \n>\n> Could it be better to have a macro that encapsulates exception entries\n> e.g.:\n>\n> .macro ex_entry insn fixup\n> .long \\insn - ., \\fixup - .\n> .endif\n>\n> so that if ever this changes again or for whatever reason someone needs\n> absolute entries then this won't have to be done everywhere. The section\n> switch could be included in such a macro too. And it is so easy to\n> forget to do the \"- .\" when adding new entries.\n>\n\nGood point. I will change that.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"kfIJH6yG\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"iAjY9r49\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xmH1q4zvYz9t39\n\tfor ;\n\tTue, 5 Sep 2017 03:30:55 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dovD1-0000Ai-OE; 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\n\tMon, 04 Sep 2017 10:30:27 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"","References":"<20170903120757.14968-1-ard.biesheuvel@linaro.org>\n\t<20170903120757.14968-17-ard.biesheuvel@linaro.org>\n\t","From":"Ard Biesheuvel ","Date":"Mon, 4 Sep 2017 18:30:26 +0100","Message-ID":"","Subject":"Re: [PATCH v2 16/29] ARM: kernel: switch to relative exception\n\ttables","To":"Nicolas Pitre ","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170904_103048_007699_E80DE8C7 ","X-CRM114-Status":"GOOD ( 12.05 )","X-Spam-Score":"-2.7 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.7 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow\n\ttrust [2607:f8b0:4001:c06:0:0:0:234 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Mark Rutland , Kees Cook , \n\tArnd Bergmann ,\n\tKernel Hardening ,\n\tMarc Zyngier ,\n\tRussell King , \n\tDave Martin , Tony Lindgren , \n\tMatt Fleming ,\n\tThomas Garnier , \n\t\"linux-arm-kernel@lists.infradead.org\"\n\t","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762826,"web_url":"http://patchwork.ozlabs.org/comment/1762826/","msgid":"","list_archive_url":null,"date":"2017-09-04T18:03:00","subject":"Re: [PATCH v2 17/29] ARM: kernel: use relative phys-to-virt patch\n\ttables","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> Replace the contents of the __pv_table entries with relative references\n> so that we don't have to relocate them at runtime when running the KASLR\n> kernel. This ensures these quantities are invariant under runtime\n> relocation, which makes any cache maintenance after runtime relocation\n> unnecessary.\n> \n> Cc: Russell King \n> Signed-off-by: Ard Biesheuvel \n> ---\n> arch/arm/include/asm/memory.h | 6 +++---\n> arch/arm/kernel/head.S | 21 ++++++++++----------\n> 2 files changed, 13 insertions(+), 14 deletions(-)\n> \n> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h\n> index 1f54e4e98c1e..47a984e3a244 100644\n> --- a/arch/arm/include/asm/memory.h\n> +++ b/arch/arm/include/asm/memory.h\n> @@ -195,7 +195,7 @@ extern const void *__pv_table_begin, *__pv_table_end;\n> \t__asm__(\"@ __pv_stub\\n\"\t\t\t\t\\\n> \t\"1:\t\" instr \"\t%0, %1, %2\\n\"\t\t\\\n> \t\"\t.pushsection .pv_table,\\\"a\\\"\\n\"\t\t\\\n> -\t\"\t.long\t1b\\n\"\t\t\t\t\\\n> +\t\"\t.long\t1b - .\\n\"\t\t\t\\\n> \t\"\t.popsection\\n\"\t\t\t\t\\\n\n[...]\n\n> --- a/arch/arm/kernel/head.S\n> +++ b/arch/arm/kernel/head.S\n> @@ -612,22 +611,22 @@ __fixup_a_pv_table:\n> \torr\tr6, r6, r7, lsl #12\n> \torr\tr6, #0x4000\n> \tb\t2f\n> -1:\tadd r7, r3\n> -\tldrh\tip, [r7, #2]\n> +1:\tadd\tr7, r4\n> +\tldrh\tip, [r7, #-2]\n\nPlease use \"ldrh ip, [r7, #(-4 + 2)]\" so the -4 offset is clearly \nspelled out. The #-2 gave me a pause of confusion.\n\n> ARM_BE8(rev16\tip, ip)\n> \ttst\tip, #0x4000\n> \tand\tip, #0x8f00\n> \torrne\tip, r6\t@ mask in offset bits 31-24\n> \torreq\tip, r0\t@ mask in offset bits 7-0\n> ARM_BE8(rev16\tip, ip)\n> -\tstrh\tip, [r7, #2]\n> +\tstrh\tip, [r7, #-2]\n\nDitto here.\n\n> \tbne\t2f\n> -\tldrh\tip, [r7]\n> +\tldrh\tip, [r7, #-4]\n\nAnd to be clear, here I'd use \"#(-4 + 0)\" to be explicit.\n\n> ARM_BE8(rev16\tip, ip)\n> \tbic\tip, #0x20\n> \torr\tip, ip, r0, lsr #16\n> ARM_BE8(rev16\tip, ip)\n> -\tstrh\tip, [r7]\n> +\tstrh\tip, [r7, #-4]\n\nAnd so here.\n\n\nWith that:\n\nReviewed-by: Nicolas Pitre \n\n\n> 2:\tcmp\tr4, r5\n> \tldrcc\tr7, [r4], #4\t@ use branch for delay slot\n> \tbcc\t1b\n> @@ -639,7 +638,8 @@ ARM_BE8(rev16\tip, ip)\n> \tmoveq\tr0, #0x400000\t@ set bit 22, mov to mvn instruction\n> #endif\n> \tb\t2f\n> -1:\tldr\tip, [r7, r3]\n> +1:\tldr\tip, [r7, r4]!\n> +\tadd\tr4, r4, #4\n> #ifdef CONFIG_CPU_ENDIAN_BE8\n> \t@ in BE8, we load data in BE, but instructions still in LE\n> \tbic\tip, ip, #0xff000000\n> @@ -654,9 +654,9 @@ ARM_BE8(rev16\tip, ip)\n> \tbiceq\tip, ip, #0x400000\t@ clear bit 22\n> \torreq\tip, ip, r0\t@ mask in offset bits 7-0\n> #endif\n> -\tstr\tip, [r7, r3]\n> +\tstr\tip, [r7]\n> 2:\tcmp\tr4, r5\n> -\tldrcc\tr7, [r4], #4\t@ use branch for delay slot\n> +\tldrcc\tr7, [r4]\t@ use branch for delay slot\n> \tbcc\t1b\n> \tret\tlr\n> #endif\n> @@ -664,7 +664,6 @@ ENDPROC(__fixup_a_pv_table)\n> \n> ENTRY(fixup_pv_table)\n> \tstmfd\tsp!, {r4 - r7, lr}\n> -\tmov\tr3, #0\t\t\t@ no offset\n> \tmov\tr4, r0\t\t\t@ r0 = table start\n> \tadd\tr5, r0, r1\t\t@ r1 = table size\n> \tbl\t__fixup_a_pv_table\n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762828,"web_url":"http://patchwork.ozlabs.org/comment/1762828/","msgid":"","list_archive_url":null,"date":"2017-09-04T18:11:30","subject":"Re: [PATCH v2 19/29] ARM: kernel: make vmlinux buildable as a PIE\n\texecutable","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> Update the build flags and linker script to allow vmlinux to be built\n> as a PIE binary, which retains relocation information about absolute\n> symbol references so that they can be fixed up at runtime. This will\n> be used for implementing KASLR,\n> \n> Cc: Russell King \n> Signed-off-by: Ard Biesheuvel \n> ---\n> arch/arm/Kconfig | 4 ++++\n> arch/arm/Makefile | 5 +++++\n> arch/arm/include/asm/assembler.h | 2 +-\n> arch/arm/kernel/vmlinux.lds.S | 9 +++++++++\n> include/linux/hidden.h | 20 ++++++++++++++++++++\n> scripts/module-common.lds | 1 +\n> 6 files changed, 40 insertions(+), 1 deletion(-)\n> \n> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\n> index 61a0cb15067e..300add3b8023 100644\n> --- a/arch/arm/Kconfig\n> +++ b/arch/arm/Kconfig\n> @@ -2085,6 +2085,10 @@ config DMI\n> \t firmware need to be enabled. This would require the DMI subsystem\n> \t to be enabled much earlier than we do on ARM, which is non-trivial.\n> \n> +config RELOCATABLE\n> +\tbool\n> +\tselect HAVE_ARCH_PREL32_RELOCATIONS\n> +\n\nYou should probably make it depend on !XIP_KERNEL.\n\nOther than that\n\nAcked-by: Nicolas Pitre \n\n\n> \n> menu \"CPU Power Management\"\n> diff --git a/arch/arm/Makefile b/arch/arm/Makefile\n> index 47d3a1ab08d2..8544c8148b9f 100644\n> --- a/arch/arm/Makefile\n> +++ b/arch/arm/Makefile\n> @@ -52,6 +52,11 @@ AS\t\t+= -EL\n> LD\t\t+= -EL\n> endif\n> \n> +ifeq ($(CONFIG_RELOCATABLE),y)\n> +KBUILD_CFLAGS\t\t+= -fpic -include $(srctree)/include/linux/hidden.h\n> +LDFLAGS_vmlinux\t\t+= -pie -shared -Bsymbolic\n> +endif\n> +\n> #\n> # The Scalar Replacement of Aggregates (SRA) optimization pass in GCC 4.9 and\n> # later may result in code being generated that handles signed short and signed\n> diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h\n> index ae43859a9000..0586e1c77a80 100644\n> --- a/arch/arm/include/asm/assembler.h\n> +++ b/arch/arm/include/asm/assembler.h\n> @@ -555,7 +555,7 @@ THUMB(\torr\t\\reg , \\reg , #PSR_T_BIT\t)\n> \t * mov_l - move a constant value or [relocated] address into a register\n> \t */\n> \t.macro\t\tmov_l, dst:req, imm:req\n> -\t.if\t\t__LINUX_ARM_ARCH__ < 7\n> +\t.if\t\tCONFIG_RELOCATABLE == 1 || __LINUX_ARM_ARCH__ < 7\n> \tldr\t\t\\dst, =\\imm\n> \t.else\n> \tmovw\t\t\\dst, #:lower16:\\imm\n> diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S\n> index c83a7ba737d6..5853d4be2067 100644\n> --- a/arch/arm/kernel/vmlinux.lds.S\n> +++ b/arch/arm/kernel/vmlinux.lds.S\n> @@ -89,6 +89,9 @@ SECTIONS\n> #endif\n> \t\t*(.discard)\n> \t\t*(.discard.*)\n> +\t\t*(.ARM.exidx.discard.text)\n> +\t\t*(.interp .dynamic)\n> +\t\t*(.dynsym .dynstr .hash)\n> \t}\n> \n> \t. = PAGE_OFFSET + TEXT_OFFSET;\n> @@ -209,6 +212,12 @@ SECTIONS\n> \t\t__smpalt_end = .;\n> \t}\n> #endif\n> +\t.rel.dyn : ALIGN(8) {\n> +\t\t__rel_begin = .;\n> +\t\t*(.rel .rel.* .rel.dyn)\n> +\t}\n> +\t__rel_end = ADDR(.rel.dyn) + SIZEOF(.rel.dyn);\n> +\n> \t.init.pv_table : {\n> \t\t__pv_table_begin = .;\n> \t\t*(.pv_table)\n> diff --git a/include/linux/hidden.h b/include/linux/hidden.h\n> new file mode 100644\n> index 000000000000..781fb6f0c742\n> --- /dev/null\n> +++ b/include/linux/hidden.h\n> @@ -0,0 +1,20 @@\n> +/*\n> + * GCC assumes that we are building shared libraries or hosted binaries\n> + * when the -fpic or -fpie switches are used. This results in all references\n> + * to symbols with external linkage to be redirected via entries in the global\n> + * offset table (GOT), which keeps .text pages clean and reduces the footprint\n> + * of CoWed dirty pages to the GOT itself. It also allows symbol preemption,\n> + * which is mandatory under ELF rules for shared libraries.\n> + *\n> + * For the kernel, we use PIC so that we can relocate the executable image at\n> + * runtime. This does not involve CoW or symbol preemption, and we'd rather\n> + * have relative references instead of absolute ones whenever possible.\n> + * So set the default visibility to hidden: this informs the compiler that\n> + * none of our symbols will ever be exported from a shared library, allowing\n> + * it to use relative references where possible.\n> + *\n> + * Note that simply passing -fvisibility=hidden is not sufficient to achieve\n> + * this: In that case, definitions will be marked hidden, but declarations\n> + * will not, and we still end up with GOT entries unnecessarily.\n> + */\n> +#pragma GCC visibility push(hidden)\n> diff --git a/scripts/module-common.lds b/scripts/module-common.lds\n> index d61b9e8678e8..55bb41f32c8a 100644\n> --- a/scripts/module-common.lds\n> +++ b/scripts/module-common.lds\n> @@ -7,6 +7,7 @@ SECTIONS {\n> \t/DISCARD/ : {\n> \t\t*(.discard)\n> \t\t*(.discard.*)\n> +\t\t*(*.discard.*)\n> \t}\n> \n> \t__ksymtab\t\t0 : { *(SORT(___ksymtab+*)) }\n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762829,"web_url":"http://patchwork.ozlabs.org/comment/1762829/","msgid":"","list_archive_url":null,"date":"2017-09-04T18:15:02","subject":"Re: [PATCH v2 20/29] ARM: kernel: use PC-relative symbol references\n\tin MMU switch code","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> To prepare for adding support for KASLR, which relocates all absolute\n> symbol references at runtime after the caches have been enabled,\n> update the MMU switch code to avoid using absolute symbol references\n> where possible. This ensures these quantities are invariant under\n> runtime relocation.\n> \n> Cc: Russell King \n> Signed-off-by: Ard Biesheuvel \n> ---\n> arch/arm/kernel/head-common.S | 39 ++++++++------------\n> 1 file changed, 15 insertions(+), 24 deletions(-)\n> \n> diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S\n> index 06035488130c..b74477507a12 100644\n> --- a/arch/arm/kernel/head-common.S\n> +++ b/arch/arm/kernel/head-common.S\n> @@ -79,9 +79,10 @@ ENDPROC(__vet_atags)\n> */\n> \t__INIT\n> __mmap_switched:\n> -\tadr\tr3, __mmap_switched_data\n> -\n> -\tldmia\tr3!, {r4, r5, r6, r7}\n> +\tadr_l\tr4, __data_loc\n> +\tadr_l\tr5, _sdata\n> +\tadr_l\tr6, __bss_start\n> +\tadr_l\tr7, _end\n> \tcmp\tr4, r5\t\t\t\t@ Copy data segment if needed\n> 1:\tcmpne\tr5, r6\n> \tldrne\tfp, [r4], #4\n> @@ -93,9 +94,17 @@ __mmap_switched:\n> \tstrcc\tfp, [r6],#4\n> \tbcc\t1b\n> \n> - ARM(\tldmia\tr3, {r4, r5, r6, r7, sp})\n> - THUMB(\tldmia\tr3, {r4, r5, r6, r7}\t)\n> - THUMB(\tldr\tsp, [r3, #16]\t\t)\n> +\tadr_l\tr3, init_thread_union + THREAD_START_SP\n> +\tmov\tsp, r3\n> +\tadr_l\tr4, processor_id\n> +\tadr_l\tr5, __machine_arch_type\n> +\tadr_l\tr6, __atags_pointer\n> +#ifdef CONFIG_CPU_CP15\n> +\tadr_l\tr7, cr_alignment\n> +#else\n> +\tmov\tr7, #0\n> +#endif\n\nThe code that follows is testing for a non-zero r7 value to store r0 so \nyou could make that code conditional rather than loading 0 here.\n\n> +\n> \tstr\tr9, [r4]\t\t\t@ Save processor ID\n> \tstr\tr1, [r5]\t\t\t@ Save machine type\n> \tstr\tr2, [r6]\t\t\t@ Save atags pointer\n> @@ -104,24 +113,6 @@ __mmap_switched:\n> \tb\tstart_kernel\n> ENDPROC(__mmap_switched)\n> \n> -\t.align\t2\n> -\t.type\t__mmap_switched_data, %object\n> -__mmap_switched_data:\n> -\t.long\t__data_loc\t\t\t@ r4\n> -\t.long\t_sdata\t\t\t\t@ r5\n> -\t.long\t__bss_start\t\t\t@ r6\n> -\t.long\t_end\t\t\t\t@ r7\n> -\t.long\tprocessor_id\t\t\t@ r4\n> -\t.long\t__machine_arch_type\t\t@ r5\n> -\t.long\t__atags_pointer\t\t\t@ r6\n> -#ifdef CONFIG_CPU_CP15\n> -\t.long\tcr_alignment\t\t\t@ r7\n> -#else\n> -\t.long\t0\t\t\t\t@ r7\n> -#endif\n> -\t.long\tinit_thread_union + THREAD_START_SP @ sp\n> -\t.size\t__mmap_switched_data, . - __mmap_switched_data\n> -\n> /*\n> * This provides a C-API version of __lookup_processor_type\n> */\n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762831,"web_url":"http://patchwork.ozlabs.org/comment/1762831/","msgid":"","list_archive_url":null,"date":"2017-09-04T18:24:36","subject":"Re: [PATCH v2 21/29] ARM: kernel: use PC relative symbol references\n\tin suspend/resume code","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> Replace some unnecessary absolute references with relative ones. Also,\n> to prepare for runtime relocation, which occurs with the caches on,\n> defer taking the absolute address of cpu_resume_after_mmu() until after\n> the MMU is enabled.\n> \n> Cc: Russell King \n> Signed-off-by: Ard Biesheuvel \n\nWhat's the point of that last hunk? I understand you load the address \nafter the mMU is on. But you should be coming back from a sleep and \ncaches ought to be clean at that point. Not that it is a bad thing to do \nbut I don't understand your reason for it.\n\n\n> ---\n> arch/arm/kernel/sleep.S | 9 ++++-----\n> 1 file changed, 4 insertions(+), 5 deletions(-)\n> \n> diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S\n> index f4920b5d0fc4..5b02744f2f12 100644\n> --- a/arch/arm/kernel/sleep.S\n> +++ b/arch/arm/kernel/sleep.S\n> @@ -60,15 +60,14 @@\n> ENTRY(__cpu_suspend)\n> \tstmfd\tsp!, {r4 - r11, lr}\n> #ifdef MULTI_CPU\n> -\tldr\tr10, =processor\n> -\tldr\tr4, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state\n> +\tldr_l\tr4, processor + CPU_SLEEP_SIZE\t@ size of CPU sleep state\n> #else\n> -\tldr\tr4, =cpu_suspend_size\n> +\tadr_l\tr4, cpu_suspend_size\n> #endif\n> \tmov\tr5, sp\t\t\t@ current virtual SP\n> \tadd\tr4, r4, #12\t\t@ Space for pgd, virt sp, phys resume fn\n> \tsub\tsp, sp, r4\t\t@ allocate CPU state on stack\n> -\tldr\tr3, =sleep_save_sp\n> +\tadr_l\tr3, sleep_save_sp\n> \tstmfd\tsp!, {r0, r1}\t\t@ save suspend func arg and pointer\n> \tldr\tr3, [r3, #SLEEP_SAVE_SP_VIRT]\n> \tALT_SMP(W(nop))\t\t\t@ don't use adr_l inside ALT_SMP()\n> @@ -101,13 +100,13 @@ ENDPROC(cpu_suspend_abort)\n> \t.align\t5\n> \t.pushsection\t.idmap.text,\"ax\"\n> ENTRY(cpu_resume_mmu)\n> -\tldr\tr3, =cpu_resume_after_mmu\n> \tinstr_sync\n> \tmcr\tp15, 0, r0, c1, c0, 0\t@ turn on MMU, I-cache, etc\n> \tmrc\tp15, 0, r0, c0, c0, 0\t@ read id reg\n> \tinstr_sync\n> \tmov\tr0, r0\n> \tmov\tr0, r0\n> +\tldr\tr3, =cpu_resume_after_mmu\n> \tret\tr3\t\t\t@ jump to virtual address\n> ENDPROC(cpu_resume_mmu)\n> \t.popsection\n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762832,"web_url":"http://patchwork.ozlabs.org/comment/1762832/","msgid":"","list_archive_url":null,"date":"2017-09-04T18:25:13","subject":"Re: [PATCH v2 22/29] ARM: mm: export default vmalloc base address","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> In order for the EFI stub to be able to decide over what range to\n> randomize the load address of the kernel, expose the definition of\n> the default vmalloc base address as VMALLOC_DEFAULT_BASE.\n> \n> Cc: Russell King \n> Signed-off-by: Ard Biesheuvel \n\nAcked-by: Nicolas Pitre \n\n> ---\n> arch/arm/include/asm/pgtable.h | 1 +\n> arch/arm/mm/mmu.c | 3 +--\n> 2 files changed, 2 insertions(+), 2 deletions(-)\n> \n> diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h\n> index 1c462381c225..a0d4a63a6516 100644\n> --- a/arch/arm/include/asm/pgtable.h\n> +++ b/arch/arm/include/asm/pgtable.h\n> @@ -45,6 +45,7 @@\n> #define VMALLOC_OFFSET\t\t(8*1024*1024)\n> #define VMALLOC_START\t\t(((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))\n> #define VMALLOC_END\t\t0xff800000UL\n> +#define VMALLOC_DEFAULT_BASE\t(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET)\n> \n> #define LIBRARY_TEXT_START\t0x0c000000\n> \n> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c\n> index e46a6a446cdd..566f7e657931 100644\n> --- a/arch/arm/mm/mmu.c\n> +++ b/arch/arm/mm/mmu.c\n> @@ -1128,8 +1128,7 @@ void __init debug_ll_io_init(void)\n> }\n> #endif\n> \n> -static void * __initdata vmalloc_min =\n> -\t(void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);\n> +static void * __initdata vmalloc_min = (void *)VMALLOC_DEFAULT_BASE;\n> \n> /*\n> * vmalloc=size forces the vmalloc area to be exactly 'size'\n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762834,"web_url":"http://patchwork.ozlabs.org/comment/1762834/","msgid":"","list_archive_url":null,"date":"2017-09-04T18:30:13","subject":"Re: [PATCH v2 23/29] ARM: kernel: refer to swapper_pg_dir via its\n\tsymbol","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> The location of swapper_pg_dir is relative to the kernel, not to\n> PAGE_OFFSET or PHYS_OFFSET. So define the symbol relative to the\n> start of the kernel image, and refer to it via its name.\n\nCould it cause a section access mismatch if defined in the __HEAD \nsection?\n\nOtherwise\n\nAcked-by: Nicolas Pitre \n\n> \n> Cc: Russell King \n> Signed-off-by: Ard Biesheuvel \n> ---\n> arch/arm/kernel/head.S | 13 ++++---------\n> 1 file changed, 4 insertions(+), 9 deletions(-)\n> \n> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S\n> index 5d685e86148c..71bc0d037bc9 100644\n> --- a/arch/arm/kernel/head.S\n> +++ b/arch/arm/kernel/head.S\n> @@ -48,14 +48,6 @@\n> #define PMD_ORDER\t2\n> #endif\n> \n> -\t.globl\tswapper_pg_dir\n> -\t.equ\tswapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE\n> -\n> -\t.macro\tpgtbl, rd, phys\n> -\tadd\t\\rd, \\phys, #TEXT_OFFSET\n> -\tsub\t\\rd, \\rd, #PG_DIR_SIZE\n> -\t.endm\n> -\n> /*\n> * Kernel startup entry point.\n> * ---------------------------\n> @@ -77,6 +69,9 @@\n> \t.arm\n> \n> \t__HEAD\n> +\t.globl\tswapper_pg_dir\n> +\t.equ\tswapper_pg_dir, . - PG_DIR_SIZE\n> +\n> ENTRY(stext)\n> ARM_BE8(setend\tbe )\t\t\t@ ensure we are in BE8 mode\n> \n> @@ -172,7 +167,7 @@ ENDPROC(stext)\n> * r4 = physical page table address\n> */\n> __create_page_tables:\n> -\tpgtbl\tr4, r8\t\t\t\t@ page table address\n> +\tadr_l\tr4, swapper_pg_dir\t\t@ page table address\n> \n> \t/*\n> \t * Clear the swapper page table\n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762836,"web_url":"http://patchwork.ozlabs.org/comment/1762836/","msgid":"","list_archive_url":null,"date":"2017-09-04T18:44:15","subject":"Re: [PATCH v2 24/29] ARM: kernel: implement randomization of the\n\tkernel load address","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> This implements randomization of the placement of the kernel image\n> inside the lowmem region. It is intended to work together with the\n> decompressor to place the kernel at an offset in physical memory\n> that is a multiple of 2 MB, and to take the same offset into account\n> when creating the virtual mapping.\n> \n> This uses runtime relocation of the kernel built as a PIE binary, to\n> fix up all absolute symbol references to refer to their runtime virtual\n> address. The physical-to-virtual mapping remains unchanged.\n> \n> In order to allow the decompressor to hand over to the core kernel\n> without making assumptions that are not guaranteed to hold when\n> invoking the core kernel directly using bootloaders that are not\n> KASLR aware, the KASLR offset is expected to be placed in r3 when\n> entering the kernel 4 bytes past the entry point, skipping the first\n> instruction.\n> \n> Cc: Russell King \n> Signed-off-by: Ard Biesheuvel \n> ---\n> arch/arm/Kconfig | 15 +++\n> arch/arm/kernel/head.S | 103 ++++++++++++++++++--\n> 2 files changed, 109 insertions(+), 9 deletions(-)\n> \n> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\n> index 300add3b8023..fe4a2cd1f15c 100644\n> --- a/arch/arm/Kconfig\n> +++ b/arch/arm/Kconfig\n> @@ -1825,6 +1825,21 @@ config XEN\n> \thelp\n> \t Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.\n> \n> +config RANDOMIZE_BASE\n> +\tbool \"Randomize the address of the kernel image\"\n> +\tdepends on MMU && AUTO_ZRELADDR\n> +\tdepends on !XIP_KERNEL && !ZBOOT_ROM\n\nThis should work even if ZBOOT_ROM is selected. The ZBOOT_ROM option \nallows for the decompressor executing directly from ROM and \ndecompressing the kernel anywhere in RAM.\n\n\n> +\tselect RELOCATABLE\n> +\thelp\n> +\t Randomizes the virtual and physical address at which the kernel\n> +\t image is loaded, as a security feature that deters exploit attempts\n> +\t relying on knowledge of the location of kernel internals.\n> +\n> +\t This relies on the UEFI stub to invoke the EFI_RNG_PROTOCOL to\n> +\t randomize the load address of the decompressed kernel in the\n> +\t physical space. The same offset is applied to the virtual mapping\n> +\t of the kernel in the virtual space by the kernel proper.\n> +\n> endmenu\n> \n> menu \"Boot options\"\n> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S\n> index 71bc0d037bc9..0795da990dde 100644\n> --- a/arch/arm/kernel/head.S\n> +++ b/arch/arm/kernel/head.S\n> @@ -48,6 +48,28 @@\n> #define PMD_ORDER\t2\n> #endif\n> \n> +\t.macro\tget_kaslr_offset, reg\n> +#ifdef CONFIG_RANDOMIZE_BASE\n> +\tldr_l\t\t\t\\reg, __kaslr_offset\n> +#else\n> +\tmov\t\t\t\\reg, #0\n> +#endif\n> +\t.endm\n> +\n> +\t.macro\tadd_kaslr_offset, reg, tmp\n> +#ifdef CONFIG_RANDOMIZE_BASE\n> +\tget_kaslr_offset\t\\tmp\n> +\tadd\t\t\t\\reg, \\reg, \\tmp\n> +#endif\n> +\t.endm\n> +\n> +\t.macro\tsub_kaslr_offset, reg, tmp\n> +#ifdef CONFIG_RANDOMIZE_BASE\n> +\tget_kaslr_offset\t\\tmp\n> +\tsub\t\t\t\\reg, \\reg, \\tmp\n> +#endif\n> +\t.endm\n> +\n> /*\n> * Kernel startup entry point.\n> * ---------------------------\n> @@ -73,6 +95,7 @@\n> \t.equ\tswapper_pg_dir, . - PG_DIR_SIZE\n> \n> ENTRY(stext)\n> +\tmov\tr3, #0\t\t\t@ normal entry point - clear r3\n> ARM_BE8(setend\tbe )\t\t\t@ ensure we are in BE8 mode\n> \n> THUMB(\tbadr\tr9, 1f\t\t)\t@ Kernel is always entered in ARM.\n> @@ -80,6 +103,16 @@ ENTRY(stext)\n> THUMB(\t.thumb\t\t\t)\t@ switch to Thumb now.\n> THUMB(1:\t\t\t)\n> \n> +#ifdef CONFIG_RANDOMIZE_BASE\n> +\tstr_l\tr3, __kaslr_offset, r9\t@ offset in r3 if entered via kaslr ep\n> +\n> +\t.section \".bss\", \"aw\", %nobits\n> +\t.align\t2\n> +__kaslr_offset:\n> +\t.long\t0\t\t\t@ will be wiped before entering C code\n> +\t.previous\n> +#endif\n> +\n> #ifdef CONFIG_ARM_VIRT_EXT\n> \tbl\t__hyp_stub_install\n> #endif\n> @@ -103,6 +136,7 @@ ENTRY(stext)\n> #ifndef CONFIG_XIP_KERNEL\n> \tadr_l\tr8, _text\t\t\t@ __pa(_text)\n> \tsub\tr8, r8, #TEXT_OFFSET\t\t@ PHYS_OFFSET\n> +\tsub_kaslr_offset r8, r12\n> #else\n> \tldr\tr8, =PLAT_PHYS_OFFSET\t\t@ always constant in this case\n> #endif\n> @@ -139,8 +173,8 @@ ENTRY(stext)\n> \t * r0 will hold the CPU control register value, r1, r2, r4, and\n> \t * r9 will be preserved. r5 will also be preserved if LPAE.\n> \t */\n> -\tldr\tr13, =__mmap_switched\t\t@ address to jump to after\n> -\t\t\t\t\t\t@ mmu has been enabled\n> +\tadr_l\tlr, __primary_switch\t\t@ address to jump to after\n> +\tmov\tr13, lr\t\t\t\t@ mmu has been enabled\n> \tbadr\tlr, 1f\t\t\t\t@ return (PIC) address\n> #ifdef CONFIG_ARM_LPAE\n> \tmov\tr5, #0\t\t\t\t@ high TTBR0\n> @@ -151,7 +185,8 @@ ENTRY(stext)\n> \tldr\tr12, [r10, #PROCINFO_INITFUNC]\n> \tadd\tr12, r12, r10\n> \tret\tr12\n> -1:\tb\t__enable_mmu\n> +1:\tget_kaslr_offset r12\t\t\t@ get before turning MMU on\n> +\tb\t__enable_mmu\n> ENDPROC(stext)\n> \t.ltorg\n> \n> @@ -230,9 +265,14 @@ __create_page_tables:\n> \t/*\n> \t * Map our RAM from the start to the end of the kernel .bss section.\n> \t */\n> -\tadd\tr0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER)\n> -\tldr\tr6, =(_end - 1)\n> -\torr\tr3, r8, r7\n> +\tget_kaslr_offset r3\n> +\tadd\tr0, r3, #PAGE_OFFSET\n> +\tadd\tr0, r4, r0, lsr #(SECTION_SHIFT - PMD_ORDER)\n> +\tadr_l\tr6, _end - 1\n> +\tsub\tr6, r6, r8\n> +\tadd\tr6, r6, #PAGE_OFFSET\n> +\tadd\tr3, r3, r8\n> +\torr\tr3, r3, r7\n> \tadd\tr6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)\n> 1:\tstr\tr3, [r0], #1 << PMD_ORDER\n> \tadd\tr3, r3, #1 << SECTION_SHIFT\n> @@ -376,7 +416,7 @@ ENTRY(secondary_startup)\n> \t * Use the page tables supplied from __cpu_up.\n> \t */\n> \tadr_l\tr3, secondary_data\n> -\tmov_l\tr12, __secondary_switched\n> +\tadr_l\tr12, __secondary_switch\n> \tldrd\tr4, [r3, #0]\t\t\t@ get secondary_data.pgdir\n> ARM_BE8(eor\tr4, r4, r5)\t\t\t@ Swap r5 and r4 in BE:\n> ARM_BE8(eor\tr5, r4, r5)\t\t\t@ it can be done in 3 steps\n> @@ -414,6 +454,7 @@ ENDPROC(__secondary_switched)\n> * r4 = TTBR pointer (low word)\n> * r5 = TTBR pointer (high word if LPAE)\n> * r9 = processor ID\n> + * r12 = KASLR offset\n> * r13 = *virtual* address to jump to upon completion\n> */\n> __enable_mmu:\n> @@ -451,6 +492,7 @@ ENDPROC(__enable_mmu)\n> * r1 = machine ID\n> * r2 = atags or dtb pointer\n> * r9 = processor ID\n> + * r12 = KASLR offset\n> * r13 = *virtual* address to jump to upon completion\n> *\n> * other registers depend on the function called upon completion\n> @@ -466,10 +508,52 @@ ENTRY(__turn_mmu_on)\n> \tmov\tr3, r3\n> \tmov\tr3, r13\n> \tret\tr3\n> -__turn_mmu_on_end:\n> ENDPROC(__turn_mmu_on)\n> -\t.popsection\n> \n> +__primary_switch:\n> +#ifdef CONFIG_RELOCATABLE\n> +\tadr_l\tr7, _text\t\t\t@ r7 := __pa(_text)\n> +\tsub\tr7, r7, #TEXT_OFFSET\t\t@ r7 := PHYS_OFFSET\n> +\n> +\tadr_l\tr5, __rel_begin\n> +\tadr_l\tr6, __rel_end\n> +\tsub\tr5, r5, r7\n> +\tsub\tr6, r6, r7\n> +\n> +\tadd\tr5, r5, #PAGE_OFFSET\n> +\tadd\tr6, r6, #PAGE_OFFSET\n> +\tadd\tr5, r5, r12\n> +\tadd\tr6, r6, r12\n> +\n> +\tadr_l\tr3, __stubs_start\t\t@ __pa(__stubs_start)\n> +\tsub\tr3, r3, r7\t\t\t@ offset of __stubs_start\n> +\tadd\tr3, r3, #PAGE_OFFSET\t\t@ __va(__stubs_start)\n> +\tsub\tr3, r3, #0xffff1000\t\t@ subtract VA of stubs section\n> +\n> +0:\tcmp\tr5, r6\n> +\tbge\t1f\n> +\tldm\tr5!, {r7, r8}\t\t\t@ load next relocation entry\n> +\tcmp\tr8, #23\t\t\t\t@ R_ARM_RELATIVE\n> +\tbne\t0b\n> +\tcmp\tr7, #0xff000000\t\t\t@ vector page?\n> +\taddgt\tr7, r7, r3\t\t\t@ fix up VA offset\n> +\tldr\tr8, [r7, r12]\n> +\tadd\tr8, r8, r12\n> +\tstr\tr8, [r7, r12]\n> +\tb\t0b\n> +1:\n> +#endif\n> +\tldr\tpc, =__mmap_switched\n> +ENDPROC(__primary_switch)\n> +\n> +#ifdef CONFIG_SMP\n> +__secondary_switch:\n> +\tldr\tpc, =__secondary_switched\n> +ENDPROC(__secondary_switch)\n> +#endif\n> +\t.ltorg\n> +__turn_mmu_on_end:\n> +\t.popsection\n> \n> #ifdef CONFIG_SMP_ON_UP\n> \t__HEAD\n> @@ -570,6 +654,7 @@ __fixup_pv_table:\n> \tadr_l\tr6, __pv_phys_pfn_offset\n> \tadr_l\tr7, __pv_offset\t\t\t@ __pa(__pv_offset)\n> \tmov_l\tr3, __pv_offset\t\t\t@ __va(__pv_offset)\n> +\tadd_kaslr_offset r3, ip\n> \tmvn\tip, #0\n> \tsubs\tr3, r7, r3\t@ PHYS_OFFSET - PAGE_OFFSET\n> \tmov\tr0, r8, lsr #PAGE_SHIFT\t@ convert to PFN\n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"l2S2HPVD\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"UIZGkYBG\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate 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ARM: kernel: implement randomization of the\n\tkernel load address","In-Reply-To":"<20170903120757.14968-25-ard.biesheuvel@linaro.org>","Message-ID":"","References":"<20170903120757.14968-1-ard.biesheuvel@linaro.org>\n\t<20170903120757.14968-25-ard.biesheuvel@linaro.org>","User-Agent":"Alpine 2.21 (LFD 202 2017-01-01)","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170904_114441_594948_BB749A20 ","X-CRM114-Status":"GOOD ( 28.89 )","X-Spam-Score":"-2.7 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.7 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow\n\ttrust [2607:f8b0:400d:c09:0:0:0:22c listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes 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","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762838,"web_url":"http://patchwork.ozlabs.org/comment/1762838/","msgid":"","list_archive_url":null,"date":"2017-09-04T18:47:42","subject":"Re: [PATCH v2 25/29] ARM: decompressor: explicitly map decompressor\n\tbinary cacheable","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> When randomizing the kernel load address, there may be a large\n> distance in memory between the decompressor binary and its payload\n> and the destination area in memory. Ensure that the decompressor\n> itself is mapped cacheable in this case, by tweaking the existing\n> routine that takes care of this for XIP decompressors.\n> \n> Cc: Russell King \n> Signed-off-by: Ard Biesheuvel \n\nAcked-by: Nicolas Pitre \n\n> ---\n> arch/arm/boot/compressed/head.S | 16 ++++++++++------\n> 1 file changed, 10 insertions(+), 6 deletions(-)\n> \n> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S\n> index 5884e8151376..583cc6899d98 100644\n> --- a/arch/arm/boot/compressed/head.S\n> +++ b/arch/arm/boot/compressed/head.S\n> @@ -706,20 +706,24 @@ __setup_mmu:\tsub\tr3, r4, #16384\t\t@ Page directory size\n> \t\tteq\tr0, r2\n> \t\tbne\t1b\n> /*\n> - * If ever we are running from Flash, then we surely want the cache\n> - * to be enabled also for our execution instance... We map 2MB of it\n> - * so there is no map overlap problem for up to 1 MB compressed kernel.\n> - * If the execution is in RAM then we would only be duplicating the above.\n> + * Make sure our entire executable image (including payload) is mapped\n> + * cacheable, in case it is located outside the region we covered above.\n> + * (This may be the case if running from flash or with randomization enabled)\n> + * If the regions happen to overlap, we just duplicate some of the above.\n> */\n> \t\torr\tr1, r6, #0x04\t\t@ ensure B is set for this\n> \t\torr\tr1, r1, #3 << 10\n> \t\tmov\tr2, pc\n> +\t\tadr_l\tr9, _end\n> \t\tmov\tr2, r2, lsr #20\n> +\t\tmov\tr9, r9, lsr #20\n> \t\torr\tr1, r1, r2, lsl #20\n> \t\tadd\tr0, r3, r2, lsl #2\n> -\t\tstr\tr1, [r0], #4\n> +\t\tadd\tr9, r3, r9, lsl #2\n> +0:\t\tstr\tr1, [r0], #4\n> \t\tadd\tr1, r1, #1048576\n> -\t\tstr\tr1, [r0]\n> +\t\tcmp\tr0, r9\n> +\t\tbls\t0b\n> \t\tmov\tpc, lr\n> ENDPROC(__setup_mmu)\n> \n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762840,"web_url":"http://patchwork.ozlabs.org/comment/1762840/","msgid":"","list_archive_url":null,"date":"2017-09-04T18:53:52","subject":"Re: [PATCH v2 26/29] ARM: decompressor: add KASLR support","submitter":{"id":4652,"url":"http://patchwork.ozlabs.org/api/people/4652/","name":"Nicolas Pitre","email":"nicolas.pitre@linaro.org"},"content":"On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n\n> Add support to the decompressor to load the kernel at a randomized\n> offset, and invoke the kernel proper while passing on the information\n> about the offset at which the kernel was loaded.\n> \n> This implementation will extract some pseudo-randomness from the low\n> bits of the generic timer (if available), and use CRC-16 to combine\n> it with the build ID string and the device tree binary (which ideally\n> has a /chosen/kaslr-seed property, but may also have other properties\n> that differ between boots). This seed is used to select one of the\n> candidate offsets in the lowmem region that don't overlap the zImage\n> itself, the DTB, the initrd and /memreserve/s and/or /reserved-memory\n> nodes that should be left alone.\n> \n> When booting via the UEFI stub, it is left up to the firmware to supply\n> a suitable seed and select an offset.\n\nWhy did you remove the entropy contribution from general regs upon \nentry? That was an easy way to enable KASLR on those platforms not using \nDT as they would simply have to put some random value in any of the \nregs.\n\n\n> \n> Cc: Russell King \n> Signed-off-by: Ard Biesheuvel \n> ---\n> arch/arm/boot/compressed/Makefile | 8 +-\n> arch/arm/boot/compressed/head.S | 84 ++++-\n> arch/arm/boot/compressed/kaslr.c | 398 ++++++++++++++++++++\n> 3 files changed, 484 insertions(+), 6 deletions(-)\n> \n> diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile\n> index d50430c40045..771b1ba1baa3 100644\n> --- a/arch/arm/boot/compressed/Makefile\n> +++ b/arch/arm/boot/compressed/Makefile\n> @@ -85,8 +85,14 @@ $(addprefix $(obj)/,$(libfdt) $(libfdt_hdrs)): $(obj)/%: $(srctree)/scripts/dtc/\n> $(addprefix $(obj)/,$(libfdt_objs) atags_to_fdt.o): \\\n> \t$(addprefix $(obj)/,$(libfdt_hdrs))\n> \n> +ifneq ($(CONFIG_ARM_ATAG_DTB_COMPAT)$(CONFIG_RANDOMIZE_BASE),)\n> +OBJS\t+= $(libfdt_objs)\n> ifeq ($(CONFIG_ARM_ATAG_DTB_COMPAT),y)\n> -OBJS\t+= $(libfdt_objs) atags_to_fdt.o\n> +OBJS\t+= atags_to_fdt.o\n> +endif\n> +ifeq ($(CONFIG_RANDOMIZE_BASE),y)\n> +OBJS\t+= kaslr.o\n> +endif\n> endif\n> \n> targets := vmlinux vmlinux.lds piggy_data piggy.o \\\n> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S\n> index 583cc6899d98..79b4033b0ed4 100644\n> --- a/arch/arm/boot/compressed/head.S\n> +++ b/arch/arm/boot/compressed/head.S\n> @@ -381,6 +381,42 @@ restart:\tadr\tr0, LC0\n> dtb_check_done:\n> #endif\n> \n> +#ifdef CONFIG_RANDOMIZE_BASE\n> +\t\tldr\tr1, kaslr_offset\t@ check if the kaslr_offset is\n> +\t\tcmp\tr1, #0\t\t\t@ already set\n> +#ifdef CONFIG_EFI_STUB\n> +\t\tldreq\tr1, __efi_boot\t\t@ UEFI has its own KASLR init\n> +\t\tcmpeq\tr1, #0\t\t\t@ routine so skip over this one\n> +#endif\n> +\t\tbne\t1f\n> +\n> +\t\tstmfd\tsp!, {r0-r3, ip, lr}\n> +\t\tadr_l\tr2, _text\t\t@ start of zImage\n> +\t\tstmfd\tsp!, {r2, r8, r10}\t@ pass stack arguments\n> +\n> +#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)\n> +\t\t/*\n> +\t\t * Get some pseudo-entropy from the low bits of the generic\n> +\t\t * timer if it is implemented.\n> +\t\t */\n> +\t\tmrc\tp15, 0, r1, c0, c1, 1\t@ read ID_PFR1 register\n> +\t\ttst\tr1, #0x10000\t\t@ have generic timer?\n> +\t\tbeq\t0f\n> +\t\tmrrc\tp15, 1, r3, r1, c14\t@ read CNTVCT\n> +#endif\n> +0:\t\tadr_l\tr0, kaslr_offset\t@ pass &kaslr_offset in r0\n> +\t\tmov\tr1, r4\t\t\t@ pass base address\n> +\t\tmov\tr2, r9\t\t\t@ pass decompressed image size\n> +\t\teor\tr3, r3, r3, ror #16\t@ pass initial seed\n> +\t\tbl\tkaslr_early_init\n> +\t\tadd\tsp, sp, #12\n> +\t\tcmp\tr0, #0\n> +\t\taddne\tr4, r4, r0\t\t@ add offset to base address\n> +\t\tldmfd\tsp!, {r0-r3, ip, lr}\n> +\t\tbne\trestart\n> +1:\n> +#endif\n> +\n> /*\n> * Check to see if we will overwrite ourselves.\n> * r4 = final kernel address (possibly with LSB set)\n> @@ -1356,25 +1392,63 @@ __hyp_reentry_vectors:\n> \n> __enter_kernel:\n> \t\tmov\tr0, #0\t\t\t@ must be 0\n> +#ifdef CONFIG_RANDOMIZE_BASE\n> +\t\tldr\tr3, kaslr_offset\n> +\t\tadd\tr4, r4, #4\t\t@ skip first instruction\n> +#endif\n> ARM(\t\tmov\tpc, r4\t\t)\t@ call kernel\n> M_CLASS(\tadd\tr4, r4, #1\t)\t@ enter in Thumb mode for M class\n> THUMB(\t\tbx\tr4\t\t)\t@ entry point is always ARM for A/R classes\n> \n> +#ifdef CONFIG_RANDOMIZE_BASE\n> +\t\t/*\n> +\t\t * Minimal implementation of CRC-16 that does not use a\n> +\t\t * lookup table and uses 32-bit wide loads, so it still\n> +\t\t * performs reasonably well with the D-cache off. Equivalent\n> +\t\t * to lib/crc16.c for input sizes that are 4 byte multiples.\n> +\t\t */\n> +ENTRY(__crc16)\n> +\t\tpush\t{r4, lr}\n> +\t\tldr\tr3, =0xa001\t\t@ CRC-16 polynomial\n> +0:\t\tsubs\tr2, r2, #4\n> +\t\tpopmi\t{r4, pc}\n> +\t\tldr\tr4, [r1], #4\n> +#ifdef __ARMEB__\n> +\t\teor\tip, r4, r4, ror #16\t@ endian swap\n> +\t\tbic\tip, ip, #0x00ff0000\n> +\t\tmov\tr4, r4, ror #8\n> +\t\teor\tr4, r4, ip, lsr #8\n> +#endif\n> +\t\teor\tr0, r0, r4\n> +\t\t.rept\t32\n> +\t\tlsrs\tr0, r0, #1\n> +\t\teorcs\tr0, r0, r3\n> +\t\t.endr\n> +\t\tb\t0b\n> +ENDPROC(__crc16)\n> +\n> +\t\t.align\t2\n> +kaslr_offset:\t.long\t0\n> +#ifdef CONFIG_EFI_STUB\n> +__efi_boot:\t.long\t0\n> +#endif\n> +#endif\n> +\n> reloc_code_end:\n> \n> #ifdef CONFIG_EFI_STUB\n> \t\t.align\t2\n> -_start:\t\t.long\tstart - .\n> -\n> ENTRY(efi_stub_entry)\n> \t\t@ allocate space on stack for passing current zImage address\n> \t\t@ and for the EFI stub to return of new entry point of\n> \t\t@ zImage, as EFI stub may copy the kernel. Pointer address\n> \t\t@ is passed in r2. r0 and r1 are passed through from the\n> \t\t@ EFI firmware to efi_entry\n> -\t\tadr\tip, _start\n> -\t\tldr\tr3, [ip]\n> -\t\tadd\tr3, r3, ip\n> +#ifdef CONFIG_RANDOMIZE_BASE\n> +\t\tadr\tr3, __efi_boot\n> +\t\tstr\tr3, [r3]\t\t@ set __efi_boot != 0\n> +#endif\n> +\t\tadr_l\tr3, start\n> \t\tstmfd\tsp!, {r3, lr}\n> \t\tmov\tr2, sp\t\t\t@ pass zImage address in r2\n> \t\tbl\tefi_entry\n> diff --git a/arch/arm/boot/compressed/kaslr.c b/arch/arm/boot/compressed/kaslr.c\n> new file mode 100644\n> index 000000000000..c68bdea764b6\n> --- /dev/null\n> +++ b/arch/arm/boot/compressed/kaslr.c\n> @@ -0,0 +1,398 @@\n> +/*\n> + * Copyright (C) 2017 Linaro Ltd; \n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation.\n> + *\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +struct regions {\n> +\tu32 pa_start;\n> +\tu32 pa_end;\n> +\tu32 image_size;\n> +\tu32 zimage_start;\n> +\tu32 zimage_size;\n> +\tu32 dtb_start;\n> +\tu32 dtb_size;\n> +\tu32 initrd_start;\n> +\tu32 initrd_size;\n> +\tint reserved_mem;\n> +\tint reserved_mem_addr_cells;\n> +\tint reserved_mem_size_cells;\n> +};\n> +\n> +extern u32 __crc16(u32 crc, u32 const input[], int byte_count);\n> +\n> +static u32 __memparse(const char *val, const char **retptr)\n> +{\n> +\tint base = 10;\n> +\tu32 ret = 0;\n> +\n> +\tif (*val == '0') {\n> +\t\tval++;\n> +\t\tif (*val == 'x' || *val == 'X') {\n> +\t\t\tval++;\n> +\t\t\tbase = 16;\n> +\t\t} else {\n> +\t\t\tbase = 8;\n> +\t\t}\n> +\t}\n> +\n> +\twhile (*val != ',' && *val != ' ' && *val != '\\0') {\n> +\t\tchar c = *val++;\n> +\n> +\t\tswitch (c) {\n> +\t\tcase '0' ... '9':\n> +\t\t\tret = ret * base + (c - '0');\n> +\t\t\tcontinue;\n> +\t\tcase 'a' ... 'f':\n> +\t\t\tret = ret * base + (c - 'a' + 10);\n> +\t\t\tcontinue;\n> +\t\tcase 'A' ... 'F':\n> +\t\t\tret = ret * base + (c - 'A' + 10);\n> +\t\t\tcontinue;\n> +\t\tcase 'g':\n> +\t\tcase 'G':\n> +\t\t\tret <<= 10;\n> +\t\tcase 'm':\n> +\t\tcase 'M':\n> +\t\t\tret <<= 10;\n> +\t\tcase 'k':\n> +\t\tcase 'K':\n> +\t\t\tret <<= 10;\n> +\t\t\tbreak;\n> +\t\tdefault:\n> +\t\t\tif (retptr)\n> +\t\t\t\t*retptr = NULL;\n> +\t\t\treturn 0;\n> +\t\t}\n> +\t}\n> +\tif (retptr)\n> +\t\t*retptr = val;\n> +\treturn ret;\n> +}\n> +\n> +static bool regions_intersect(u32 s1, u32 e1, u32 s2, u32 e2)\n> +{\n> +\treturn e1 >= s2 && e2 >= s1;\n> +}\n> +\n> +static bool intersects_reserved_region(const void *fdt, u32 start,\n> +\t\t\t\t u32 end, struct regions *regions)\n> +{\n> +\tint subnode, len, i;\n> +\tu64 base, size;\n> +\n> +\t/* check for overlap with /memreserve/ entries */\n> +\tfor (i = 0; i < fdt_num_mem_rsv(fdt); i++) {\n> +\t\tif (fdt_get_mem_rsv(fdt, i, &base, &size) < 0)\n> +\t\t\tcontinue;\n> +\t\tif (regions_intersect(start, end, base, base + size))\n> +\t\t\treturn true;\n> +\t}\n> +\n> +\tif (regions->reserved_mem < 0)\n> +\t\treturn false;\n> +\n> +\t/* check for overlap with static reservations in /reserved-memory */\n> +\tfor (subnode = fdt_first_subnode(fdt, regions->reserved_mem);\n> +\t subnode >= 0;\n> +\t subnode = fdt_next_subnode(fdt, subnode)) {\n> +\t\tconst fdt32_t *reg;\n> +\n> +\t\tlen = 0;\n> +\t\treg = fdt_getprop(fdt, subnode, \"reg\", &len);\n> +\t\twhile (len >= (regions->reserved_mem_addr_cells +\n> +\t\t\t regions->reserved_mem_size_cells)) {\n> +\n> +\t\t\tbase = fdt32_to_cpu(reg[0]);\n> +\t\t\tif (regions->reserved_mem_addr_cells == 2)\n> +\t\t\t\tbase = (base << 32) | fdt32_to_cpu(reg[1]);\n> +\n> +\t\t\treg += regions->reserved_mem_addr_cells;\n> +\t\t\tlen -= 4 * regions->reserved_mem_addr_cells;\n> +\n> +\t\t\tsize = fdt32_to_cpu(reg[0]);\n> +\t\t\tif (regions->reserved_mem_size_cells == 2)\n> +\t\t\t\tsize = (size << 32) | fdt32_to_cpu(reg[1]);\n> +\n> +\t\t\treg += regions->reserved_mem_size_cells;\n> +\t\t\tlen -= 4 * regions->reserved_mem_size_cells;\n> +\n> +\t\t\tif (base >= regions->pa_end)\n> +\t\t\t\tcontinue;\n> +\n> +\t\t\tif (regions_intersect(start, end, base,\n> +\t\t\t\t\t min(base + size, (u64)U32_MAX)))\n> +\t\t\t\treturn true;\n> +\t\t}\n> +\t}\n> +\treturn false;\n> +}\n> +\n> +static bool intersects_occupied_region(const void *fdt, u32 start,\n> +\t\t\t\t u32 end, struct regions *regions)\n> +{\n> +\tif (regions_intersect(start, end, regions->zimage_start,\n> +\t\t\t regions->zimage_start + regions->zimage_size))\n> +\t\treturn true;\n> +\n> +\tif (regions_intersect(start, end, regions->initrd_start,\n> +\t\t\t regions->initrd_start + regions->initrd_size))\n> +\t\treturn true;\n> +\n> +\tif (regions_intersect(start, end, regions->dtb_start,\n> +\t\t\t regions->dtb_start + regions->dtb_size))\n> +\t\treturn true;\n> +\n> +\treturn intersects_reserved_region(fdt, start, end, regions);\n> +}\n> +\n> +static u32 count_suitable_regions(const void *fdt, struct regions *regions)\n> +{\n> +\tu32 pa, ret = 0;\n> +\n> +\tfor (pa = regions->pa_start; pa < regions->pa_end; pa += SZ_2M) {\n> +\t\tif (!intersects_occupied_region(fdt, pa,\n> +\t\t\t\t\t\tpa + regions->image_size,\n> +\t\t\t\t\t\tregions))\n> +\t\t\tret++;\n> +\t}\n> +\treturn ret;\n> +}\n> +\n> +static u32 get_numbered_region(const void *fdt,\n> +\t\t\t\t\t struct regions *regions,\n> +\t\t\t\t\t int num)\n> +{\n> +\tu32 pa;\n> +\n> +\tfor (pa = regions->pa_start; pa < regions->pa_end; pa += SZ_2M) {\n> +\t\tif (!intersects_occupied_region(fdt, pa,\n> +\t\t\t\t\t\tpa + regions->image_size,\n> +\t\t\t\t\t\tregions))\n> +\t\t\tif (num-- == 0)\n> +\t\t\t\treturn pa;\n> +\t}\n> +\treturn regions->pa_start; /* should not happen */\n> +}\n> +\n> +static void get_cell_sizes(const void *fdt, int node, int *addr_cells,\n> +\t\t\t int *size_cells)\n> +{\n> +\tconst int *prop;\n> +\tint len;\n> +\n> +\t/*\n> +\t * Retrieve the #address-cells and #size-cells properties\n> +\t * from the 'node', or use the default if not provided.\n> +\t */\n> +\t*addr_cells = *size_cells = 1;\n> +\n> +\tprop = fdt_getprop(fdt, node, \"#address-cells\", &len);\n> +\tif (len == 4)\n> +\t\t*addr_cells = fdt32_to_cpu(*prop);\n> +\tprop = fdt_getprop(fdt, node, \"#size-cells\", &len);\n> +\tif (len == 4)\n> +\t\t*size_cells = fdt32_to_cpu(*prop);\n> +}\n> +\n> +static u32 get_memory_end(const void *fdt)\n> +{\n> +\tint mem_node, address_cells, size_cells, len;\n> +\tconst fdt32_t *reg;\n> +\tu64 memory_end = 0;\n> +\n> +\t/* Look for a node called \"memory\" at the lowest level of the tree */\n> +\tmem_node = fdt_path_offset(fdt, \"/memory\");\n> +\tif (mem_node <= 0)\n> +\t\treturn 0;\n> +\n> +\tget_cell_sizes(fdt, 0, &address_cells, &size_cells);\n> +\n> +\t/*\n> +\t * Now find the 'reg' property of the /memory node, and iterate over\n> +\t * the base/size pairs.\n> +\t */\n> +\tlen = 0;\n> +\treg = fdt_getprop(fdt, mem_node, \"reg\", &len);\n> +\twhile (len >= 4 * (address_cells + size_cells)) {\n> +\t\tu64 base, size;\n> +\n> +\t\tbase = fdt32_to_cpu(reg[0]);\n> +\t\tif (address_cells == 2)\n> +\t\t\tbase = (base << 32) | fdt32_to_cpu(reg[1]);\n> +\n> +\t\treg += address_cells;\n> +\t\tlen -= 4 * address_cells;\n> +\n> +\t\tsize = fdt32_to_cpu(reg[0]);\n> +\t\tif (size_cells == 2)\n> +\t\t\tsize = (size << 32) | fdt32_to_cpu(reg[1]);\n> +\n> +\t\treg += size_cells;\n> +\t\tlen -= 4 * size_cells;\n> +\n> +\t\tmemory_end = max(memory_end, base + size);\n> +\t}\n> +\treturn min(memory_end, (u64)U32_MAX);\n> +}\n> +\n> +static char *__strstr(const char *s1, const char *s2, int l2)\n> +{\n> +\tint l1;\n> +\n> +\tl1 = strlen(s1);\n> +\twhile (l1 >= l2) {\n> +\t\tl1--;\n> +\t\tif (!memcmp(s1, s2, l2))\n> +\t\t\treturn (char *)s1;\n> +\t\ts1++;\n> +\t}\n> +\treturn NULL;\n> +}\n> +\n> +static const char *get_cmdline_param(const char *cmdline, const char *param,\n> +\t\t\t\t int param_size)\n> +{\n> +\tstatic const char default_cmdline[] = CONFIG_CMDLINE;\n> +\tconst char *p;\n> +\n> +\tif (!IS_ENABLED(CONFIG_CMDLINE_FORCE) && cmdline != NULL) {\n> +\t\tp = __strstr(cmdline, param, param_size);\n> +\t\tif (p == cmdline ||\n> +\t\t (p > cmdline && *(p - 1) == ' '))\n> +\t\t\treturn p;\n> +\t}\n> +\n> +\tif (IS_ENABLED(CONFIG_CMDLINE_FORCE) ||\n> +\t IS_ENABLED(CONFIG_CMDLINE_EXTEND)) {\n> +\t\tp = __strstr(default_cmdline, param, param_size);\n> +\t\tif (p == default_cmdline ||\n> +\t\t (p > default_cmdline && *(p - 1) == ' '))\n> +\t\t\treturn p;\n> +\t}\n> +\treturn NULL;\n> +}\n> +\n> +u32 kaslr_early_init(u32 *kaslr_offset, u32 image_base, u32 image_size,\n> +\t\t u32 seed, u32 zimage_start, const void *fdt,\n> +\t\t u32 zimage_end)\n> +{\n> +\tstatic const char __aligned(4) build_id[] = UTS_VERSION UTS_RELEASE;\n> +\tstruct regions regions;\n> +\tconst char *command_line;\n> +\tconst char *p;\n> +\tint chosen, len;\n> +\tu32 lowmem_top, num;\n> +\n> +\tif (fdt_check_header(fdt))\n> +\t\treturn 0;\n> +\n> +\tchosen = fdt_path_offset(fdt, \"/chosen\");\n> +\tif (chosen < 0)\n> +\t\treturn 0;\n> +\n> +\tcommand_line = fdt_getprop(fdt, chosen, \"bootargs\", &len);\n> +\n> +\t/* check the command line for the presence of 'nokaslr' */\n> +\tp = get_cmdline_param(command_line, \"nokaslr\", sizeof(\"nokaslr\") - 1);\n> +\tif (p != NULL)\n> +\t\treturn 0;\n> +\n> +\t/* check the command line for the presence of 'vmalloc=' */\n> +\tp = get_cmdline_param(command_line, \"vmalloc=\", sizeof(\"vmalloc=\") - 1);\n> +\tif (p != NULL)\n> +\t\tlowmem_top = VMALLOC_END - __memparse(p + 8, NULL) -\n> +\t\t\t VMALLOC_OFFSET;\n> +\telse\n> +\t\tlowmem_top = VMALLOC_DEFAULT_BASE;\n> +\n> +\tregions.image_size = round_up(image_size, SZ_2M);\n> +\tregions.pa_start = round_down(image_base, SZ_128M);\n> +\tregions.pa_end = lowmem_top - PAGE_OFFSET + regions.pa_start -\n> +\t\t\t regions.image_size;\n> +\tregions.zimage_start = zimage_start;\n> +\tregions.zimage_size = zimage_end - zimage_start;\n> +\tregions.dtb_start = (u32)fdt;\n> +\tregions.dtb_size = fdt_totalsize(fdt);\n> +\n> +\t/*\n> +\t * Stir up the seed a bit by taking the CRC of the DTB:\n> +\t * hopefully there's a /chosen/kaslr-seed in there.\n> +\t */\n> +\tseed = __crc16(seed, fdt, regions.dtb_size);\n> +\n> +\t/* stir a bit more using data that changes between builds */\n> +\tseed = __crc16(seed, (u32 *)build_id, sizeof(build_id));\n> +\n> +\t/* check for initrd on the command line */\n> +\tregions.initrd_start = regions.initrd_size = 0;\n> +\tp = get_cmdline_param(command_line, \"initrd=\", sizeof(\"initrd=\") - 1);\n> +\tif (p != NULL) {\n> +\t\tregions.initrd_start = __memparse(p + 7, &p);\n> +\t\tif (*p++ == ',')\n> +\t\t\tregions.initrd_size = __memparse(p, NULL);\n> +\t\tif (regions.initrd_size == 0)\n> +\t\t\tregions.initrd_start = 0;\n> +\t}\n> +\n> +\t/* ... or in /chosen */\n> +\tif (regions.initrd_size == 0) {\n> +\t\tconst fdt32_t *prop;\n> +\t\tu64 start = 0, end = 0;\n> +\n> +\t\tprop = fdt_getprop(fdt, chosen, \"linux,initrd-start\", &len);\n> +\t\tif (prop) {\n> +\t\t\tstart = fdt32_to_cpu(prop[0]);\n> +\t\t\tif (len == 8)\n> +\t\t\t\tstart = (start << 32) | fdt32_to_cpu(prop[1]);\n> +\t\t}\n> +\n> +\t\tprop = fdt_getprop(fdt, chosen, \"linux,initrd-end\", &len);\n> +\t\tif (prop) {\n> +\t\t\tend = fdt32_to_cpu(prop[0]);\n> +\t\t\tif (len == 8)\n> +\t\t\t\tend = (end << 32) | fdt32_to_cpu(prop[1]);\n> +\t\t}\n> +\t\tif (start != 0 && end != 0 && start < U32_MAX) {\n> +\t\t\tregions.initrd_start = start;\n> +\t\t\tregions.initrd_size = max_t(u64, end, U32_MAX) - start;\n> +\t\t}\n> +\t}\n> +\n> +\t/* check the memory nodes for the size of the lowmem region */\n> +\tregions.pa_end = min(regions.pa_end, get_memory_end(fdt));\n> +\n> +\t/* check for a reserved-memory node and record its cell sizes */\n> +\tregions.reserved_mem = fdt_path_offset(fdt, \"/reserved-memory\");\n> +\tif (regions.reserved_mem >= 0)\n> +\t\tget_cell_sizes(fdt, regions.reserved_mem,\n> +\t\t\t ®ions.reserved_mem_addr_cells,\n> +\t\t\t ®ions.reserved_mem_size_cells);\n> +\n> +\t/*\n> +\t * Iterate over the physical memory range covered by the lowmem region\n> +\t * in 2 MB increments, and count each offset at which we don't overlap\n> +\t * with any of the reserved regions for the zImage itself, the DTB,\n> +\t * the initrd and any regions described as reserved in the device tree.\n> +\t * This produces a count, which we will scale by multiplying by a 16-bit\n> +\t * random value and shifting right by 16 places.\n> +\t * Using this random value, we iterate over the physical memory range\n> +\t * again until we counted enough iterations, and return the offset we\n> +\t * ended up at.\n> +\t */\n> +\tnum = ((u16)seed * count_suitable_regions(fdt, ®ions)) >> 16;\n> +\n> +\t*kaslr_offset = get_numbered_region(fdt, ®ions, num) -\n> +\t\t\tregions.pa_start;\n> +\n> +\treturn *kaslr_offset;\n> +}\n> -- \n> 2.11.0\n> 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26/29] ARM: decompressor: add KASLR support","In-Reply-To":"<20170903120757.14968-27-ard.biesheuvel@linaro.org>","Message-ID":"","References":"<20170903120757.14968-1-ard.biesheuvel@linaro.org>\n\t<20170903120757.14968-27-ard.biesheuvel@linaro.org>","User-Agent":"Alpine 2.21 (LFD 202 2017-01-01)","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170904_115415_542559_CD77C2D9 ","X-CRM114-Status":"GOOD ( 37.24 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Mark Rutland , Kees Cook , \n\tArnd Bergmann , kernel-hardening@lists.openwall.com,\n\tMarc Zyngier ,\n\tRussell King , \n\tDave Martin , Tony Lindgren , \n\tMatt Fleming ,\n\tThomas Garnier , \n\tlinux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762846,"web_url":"http://patchwork.ozlabs.org/comment/1762846/","msgid":"","list_archive_url":null,"date":"2017-09-04T19:10:00","subject":"Re: [PATCH v2 19/29] ARM: kernel: make vmlinux buildable as a PIE\n\texecutable","submitter":{"id":26857,"url":"http://patchwork.ozlabs.org/api/people/26857/","name":"Ard Biesheuvel","email":"ard.biesheuvel@linaro.org"},"content":"On 4 September 2017 at 19:11, Nicolas Pitre wrote:\n> On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n>\n>> Update the build flags and linker script to allow vmlinux to be built\n>> as a PIE binary, which retains relocation information about absolute\n>> symbol references so that they can be fixed up at runtime. This will\n>> be used for implementing KASLR,\n>>\n>> Cc: Russell King \n>> Signed-off-by: Ard Biesheuvel \n>> ---\n>> arch/arm/Kconfig | 4 ++++\n>> arch/arm/Makefile | 5 +++++\n>> arch/arm/include/asm/assembler.h | 2 +-\n>> arch/arm/kernel/vmlinux.lds.S | 9 +++++++++\n>> include/linux/hidden.h | 20 ++++++++++++++++++++\n>> scripts/module-common.lds | 1 +\n>> 6 files changed, 40 insertions(+), 1 deletion(-)\n>>\n>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\n>> index 61a0cb15067e..300add3b8023 100644\n>> --- a/arch/arm/Kconfig\n>> +++ b/arch/arm/Kconfig\n>> @@ -2085,6 +2085,10 @@ config DMI\n>> firmware need to be enabled. This would require the DMI subsystem\n>> to be enabled much earlier than we do on ARM, which is non-trivial.\n>>\n>> +config RELOCATABLE\n>> + bool\n>> + select HAVE_ARCH_PREL32_RELOCATIONS\n>> +\n>\n> You should probably make it depend on !XIP_KERNEL.\n>\n\nIndeed.\n\n> Other than that\n>\n> Acked-by: Nicolas Pitre \n>\n\nThanks.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"I2gAal1N\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"Ch8vpFAU\"; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762847,"web_url":"http://patchwork.ozlabs.org/comment/1762847/","msgid":"","list_archive_url":null,"date":"2017-09-04T19:09:27","subject":"Re: [PATCH v2 17/29] ARM: kernel: use relative phys-to-virt patch\n\ttables","submitter":{"id":26857,"url":"http://patchwork.ozlabs.org/api/people/26857/","name":"Ard Biesheuvel","email":"ard.biesheuvel@linaro.org"},"content":"On 4 September 2017 at 19:03, Nicolas Pitre wrote:\n> On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n>\n>> Replace the contents of the __pv_table entries with relative references\n>> so that we don't have to relocate them at runtime when running the KASLR\n>> kernel. This ensures these quantities are invariant under runtime\n>> relocation, which makes any cache maintenance after runtime relocation\n>> unnecessary.\n>>\n>> Cc: Russell King \n>> Signed-off-by: Ard Biesheuvel \n>> ---\n>> arch/arm/include/asm/memory.h | 6 +++---\n>> arch/arm/kernel/head.S | 21 ++++++++++----------\n>> 2 files changed, 13 insertions(+), 14 deletions(-)\n>>\n>> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h\n>> index 1f54e4e98c1e..47a984e3a244 100644\n>> --- a/arch/arm/include/asm/memory.h\n>> +++ b/arch/arm/include/asm/memory.h\n>> @@ -195,7 +195,7 @@ extern const void *__pv_table_begin, *__pv_table_end;\n>> __asm__(\"@ __pv_stub\\n\" \\\n>> \"1: \" instr \" %0, %1, %2\\n\" \\\n>> \" .pushsection .pv_table,\\\"a\\\"\\n\" \\\n>> - \" .long 1b\\n\" \\\n>> + \" .long 1b - .\\n\" \\\n>> \" .popsection\\n\" \\\n>\n> [...]\n>\n>> --- a/arch/arm/kernel/head.S\n>> +++ b/arch/arm/kernel/head.S\n>> @@ -612,22 +611,22 @@ __fixup_a_pv_table:\n>> orr r6, r6, r7, lsl #12\n>> orr r6, #0x4000\n>> b 2f\n>> -1: add r7, r3\n>> - ldrh ip, [r7, #2]\n>> +1: add r7, r4\n>> + ldrh ip, [r7, #-2]\n>\n> Please use \"ldrh ip, [r7, #(-4 + 2)]\" so the -4 offset is clearly\n> spelled out. The #-2 gave me a pause of confusion.\n>\n>> ARM_BE8(rev16 ip, ip)\n>> tst ip, #0x4000\n>> and ip, #0x8f00\n>> orrne ip, r6 @ mask in offset bits 31-24\n>> orreq ip, r0 @ mask in offset bits 7-0\n>> ARM_BE8(rev16 ip, ip)\n>> - strh ip, [r7, #2]\n>> + strh ip, [r7, #-2]\n>\n> Ditto here.\n>\n>> bne 2f\n>> - ldrh ip, [r7]\n>> + ldrh ip, [r7, #-4]\n>\n> And to be clear, here I'd use \"#(-4 + 0)\" to be explicit.\n>\n>> ARM_BE8(rev16 ip, ip)\n>> bic ip, #0x20\n>> orr ip, ip, r0, lsr #16\n>> ARM_BE8(rev16 ip, ip)\n>> - strh ip, [r7]\n>> + strh ip, [r7, #-4]\n>\n> And so here.\n>\n\nOK\n\n>\n> With that:\n>\n> Reviewed-by: Nicolas Pitre \n\nThanks.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1762848,"web_url":"http://patchwork.ozlabs.org/comment/1762848/","msgid":"","list_archive_url":null,"date":"2017-09-04T19:14:54","subject":"Re: [PATCH v2 20/29] ARM: kernel: use PC-relative symbol references\n\tin MMU switch code","submitter":{"id":26857,"url":"http://patchwork.ozlabs.org/api/people/26857/","name":"Ard Biesheuvel","email":"ard.biesheuvel@linaro.org"},"content":"On 4 September 2017 at 19:15, Nicolas Pitre wrote:\n> On Sun, 3 Sep 2017, Ard Biesheuvel wrote:\n>\n>> To prepare for adding support for KASLR, which relocates all absolute\n>> symbol references at runtime after the caches have been enabled,\n>> update the MMU switch code to avoid using absolute symbol references\n>> where possible. This ensures these quantities are invariant under\n>> runtime relocation.\n>>\n>> Cc: Russell King \n>> Signed-off-by: Ard Biesheuvel \n>> ---\n>> arch/arm/kernel/head-common.S | 39 ++++++++------------\n>> 1 file changed, 15 insertions(+), 24 deletions(-)\n>>\n>> diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S\n>> index 06035488130c..b74477507a12 100644\n>> --- a/arch/arm/kernel/head-common.S\n>> +++ b/arch/arm/kernel/head-common.S\n>> @@ -79,9 +79,10 @@ ENDPROC(__vet_atags)\n>> */\n>> __INIT\n>> __mmap_switched:\n>> - adr r3, __mmap_switched_data\n>> -\n>> - ldmia r3!, {r4, r5, r6, r7}\n>> + adr_l r4, __data_loc\n>> + adr_l r5, _sdata\n>> + adr_l r6, __bss_start\n>> + adr_l r7, _end\n>> cmp r4, r5 @ Copy data segment if needed\n>> 1: cmpne r5, r6\n>> ldrne fp, [r4], #4\n>> @@ -93,9 +94,17 @@ __mmap_switched:\n>> strcc fp, [r6],#4\n>> bcc 1b\n>>\n>> - ARM( ldmia r3, {r4, r5, r6, r7, sp})\n>> - THUMB( ldmia r3, {r4, r5, r6, r7} )\n>> - THUMB( ldr sp, [r3, #16] )\n>> + adr_l r3, init_thread_union + THREAD_START_SP\n>> + mov sp, r3\n>> + adr_l r4, processor_id\n>> + adr_l r5, __machine_arch_type\n>> + adr_l r6, __atags_pointer\n>> +#ifdef CONFIG_CPU_CP15\n>> + adr_l r7, cr_alignment\n>> +#else\n>> + mov r7, #0\n>> +#endif\n>\n> The code that follows is testing for a non-zero r7 value to store r0 so\n> you could make that code conditional rather than loading 0 here.\n>\n\nOK, I will look into that.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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