[{"id":1768618,"web_url":"http://patchwork.ozlabs.org/comment/1768618/","msgid":"","list_archive_url":null,"date":"2017-09-14T13:54:56","subject":"Re: [PATCH 00/16] gpio: Tight IRQ chip integration and banked\n\tinfrastructure","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Fri, Sep 1, 2017 at 8:57 PM, Thierry Reding wrote:\n\n> here's the latest series of patches that implement the tighter IRQ chip\n> integration as well as the banked GPIO infrastructure that we had\n> discussed a couple of weeks/months back.\n\nYes it has become really tasty now, don't you think :)\n\nI really like the series.\n\nBanks are handled in the core, exactly as I wanted.\n\nI will likely go in and change some things I don't like, like switching\nnum_pins in the bank to num_lines. I have preferred that terminology\nto avoid confusion with pin control. So GPIO chips have lines, not pins.\nBut it's so minor that I can fix it up if you don't want to.\n\nWe also need to go in and patch Documentation/gpio/driver.txt\nto represent the current best practice. But that can be later,\nseparate patch.\n\n> The first couple of patches are mostly preparatory work in order to\n> consolidate all IRQ chip related fields in a new structure and create\n> the base functionality for adding IRQ chips.\n>\n> After that, I've added the Tegra186 GPIO support patch that makes use of\n> the new tight integration.\n>\n> To round things off the new banked GPIO infrastructure is added (along\n> with some more preparatory work), followed by the conversion of the two\n> Tegra GPIO drivers to the new infrastructure.\n\nI have put all on a branch for pushing to the test builders to begin with.\n\nThen I plan to make one branch with all infrastructure patches\n(patches 1-10, 12-14) and pull that into devel, then apply patch\n11 and 15-16 directly on devel.\n\nThat way other subsystems (pinctrl ...) can pull in the infrastructure\nfor people adding new gpiochips this cycle.\n\n> Any thoughts on this? I'd like to target 4.15 with this,\n\nMe, too.\n\n> unless you'd be\n> willing to take this into 4.14, which I doubt at this point. The absence\n> of a GPIO driver has been hampering Tegra186 support upstream for a\n> while now, so it'd be good to make progress on this.\n\nSorry about that. Let's move ahead with this now, it is neat and\nclean.\n\nWhat I want (as maintainer) is a bit of fingerpointing at the drivers\nthat need to be converted to use the new banking infrastructure\nso they don't stay with their old crappy design pattern. OMAP is\na clear candidate right? (Added Tony to CC...)\n\nWho else?\n\nYours,\nLinus Walleij\n--\nTo unsubscribe from this list: send the line \"unsubscribe linux-gpio\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"BQGLDTDz\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xtKmC5KXHz9sPt\n\tfor ;\n\tThu, 14 Sep 2017 23:55:07 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751455AbdINNy7 (ORCPT );\n\tThu, 14 Sep 2017 09:54:59 -0400","from mail-it0-f47.google.com ([209.85.214.47]:48745 \"EHLO\n\tmail-it0-f47.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751447AbdINNy5 (ORCPT\n\t); Thu, 14 Sep 2017 09:54:57 -0400","by mail-it0-f47.google.com with SMTP id d123so206660ith.3\n\tfor ;\n\tThu, 14 Sep 2017 06:54:57 -0700 (PDT)","by 10.79.164.78 with HTTP; Thu, 14 Sep 2017 06:54:56 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=TLooxCjVm6L4HCUP+ky0aAcXxvdyqMl6DvapJdM5aO0=;\n\tb=BQGLDTDzTGgIZMSjGzCW3n34wkgeRsSnvp0q4uSNLu218L/xZlAaP48kvB4Rp8ssFO\n\tIFtKrS3NsLcRGISOgMZUdxYd/yd9ou21BxWRtuSDQA1tYutU6pBk9qrCZGOH07V2FxPV\n\tKCRL+TTmijyJgKz9wjS2iEBd6SdDawa/YyMno=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=TLooxCjVm6L4HCUP+ky0aAcXxvdyqMl6DvapJdM5aO0=;\n\tb=qxk1Q/5IJMTYtT7LMRYz0ZuUMNWOD4k8HQDSGi40IVmbgAYmQCt0gRk/Q7kv9/NnUd\n\tngU1qR0IbdPbEq8An4N0xT0ED2sPK/qHj3B3qqoEN8atV6hhZA5rNVRR6J0nkvN5wqez\n\twwCIYnMTXF7R5RJ9py5ghdP8phMLNFWjZNT8vHUJSp6Kdr5bPqTaNzfqTzXI/4J9dgBk\n\tL3hd8azeuSRafO1tRKbsHqYADN72BmSMNTrom65JC4O59J+Aodz1KFIJete6o8QktWKf\n\tSkGaNfEjkKBcrA/VzJAzIox0tAYWEDf3g4383G+B4OFJ2wlCcPdo7ri6BEQylX8zPTmx\n\tOjQA==","X-Gm-Message-State":"AHPjjUi6OCbs2FPfKJOi3En5PVIC3j/Jx4TY+Eulrp53TYA4z+6aj+1Y\n\tKhGRdMX/NKt5P7RabnpsoW0wcDtN6lo8iaKNqnp8CQ==","X-Google-Smtp-Source":"AOwi7QCT0iuDDm+NCkOrQcFjCWo3HfrO/VXvx753jZeyoYGjtQ9Hpj8Mgy5KlM3zVNQ5mkSW5gW5OwMQCjncAv49jZk=","X-Received":"by 10.36.41.132 with SMTP id p126mr213105itp.84.1505397297074;\n\tThu, 14 Sep 2017 06:54:57 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170901185736.28051-1-thierry.reding@gmail.com>","References":"<20170901185736.28051-1-thierry.reding@gmail.com>","From":"Linus Walleij ","Date":"Thu, 14 Sep 2017 15:54:56 +0200","Message-ID":"","Subject":"Re: [PATCH 00/16] gpio: Tight IRQ chip integration and banked\n\tinfrastructure","To":"Thierry Reding ","Cc":"Jonathan Hunter ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-tegra@vger.kernel.org\" ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\text Tony Lindgren ","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1769240,"web_url":"http://patchwork.ozlabs.org/comment/1769240/","msgid":"<20170914185233.GA6410@aiwendil>","list_archive_url":null,"date":"2017-09-15T15:09:57","subject":"Re: [PATCH 00/16] gpio: Tight IRQ chip integration and banked\n\tinfrastructure","submitter":{"id":26234,"url":"http://patchwork.ozlabs.org/api/people/26234/","name":"Thierry Reding","email":"thierry.reding@gmail.com"},"content":"On Thu, Sep 14, 2017 at 03:54:56PM +0200, Linus Walleij wrote:\n> On Fri, Sep 1, 2017 at 8:57 PM, Thierry Reding wrote:\n> \n> > here's the latest series of patches that implement the tighter IRQ chip\n> > integration as well as the banked GPIO infrastructure that we had\n> > discussed a couple of weeks/months back.\n> \n> Yes it has become really tasty now, don't you think :)\n> \n> I really like the series.\n> \n> Banks are handled in the core, exactly as I wanted.\n> \n> I will likely go in and change some things I don't like, like switching\n> num_pins in the bank to num_lines. I have preferred that terminology\n> to avoid confusion with pin control. So GPIO chips have lines, not pins.\n> But it's so minor that I can fix it up if you don't want to.\n\nI rebased this on today's linux-next and noticed that there was a small\nconflict. I can rebase and work in the changes that you requested.\n\nI'm travelling this week and next, so it may take until after -rc2 that\nI can send out a new version that's properly build-tested.\n\n> We also need to go in and patch Documentation/gpio/driver.txt\n> to represent the current best practice. But that can be later,\n> separate patch.\n> \n> > The first couple of patches are mostly preparatory work in order to\n> > consolidate all IRQ chip related fields in a new structure and create\n> > the base functionality for adding IRQ chips.\n> >\n> > After that, I've added the Tegra186 GPIO support patch that makes use of\n> > the new tight integration.\n> >\n> > To round things off the new banked GPIO infrastructure is added (along\n> > with some more preparatory work), followed by the conversion of the two\n> > Tegra GPIO drivers to the new infrastructure.\n> \n> I have put all on a branch for pushing to the test builders to begin with.\n> \n> Then I plan to make one branch with all infrastructure patches\n> (patches 1-10, 12-14) and pull that into devel, then apply patch\n> 11 and 15-16 directly on devel.\n> \n> That way other subsystems (pinctrl ...) can pull in the infrastructure\n> for people adding new gpiochips this cycle.\n\nSounds good.\n\n> > Any thoughts on this? I'd like to target 4.15 with this,\n> \n> Me, too.\n> \n> > unless you'd be\n> > willing to take this into 4.14, which I doubt at this point. The absence\n> > of a GPIO driver has been hampering Tegra186 support upstream for a\n> > while now, so it'd be good to make progress on this.\n> \n> Sorry about that. Let's move ahead with this now, it is neat and\n> clean.\n> \n> What I want (as maintainer) is a bit of fingerpointing at the drivers\n> that need to be converted to use the new banking infrastructure\n> so they don't stay with their old crappy design pattern. OMAP is\n> a clear candidate right? (Added Tony to CC...)\n\nOMAP should be able to use this infrastructure, but it may not want to\nbecause the semantics would change slightly. Currently OMAP registers a\nGPIO chip for each bank, whereas this infrastructure exposes multiple\nbanks via a single chip.\n\nThere might be some userspace that relies on the existence of multiple\nchips, but Tony can probably knows that better than I.\n\n> Who else?\n\ngpio-intel-mid.c and gpio-merrifield.c look like they could use this new\ninfrastructure. So do gpio-pca953x.c, gpio-stmpe.c and gpio-tc3589x.c.\n\ngpio-ws16c48.c is another one that uses a similar pattern.\n\nThierry","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"skdV/Bft\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xtzNG3kWmz9sBZ\n\tfor ;\n\tSat, 16 Sep 2017 01:10:06 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751234AbdIOPKF (ORCPT );\n\tFri, 15 Sep 2017 11:10:05 -0400","from mail-pg0-f52.google.com ([74.125.83.52]:48855 \"EHLO\n\tmail-pg0-f52.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751201AbdIOPKE (ORCPT\n\t); Fri, 15 Sep 2017 11:10:04 -0400","by mail-pg0-f52.google.com with SMTP id v66so1673291pgb.5;\n\tFri, 15 Sep 2017 08:10:03 -0700 (PDT)","from localhost (198-0-214-85-static.hfc.comcastbusiness.net.\n\t[198.0.214.85]) by smtp.gmail.com with ESMTPSA id\n\t70sm2733472pfh.63.2017.09.15.08.10.00\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tFri, 15 Sep 2017 08:10:01 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=date:from:to:cc:subject:message-id:references:mime-version\n\t:content-disposition:in-reply-to:user-agent;\n\tbh=Kp9KU3FN3R87TWDx/FaX7zYWft7xi0Y0iq73CyzH0nw=;\n\tb=skdV/BftfR7Crah+93gbILNUlaywmgKWoi8BZtPG+8t2xVJY9Ljlga50x234E2Fqrq\n\tiiQlBgfkNS/m/zxan+yrVB6KP7byPULLKefAokLVAPc/2xOtWYMnR1FpcUpUF9h0wDfC\n\tnfkQZo5iDGEuqIWk5Ja56m3RZOL1sy2QIwZRnRbV1r/wUqGcJtUZB9gnfT/dQQsZO/mX\n\t4vg/biTaAytpnrYmLdeOvq+OZQe5bNhZyejjyQyeGhRR79ogoYJFeAr6dynYCho5PzKR\n\tVcrk4+2ZaepaNbBbP44RCwCpQql6PA9GhT3m5j/QN1hLRTU2ugBEv6faVCpc8yAw060q\n\t7WJg==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=Kp9KU3FN3R87TWDx/FaX7zYWft7xi0Y0iq73CyzH0nw=;\n\tb=ZOVJutEr45W/gpEq7DMRXv/4U0D0IKEAo+TZ4vOjIBmMaH5Qm6G9BYoqpMtJqPZUBA\n\tDhumAM/COkaqpGQiuIu/bFw8XZCFgNP/yDx2WIG4kGnugITBJsxnZ6sWRMHLVWl9V3wq\n\tOsjkgndOL2Ln9J+ipcMw4ejxc0N2pIhWJmXESEOXUnMYV16naMSNXh54EjA0MdIA8hmp\n\tIaZQoxpyLyTl4JTuIrxcZYhax64kotc3DTQdhhzZ4EKAgjoni7y51e4huioJx4WsH0F9\n\tAKRFAYId0ENuebe4htq0GTdfFEpuiGTAjKeYmfbggvH+1e1zT6+ajvQFl07xYlop5lXh\n\t1IaQ==","X-Gm-Message-State":"AHPjjUgPuVW7nLsxlR+pK1/3UFC5UFJ6VdaP2mot9XY/aL18O1Kt9NDE\n\tSAltoO9HNjkAgQ==","X-Google-Smtp-Source":"AOwi7QCbFWKCgKU8x+bkDCxZy0l5/yNDRohpLNzwCp+a/sZxsoeXA+HT4b3/JZKh8WhM5XU/70IYTA==","X-Received":"by 10.159.198.10 with SMTP id f10mr11874487plo.14.1505488203079; \n\tFri, 15 Sep 2017 08:10:03 -0700 (PDT)","Date":"Fri, 15 Sep 2017 08:09:57 -0700","From":"Thierry Reding ","To":"Linus Walleij ","Cc":"Jonathan Hunter ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-tegra@vger.kernel.org\" ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\text Tony Lindgren ","Subject":"Re: [PATCH 00/16] gpio: Tight IRQ chip integration and banked\n\tinfrastructure","Message-ID":"<20170914185233.GA6410@aiwendil>","References":"<20170901185736.28051-1-thierry.reding@gmail.com>\n\t","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha256;\n\tprotocol=\"application/pgp-signature\"; boundary=\"4Ckj6UjgE2iN1+kY\"","Content-Disposition":"inline","In-Reply-To":"","User-Agent":"Mutt/1.9.0 (2017-09-02)","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1769303,"web_url":"http://patchwork.ozlabs.org/comment/1769303/","msgid":"<20170915165750.GW5024@atomide.com>","list_archive_url":null,"date":"2017-09-15T16:57:51","subject":"Re: [PATCH 00/16] gpio: Tight IRQ chip integration and banked\n\tinfrastructure","submitter":{"id":365,"url":"http://patchwork.ozlabs.org/api/people/365/","name":"Tony Lindgren","email":"tony@atomide.com"},"content":"* Thierry Reding [170915 08:10]:\n> On Thu, Sep 14, 2017 at 03:54:56PM +0200, Linus Walleij wrote:\n> > Sorry about that. Let's move ahead with this now, it is neat and\n> > clean.\n> > \n> > What I want (as maintainer) is a bit of fingerpointing at the drivers\n> > that need to be converted to use the new banking infrastructure\n> > so they don't stay with their old crappy design pattern. OMAP is\n> > a clear candidate right? (Added Tony to CC...)\n> \n> OMAP should be able to use this infrastructure, but it may not want to\n> because the semantics would change slightly. Currently OMAP registers a\n> GPIO chip for each bank, whereas this infrastructure exposes multiple\n> banks via a single chip.\n\nOh so you don't have separate interrupts for the instances?\nThanks for clarifying that.\n\n> There might be some userspace that relies on the existence of multiple\n> chips, but Tony can probably knows that better than I.\n\nOn omaps, each bank is a separate driver instance with it's own\ninterrupt. Maybe really all we need to do is get rid of the \"bank\"\nnaming, I think that's left over from 15 years ago when we did not\nhave separate driver instances. It seems we should s/bank/ddata/\non the driver to avoid confusion.\n\nGrygorii, any comments?\n\nRegards,\n\nTony\n--\nTo unsubscribe from this list: send the line \"unsubscribe linux-gpio\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xv1mk1gJBz9s7m\n\tfor ;\n\tSat, 16 Sep 2017 02:57:57 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1750841AbdIOQ54 convert rfc822-to-8bit (ORCPT\n\t);\n\tFri, 15 Sep 2017 12:57:56 -0400","from muru.com ([72.249.23.125]:40786 \"EHLO muru.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1750825AbdIOQ5z (ORCPT );\n\tFri, 15 Sep 2017 12:57:55 -0400","from atomide.com (localhost [127.0.0.1])\n\tby muru.com (Postfix) with ESMTPS id C7607816A;\n\tFri, 15 Sep 2017 16:58:34 +0000 (UTC)"],"Date":"Fri, 15 Sep 2017 09:57:51 -0700","From":"Tony Lindgren ","To":"Thierry Reding ","Cc":"Linus Walleij ,\n\tJonathan Hunter ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-tegra@vger.kernel.org\" ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\tGrygorii Strashko , linux-omap@vger.kernel.org","Subject":"Re: [PATCH 00/16] gpio: Tight IRQ chip integration and banked\n\tinfrastructure","Message-ID":"<20170915165750.GW5024@atomide.com>","References":"<20170901185736.28051-1-thierry.reding@gmail.com>\n\t\n\t<20170914185233.GA6410@aiwendil>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","Content-Transfer-Encoding":"8BIT","In-Reply-To":"<20170914185233.GA6410@aiwendil>","User-Agent":"Mutt/1.8.3 (2017-05-23)","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1769497,"web_url":"http://patchwork.ozlabs.org/comment/1769497/","msgid":"","list_archive_url":null,"date":"2017-09-15T22:26:22","subject":"Re: [PATCH 00/16] gpio: Tight IRQ chip integration and banked\n\tinfrastructure","submitter":{"id":25084,"url":"http://patchwork.ozlabs.org/api/people/25084/","name":"Grygorii Strashko","email":"grygorii.strashko@ti.com"},"content":"On 09/15/2017 11:57 AM, Tony Lindgren wrote:\n> * Thierry Reding [170915 08:10]:\n>> On Thu, Sep 14, 2017 at 03:54:56PM +0200, Linus Walleij wrote:\n>>> Sorry about that. Let's move ahead with this now, it is neat and\n>>> clean.\n>>>\n>>> What I want (as maintainer) is a bit of fingerpointing at the drivers\n>>> that need to be converted to use the new banking infrastructure\n>>> so they don't stay with their old crappy design pattern. OMAP is\n>>> a clear candidate right? (Added Tony to CC...)\n>>\n>> OMAP should be able to use this infrastructure, but it may not want to\n>> because the semantics would change slightly. Currently OMAP registers a\n>> GPIO chip for each bank, whereas this infrastructure exposes multiple\n>> banks via a single chip.\n> \n> Oh so you don't have separate interrupts for the instances?\n> Thanks for clarifying that.\n> \n>> There might be some userspace that relies on the existence of multiple\n>> chips, but Tony can probably knows that better than I.\n> \n> On omaps, each bank is a separate driver instance with it's own\n> interrupt. Maybe really all we need to do is get rid of the \"bank\"\n> naming, I think that's left over from 15 years ago when we did not\n> have separate driver instances. It seems we should s/bank/ddata/\n> on the driver to avoid confusion.\n> \n> Grygorii, any comments?\n\nSry, for delayed reply - I've saw this series, but, honestly, it's very big \nchange for review :(\n\nSo, can it be split? I think, patches which reorganize gpio irqchip specific fields placement \nand move them in gpio_irq_chip can be considered separately if they will not introduce\nfunctional changes. Also, omap changes can be considered separately.\n(Pay attention that new fields introduced in patch 1). \n\nRegarding OMAP GPIO - right now I do not see how it can be applied for OMAP :(\nEach OMAP GPIO bank is standalone device which can be enabled/disabled, \npowered on/off in Linux. There are no contiguous MMIO space and each GPIO\nbank have separate MMIO space.\n\nI really, need more time to review this idea and I think that it can be done\nmore easily if series size will be reduced.\n\nFew more notes:\n- pay attention on commit dc749a0 \"gpiolib: allow gpio irqchip to map irqs dynamically\"\n- good to see binding and DT examples\n- not sure if I've got idea of encoding bank&pin in spec[0] :(\n\n+\tbank = (spec[0] >> gc->of_gpio_bank_mask) & gc->of_gpio_bank_shift;\n+\tpin = (spec[0] >> gc->of_gpio_pin_mask) & gc->of_gpio_pin_shift;\n\n- irq \"mapping\" inside gpio_irq_chip is not clear :( does it static?\ndoes it require one array item/per pin - sry, this is waste of memory?\n\nirq->map[offset + j] = irq->parents[parent];\n\nPotentially, this feature can be applied to Davinci GPIO driver, which\nis GPIO controller divided in multiple logical banks and which also have\nset of common registers for all logical banks. But, again, not sure how\neffective this implementation is - need more time. As of now, we perfectly \nhandle this in Davinci GPIO driver by creating only ONE gpio_chip which hides\nHW details in driver and still uses standard irq DT mappings:\n <&gpio0 140 GPIO_ACTIVE_LOW>;\n\nBy the way Patch 14 adds 300 lines, while patch changes 200 lines, so\nin terms of code lines this feature seems is not very efficient.\n(same for Patch 15, 16)","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"kHPbtF2L\";\n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xv9453Pkwz9s5L\n\tfor ;\n\tSat, 16 Sep 2017 08:26:45 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751230AbdIOW0c (ORCPT );\n\tFri, 15 Sep 2017 18:26:32 -0400","from lelnx193.ext.ti.com ([198.47.27.77]:36722 \"EHLO\n\tlelnx193.ext.ti.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750871AbdIOW0a (ORCPT\n\t); Fri, 15 Sep 2017 18:26:30 -0400","from dflxv15.itg.ti.com ([128.247.5.124])\n\tby lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8FMQNNp016279; \n\tFri, 15 Sep 2017 17:26:23 -0500","from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113])\n\tby dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8FMQNIB010972;\n\tFri, 15 Sep 2017 17:26:23 -0500","from [128.247.59.147] (128.247.59.147) by DLEE70.ent.ti.com\n\t(157.170.170.113) with Microsoft SMTP Server id 14.3.294.0;\n\tFri, 15 Sep 2017 17:26:22 -0500"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1505514383;\n\tbh=P1+DGRdTfcy9udBkuWIjyMEZNs8WvGbOT5/qAHzUmEM=;\n\th=Subject:To:CC:References:From:Date:In-Reply-To;\n\tb=kHPbtF2Lc0N+aMJUzQ03DPV4qMmgftTJOPgxtetnIEa30u/AGVf2ExMvyLCBZptli\n\tjClcL+F8S863GQgu/UQgn4NdSoCTvn3u769scve/t2rGfj4Poov/JpXJTu6iK2Lxxp\n\tLoJuVWuWYZ6HatSKnxNuABluovazUnKqg7euEmYI=","Subject":"Re: [PATCH 00/16] gpio: Tight IRQ chip integration and banked\n\tinfrastructure","To":"Tony Lindgren ,\n\tThierry Reding ","CC":"Linus Walleij ,\n\tJonathan Hunter ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-tegra@vger.kernel.org\" ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\t","References":"<20170901185736.28051-1-thierry.reding@gmail.com>\n\t\n\t<20170914185233.GA6410@aiwendil> <20170915165750.GW5024@atomide.com>","From":"Grygorii Strashko ","Message-ID":"","Date":"Fri, 15 Sep 2017 17:26:22 -0500","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20170915165750.GW5024@atomide.com>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-Originating-IP":"[128.247.59.147]","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1772749,"web_url":"http://patchwork.ozlabs.org/comment/1772749/","msgid":"","list_archive_url":null,"date":"2017-09-21T12:06:35","subject":"Re: [PATCH 00/16] gpio: Tight IRQ chip integration and banked\n\tinfrastructure","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Fri, Sep 15, 2017 at 6:57 PM, Tony Lindgren wrote:\n\n> On omaps, each bank is a separate driver instance with it's own\n> interrupt. Maybe really all we need to do is get rid of the \"bank\"\n> naming, I think that's left over from 15 years ago when we did not\n> have separate driver instances. It seems we should s/bank/ddata/\n> on the driver to avoid confusion.\n\nOK sorry maybe OMAP is not a target for this, I just thought so\nsince it was one of the platforms that is patches in the patch\nseries.\n\nBut I'm pretty sure we have chips with banking like this: separate\ninterrupts but a single device. I would have to read through them\nall I guess.\n\nYours,\nLinus Walleij\n--\nTo unsubscribe from this list: send the line \"unsubscribe linux-gpio\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"O15QACSJ\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyb243WBSz9t43\n\tfor ;\n\tThu, 21 Sep 2017 22:06:52 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751661AbdIUMGi (ORCPT );\n\tThu, 21 Sep 2017 08:06:38 -0400","from mail-io0-f181.google.com ([209.85.223.181]:56807 \"EHLO\n\tmail-io0-f181.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751550AbdIUMGh (ORCPT\n\t); Thu, 21 Sep 2017 08:06:37 -0400","by mail-io0-f181.google.com with SMTP id m103so10190216iod.13\n\tfor ;\n\tThu, 21 Sep 2017 05:06:36 -0700 (PDT)","by 10.79.164.78 with HTTP; Thu, 21 Sep 2017 05:06:35 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=MbcvMmPGrqW5Bf6H0Web5CVc0qOaGKnna+UA6NfdvnM=;\n\tb=O15QACSJsSJLTkMiZDhO/hkcM+47RaUyqJJxIBogBwnqUY5wcNjmucHZfh8TexKMtK\n\ttyuQSaQI91/dzW8lo6zmyA7FuCPJvkfXOJ40ttLbkH7McZJKHRwK5XD6xfsXjjJ7aHPk\n\tiyOjOltunONWcTBFUUMGtxg6NgB+Z7PnynWEo=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=MbcvMmPGrqW5Bf6H0Web5CVc0qOaGKnna+UA6NfdvnM=;\n\tb=Xl1xpxgrAG6g6ydZxF4v/aM4Hi6lrM/3pmhKldGpRRhUlhlC7vY5ySm3gi0F5GD6+q\n\tWgKfvOUwM/WkKG+8fgUMOCu5mvBWdhHWdL40jVanvYy3bh9nNpzLrvDRqwVZ8hwgeL2E\n\tkYOQ4vFwJ1b3LDGqTIB8tCKReDuPd+c8Erp93b0SrWD2FhtF9k97v124eFFCpoTnnrR6\n\t6hznozvvDZN/hcfPglsk/oau//Q/RqGPW8ajSixNo6cE32bguy7dFioyWwPwV/b6TRYZ\n\tj903lBv7DtdQPHYoU52IOzx4m062kgQrm78+Jqk+LZXAMprv/C6/Jhr4Qc7iL57/KD1W\n\ttEHA==","X-Gm-Message-State":"AHPjjUjlXo2J0sU8+EeCb1eX3zAaAuBjPR8vPIb7TiV6VOev21o6DWcs\n\topelUQCxbBxPF88Ieo4X4LFL9ybyb2yuZOpp/vxMWQ==","X-Google-Smtp-Source":"AOwi7QDDujOjGjJE8slU2r1lN0HQXZgSUOkwoyvvcVS+9z963krE0FMOffTet1X2REEPDrOslnMbsykMJNJWEhOR4Xc=","X-Received":"by 10.107.139.215 with SMTP id\n\tn206mr2697932iod.155.1505995596468; \n\tThu, 21 Sep 2017 05:06:36 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170915165750.GW5024@atomide.com>","References":"<20170901185736.28051-1-thierry.reding@gmail.com>\n\t\n\t<20170914185233.GA6410@aiwendil> <20170915165750.GW5024@atomide.com>","From":"Linus Walleij ","Date":"Thu, 21 Sep 2017 14:06:35 +0200","Message-ID":"","Subject":"Re: [PATCH 00/16] gpio: Tight IRQ chip integration and banked\n\tinfrastructure","To":"Tony Lindgren ","Cc":"Thierry Reding ,\n\tJonathan Hunter ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\t\"linux-tegra@vger.kernel.org\" ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\tGrygorii Strashko ,\n\tLinux-OMAP ","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}}]