[{"id":1762683,"web_url":"http://patchwork.ozlabs.org/comment/1762683/","msgid":"","list_archive_url":null,"date":"2017-09-04T14:24:05","subject":"Re: [PATCH v2 1/3] arm: npcm: add basic support for Nuvoton BMCs","submitter":{"id":72291,"url":"http://patchwork.ozlabs.org/api/people/72291/","name":"Tomer Maimon","email":"tmaimon77@gmail.com"},"content":"On 1 September 2017 at 01:53, Brendan Higgins wrote:\n> Adds basic support for the Nuvoton NPCM750 BMC.\n>\n> Signed-off-by: Brendan Higgins \n> ---\n> arch/arm/Kconfig | 2 +\n> arch/arm/Makefile | 1 +\n> arch/arm/mach-npcm/Kconfig | 58 +++++++++++++++\n> arch/arm/mach-npcm/Makefile | 3 +\n> arch/arm/mach-npcm/headsmp.S | 120 +++++++++++++++++++++++++++++++\n> arch/arm/mach-npcm/npcm7xx.c | 34 +++++++++\n> arch/arm/mach-npcm/platsmp.c | 168 +++++++++++++++++++++++++++++++++++++++++++\n> 7 files changed, 386 insertions(+)\n> create mode 100644 arch/arm/mach-npcm/Kconfig\n> create mode 100644 arch/arm/mach-npcm/Makefile\n> create mode 100644 arch/arm/mach-npcm/headsmp.S\n> create mode 100644 arch/arm/mach-npcm/npcm7xx.c\n> create mode 100644 arch/arm/mach-npcm/platsmp.c\n>\n> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\n> index 61a0cb15067e..05543f1cfbde 100644\n> --- a/arch/arm/Kconfig\n> +++ b/arch/arm/Kconfig\n> @@ -782,6 +782,8 @@ source \"arch/arm/mach-netx/Kconfig\"\n>\n> source \"arch/arm/mach-nomadik/Kconfig\"\n>\n> +source \"arch/arm/mach-npcm/Kconfig\"\n> +\n> source \"arch/arm/mach-nspire/Kconfig\"\n>\n> source \"arch/arm/plat-omap/Kconfig\"\n> diff --git a/arch/arm/Makefile b/arch/arm/Makefile\n> index 47d3a1ab08d2..60ca50c7d762 100644\n> --- a/arch/arm/Makefile\n> +++ b/arch/arm/Makefile\n> @@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MEDIATEK) += mediatek\n> machine-$(CONFIG_ARCH_MXS) += mxs\n> machine-$(CONFIG_ARCH_NETX) += netx\n> machine-$(CONFIG_ARCH_NOMADIK) += nomadik\n> +machine-$(CONFIG_ARCH_NPCM) += npcm\n> machine-$(CONFIG_ARCH_NSPIRE) += nspire\n> machine-$(CONFIG_ARCH_OXNAS) += oxnas\n> machine-$(CONFIG_ARCH_OMAP1) += omap1\n> diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig\n> new file mode 100644\n> index 000000000000..a45670e516b4\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/Kconfig\n> @@ -0,0 +1,58 @@\n> +menuconfig ARCH_NPCM\n> + bool \"Nuvoton NPCM Architecture\"\n> + select ARCH_REQUIRE_GPIOLIB\n> + select USE_OF\n> + select PINCTRL\n> + select PINCTRL_NPCM7XX\n> +\n> +if ARCH_NPCM\n> +\n> +comment \"NPCMX50 CPU type\"\n> +\n> +config CPU_NPCM750\n> + depends on ARCH_NPCM && ARCH_MULTI_V7 && !CPU_V6 && !CPU_V6K\n> + bool \"Support for NPCM750 BMC CPU (Poleg)\"\n> + select CACHE_L2X0\n> + select CPU_V7\n> + select ARM_GIC\n> + select ARM_ERRATA_754322\n> + select ARM_ERRATA_764369\n> + select USB_EHCI_ROOT_HUB_TT\n> + select USB_ARCH_HAS_HCD\n> + select USB_ARCH_HAS_EHCI\n> + select USB_EHCI_HCD\n> + select USB_ARCH_HAS_OHCI\n> + select USB_OHCI_HCD\n> + select USB\n> + select FIQ\n> + select CPU_USE_DOMAINS\n> + select COMMON_CLK if OF\n> + select NPCM750_TIMER\n> + select MFD_SYSCON\n> + help\n> + Support for single core NPCM750 BMC CPU (Poleg).\n> +\n> + Single core variant of the Nuvoton NPCM750 BMC based on the Cortex A9.\n> +\n> +config CPU_NPCM750_SMP\n> + depends on CPU_NPCM750\n> + bool \"Support for NPCM750 BMC CPU SMP (Poleg)\"\n> + select HAVE_SMP\n> + select HAVE_ARM_SCU\n> + select ARM_ERRATA_794072\n> + select PL310_ERRATA_588369\n> + select PL310_ERRATA_727915\n> + select ARM_ERRATA_720789\n> + select DEBUG_SPINLOCK\n> + select GENERIC_CLOCKEVENTS\n> + select SMP\n> + select HAVE_ARM_TWD if SMP\n> + select HAVE_ARM_SCU if SMP\n> + select CLKDEV_LOOKUP\n> + select COMMON_CLK if OF\n> + help\n> + Support for dual core NPCM750 BMC CPU (Poleg).\n> +\n> + Dual core variant of the Nuvoton NPCM750 BMC based on the Cortex A9.\n> +\n> +endif\n> diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile\n> new file mode 100644\n> index 000000000000..634e7c4d6b98\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/Makefile\n> @@ -0,0 +1,3 @@\n> +obj-$(CONFIG_CPU_NPCM750_SMP) += platsmp.o headsmp.o\n> +\n> +obj-$(CONFIG_CPU_NPCM750) += npcm7xx.o\n> diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S\n> new file mode 100644\n> index 000000000000..d22d2fc1a35c\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/headsmp.S\n> @@ -0,0 +1,120 @@\n> +/*\n> + * linux/arch/arm/mach-realview/headsmp.S\n> + *\n> + * Copyright (c) 2003 ARM Limited\n> + * Copyright 2017 Google, Inc.\n> + * All Rights Reserved\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation.\n> + */\n> +\n> +#include \n> +#include \n> +\n> +.equ SVC_MODE, 0x13\n> +.equ I_BIT, 0x80\n> +.equ F_BIT, 0x40\n> +\n> +ENTRY(npcm7xx_wakeup_z1)\n> + stmfd sp!, {r0-r12, lr}\n> + ldr r0, =0x01\n> + ldr r1, =0x01\n> + ldr r2, =0x01\n> +\n> + and r3, r0, #0x0F /* Mask off unused bits of ID, and move to r3 */\n> + and r1, r1, #0x0F /* Mask off unused bits of target_filter */\n> + and r2, r2, #0x0F /* Mask off unused bits of filter_list */\n> +\n> + orr r3, r3, r1, LSL #16 /* Combine ID and target_filter */\n> + orr r3, r3, r2, LSL #24 /* and now the filter list */\n> +\n> + /* Get the address of the GIC */\n> + mrc p15, 4, r0, c15, c0, 0 /* Read periph base address */\n> + add r0, r0, #0x1F00 /* Add offset of the sgi_trigger reg */\n> +\n> + /* Write to the Software Generated Interrupt Register (ICDSGIR) */\n> + str r3, [r0]\n> +\n> + ldmfd sp!, {r0-r12, pc}\n> +ENDPROC(npcm7xx_wakeup_z1)\n> +\n> +ENTRY(v7_invalidate_l1_npcmX50)\n> + mov r0, #0\n> + mcr p15, 0, r0, c7, c5, 0 /* invalidate I cache */\n> + mcr p15, 2, r0, c0, c0, 0\n> + mrc p15, 1, r0, c0, c0, 0\n> +\n> + ldr r1, =0x7fff\n> + and r2, r1, r0, lsr #13\n> +\n> + ldr r1, =0x3ff\n> +\n> + and r3, r1, r0, lsr #3 /* NumWays - 1 */\n> + add r2, r2, #1 /* NumSets */\n> +\n> + and r0, r0, #0x7\n> + add r0, r0, #4 /* SetShift */\n> +\n> + clz r1, r3 /* WayShift */\n> + add r4, r3, #1 /* NumWays */\n> +1: sub r2, r2, #1 /* NumSets-- */\n> + mov r3, r4 /* Temp = NumWays */\n> +2: subs r3, r3, #1 /* Temp-- */\n> + mov r5, r3, lsl r1\n> + mov r6, r2, lsl r0\n> + /* Reg = (Temp << WayShift) | (NumSets << SetShift) */\n> + orr r5, r5, r6\n> + mcr p15, 0, r5, c7, c6, 2\n> + bgt 2b\n> + cmp r2, #0\n> + bgt 1b\n> + dsb\n> + isb\n> + mov pc, lr\n> +ENDPROC(v7_invalidate_l1_npcmX50)\n> +\n> +/*\n> + * MSM specific entry point for secondary CPUs. This provides\n> + * a \"holding pen\" into which all secondary cores are held until we're\n> + * ready for them to initialise.\n> + */\n> +ENTRY(npcm7xx_secondary_startup)\n> + msr CPSR_c, #(SVC_MODE)\n> +\n> + bl v7_invalidate_l1_npcmX50\n> + /* disable vector table remapping */\n> + mrc p15, 0,r0, c1, c0, 0\n> + and r0, #0xffffdfff\n> + mcr p15, 0,r0, c1, c0, 0\n> +\n> +#ifdef CONFIG_CACHE_L2X0\n> + /* Enable L1 & L2 prefetch + Zero line */\n> + mrc p15, 0, r0, c1, c0, 1\n> + orr r0, r0, #(7 << 1)\n> + mcr p15, 0, r0, c1, c0, 1\n> +#endif /* CONFIG_CACHE_L2X0 */\n> +\n> + mrc p15, 0, r0, c0, c0, 5\n> + and r0, r0, #15\n> + adr r4, 1f\n> + ldmia r4, {r5, r6}\n> + sub r4, r4, r5\n> + add r6, r6, r4\n> + str r3,[r2]\n> +\n> +pen: ldr r7, [r6]\n> + cmp r7, r0\n> + bne pen\n> +\n> + /*\n> + * we've been released from the holding pen: secondary_stack\n> + * should now contain the SVC stack for this core\n> + */\n> + b secondary_startup\n> +ENDPROC(npcm7xx_secondary_startup)\n> +\n> + .align\n> +1: .long .\n> + .long pen_release\n> diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c\n> new file mode 100644\n> index 000000000000..106dc62dd62b\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/npcm7xx.c\n> @@ -0,0 +1,34 @@\n> +/*\n> + * Copyright (c) 2014 Nuvoton Technology corporation.\n> + * Copyright 2017 Google, Inc.\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License as published by\n> + * the Free Software Foundation;version 2 of the License.\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#define NPCM7XX_AUX_VAL (L310_AUX_CTRL_INSTR_PREFETCH | \\\n> + L310_AUX_CTRL_DATA_PREFETCH | \\\n> + L310_AUX_CTRL_NS_LOCKDOWN | \\\n> + L310_AUX_CTRL_CACHE_REPLACE_RR | \\\n> + L2C_AUX_CTRL_SHARED_OVERRIDE | \\\n> + L310_AUX_CTRL_FULL_LINE_ZERO)\n> +\n> +static const char *const npcm7xx_dt_match[] = {\n> + \"nuvoton,npcm750\",\n> + NULL\n> +};\n> +\n> +DT_MACHINE_START(NPCM7XX_DT, \"NPCMX50 Chip family\")\n> + .atag_offset = 0x100,\n> + .dt_compat = npcm7xx_dt_match,\n> + .l2c_aux_val = NPCM7XX_AUX_VAL,\n> + .l2c_aux_mask = ~NPCM7XX_AUX_VAL,\n> +MACHINE_END\n> diff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c\n> new file mode 100644\n> index 000000000000..4b53adb467fc\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/platsmp.c\n> @@ -0,0 +1,168 @@\n> +/*\n> + * Copyright (C) 2002 ARM Ltd.\n> + * Copyright (C) 2008 STMicroelctronics.\n> + * Copyright (C) 2009 ST-Ericsson.\n> + * Copyright 2017 Google, Inc.\n> + *\n> + * This file is based on arm realview platform\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation.\n> + */\n> +\n> +#define pr_fmt(fmt) \"PLATSMP: \" fmt\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#define NPCM7XX_SCRPAD_REG 0x13c\n> +\n> +static void __iomem *gcr_base;\n> +static void __iomem *scu_base;\n> +\n> +/* This is called from headsmp.S to wakeup the secondary core */\n> +extern void npcm7xx_secondary_startup(void);\n> +extern void npcm7xx_wakeup_z1(void);\n> +\n> +/*\n> + * Write pen_release in a way that is guaranteed to be visible to all\n> + * observers, irrespective of whether they're taking part in coherency\n> + * or not. This is necessary for the hotplug code to work reliably.\n> + */\n> +static void npcm7xx_write_pen_release(int val)\n> +{\n> + pen_release = val;\n> + /* write to pen_release must be visible to all observers. */\n> + smp_wmb();\n> + __cpuc_flush_dcache_area((void *) &pen_release, sizeof(pen_release));\n> + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));\n> +}\n> +\n> +static DEFINE_SPINLOCK(boot_lock);\n> +\n> +static void npcm7xx_smp_secondary_init(unsigned int cpu)\n> +{\n> + /*\n> + * let the primary processor know we're out of the\n> + * pen, then head off into the C entry point\n> + */\n> + npcm7xx_write_pen_release(-1);\n> +\n> + /*\n> + * Synchronise with the boot thread.\n> + */\n> + spin_lock(&boot_lock);\n> + spin_unlock(&boot_lock);\n> +}\n> +\n> +static int npcm7xx_smp_boot_secondary(unsigned int cpu, struct task_struct *idle)\n> +{\n> + unsigned long timeout;\n> +\n> + if (!gcr_base)\n> + return -EIO;\n> +\n> + /*\n> + * set synchronisation state between this boot processor\n> + * and the secondary one\n> + */\n> + spin_lock(&boot_lock);\n> +\n> + /*\n> + * The secondary processor is waiting to be released from\n> + * the holding pen - release it, then wait for it to flag\n> + * that it has been released by resetting pen_release.\n> + */\n> + npcm7xx_write_pen_release(cpu_logical_map(cpu));\n> + iowrite32(virt_to_phys(npcm7xx_secondary_startup),\n> + gcr_base + NPCM7XX_SCRPAD_REG);\n> + /* make npcm7xx_secondary_startup visible to all observers. */\n> + smp_rmb();\n> +\n> + arch_send_wakeup_ipi_mask(cpumask_of(cpu));\n> + timeout = jiffies + (HZ * 1);\n> + while (time_before(jiffies, timeout)) {\n> + /* make sure we see any writes to pen_release. */\n> + smp_rmb();\n> + if (pen_release == -1)\n> + break;\n> +\n> + udelay(10);\n> + }\n> +\n> + /*\n> + * now the secondary core is starting up let it run its\n> + * calibrations, then wait for it to finish\n> + */\n> + spin_unlock(&boot_lock);\n> +\n> + return pen_release != -1 ? -EIO : 0;\n> +}\n> +\n> +\n> +static void __init npcm7xx_wakeup_secondary(void)\n> +{\n> + /*\n> + * write the address of secondary startup into the backup ram register\n> + * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the\n> + * backup ram register at offset 0x1FF0, which is what boot rom code\n> + * is waiting for. This would wake up the secondary core from WFE\n> + */\n> + iowrite32(virt_to_phys(npcm7xx_secondary_startup), gcr_base +\n> + NPCM7XX_SCRPAD_REG);\n> + /* make sure npcm7xx_secondary_startup is seen by all observers. */\n> + smp_wmb();\n> + dsb_sev();\n> +\n> + /* make sure write buffer is drained */\n> + mb();\n> +}\n> +\n> +static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)\n> +{\n> + struct device_node *gcr_np, *scu_np;\n> +\n> + gcr_np = of_find_compatible_node(NULL, NULL, \"nuvoton,npcm750-gcr\");\n> + if (!gcr_np) {\n> + pr_err(\"no gcr device node\\n\");\n> + return;\n> + }\n> + gcr_base = of_iomap(gcr_np, 0);\n> + if (!gcr_base) {\n> + pr_err(\"could not iomap gcr at: 0x%llx\\n\", gcr_base);\n> + return;\n> + }\n> +\n> + scu_np = of_find_compatible_node(NULL, NULL, \"arm,cortex-a9-scu\");\n> + if (!scu_np) {\n> + pr_err(\"no scu device node\\n\");\n> + return;\n> + }\n> + scu_base = of_iomap(scu_np, 0);\n> + if (!scu_base) {\n> + pr_err(\"could not iomap gcr at: 0x%llx\\n\", scu_base);\n> + return;\n> + }\n> +\n> + scu_enable(scu_base);\n> + npcm7xx_wakeup_secondary();\n> +}\n> +\n> +static struct smp_operations npcm7xx_smp_ops __initdata = {\n> + .smp_prepare_cpus = npcm7xx_smp_prepare_cpus,\n> + .smp_boot_secondary = npcm7xx_smp_boot_secondary,\n> + .smp_secondary_init = npcm7xx_smp_secondary_init,\n> +};\n> +\n> +CPU_METHOD_OF_DECLARE(npcm7xx_smp, \"nuvoton,npcm7xx-smp\", &npcm7xx_smp_ops);\n> --\n> 2.14.1.581.gf28d330327-goog\n>\n\nReviewed-by: Tomer Maimon \nTested-by: Tomer Maimon \n\nReviewed-by: Avi Fishman \nTested-by: Avi Fishman \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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\n\tMon, 04 Sep 2017 07:24:06 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170831225400.19756-2-brendanhiggins@google.com>","References":"<20170831225400.19756-1-brendanhiggins@google.com>\n\t<20170831225400.19756-2-brendanhiggins@google.com>","From":"Tomer Maimon ","Date":"Mon, 4 Sep 2017 17:24:05 +0300","Message-ID":"","Subject":"Re: [PATCH v2 1/3] arm: npcm: add basic support for Nuvoton BMCs","To":"Brendan Higgins ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk,\n\tavifishman70@gmail.com, raltherr@google.com,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, openbmc@lists.ozlabs.org","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1762686,"web_url":"http://patchwork.ozlabs.org/comment/1762686/","msgid":"","list_archive_url":null,"date":"2017-09-04T14:25:11","subject":"Re: [PATCH v2 3/3] MAINTAINERS: Add entry for the Nuvoton NPCM\n\tarchitecture","submitter":{"id":72291,"url":"http://patchwork.ozlabs.org/api/people/72291/","name":"Tomer Maimon","email":"tmaimon77@gmail.com"},"content":"On 1 September 2017 at 01:54, Brendan Higgins wrote:\n> Add maintainers and reviewers for the Nuvoton NPCM architecture.\n>\n> Signed-off-by: Brendan Higgins \n> ---\n> MAINTAINERS | 13 +++++++++++++\n> 1 file changed, 13 insertions(+)\n>\n> diff --git a/MAINTAINERS b/MAINTAINERS\n> index 44cb004c765d..67064bf11904 100644\n> --- a/MAINTAINERS\n> +++ b/MAINTAINERS\n> @@ -1598,6 +1598,19 @@ F: drivers/pinctrl/nomadik/\n> F: drivers/i2c/busses/i2c-nomadik.c\n> T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git\n>\n> +ARM/NUVOTON NPCM ARCHITECTURE\n> +M: Avi Fishman \n> +M: Tomer Maimon \n> +R: Brendan Higgins \n> +R: Rick Altherr \n> +L: openbmc@lists.ozlabs.org (moderated for non-subscribers)\n> +S: Maintained\n> +F: arch/arm/mach-npcm/\n> +F: arch/arm/boot/dts/nuvoton-npcm*\n> +F: include/dt-bindings/clock/nuvoton,npcm7xx-clks.h\n> +F: drivers/*/*npcm*\n> +F: Documentation/*/*npcm*\n> +\n> ARM/NUVOTON W90X900 ARM ARCHITECTURE\n> M: Wan ZongShun \n> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)\n> --\n> 2.14.1.581.gf28d330327-goog\n>\n\nReviewed-by: Tomer Maimon \nTested-by: Tomer Maimon \n\nReviewed-by: Avi Fishman \nTested-by: Avi Fishman \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1762923,"web_url":"http://patchwork.ozlabs.org/comment/1762923/","msgid":"<8fd55a57-946d-f53f-e10b-c73d1f70d1dc@gmail.com>","list_archive_url":null,"date":"2017-09-05T02:47:16","subject":"Re: [PATCH v2 1/3] arm: npcm: add basic support for Nuvoton BMCs","submitter":{"id":2800,"url":"http://patchwork.ozlabs.org/api/people/2800/","name":"Florian Fainelli","email":"f.fainelli@gmail.com"},"content":"Le 08/31/17 à 15:53, Brendan Higgins a écrit :\n> Adds basic support for the Nuvoton NPCM750 BMC.\n> \n> Signed-off-by: Brendan Higgins \n> ---\n> arch/arm/Kconfig | 2 +\n> arch/arm/Makefile | 1 +\n> arch/arm/mach-npcm/Kconfig | 58 +++++++++++++++\n> arch/arm/mach-npcm/Makefile | 3 +\n> arch/arm/mach-npcm/headsmp.S | 120 +++++++++++++++++++++++++++++++\n> arch/arm/mach-npcm/npcm7xx.c | 34 +++++++++\n> arch/arm/mach-npcm/platsmp.c | 168 +++++++++++++++++++++++++++++++++++++++++++\n> 7 files changed, 386 insertions(+)\n> create mode 100644 arch/arm/mach-npcm/Kconfig\n> create mode 100644 arch/arm/mach-npcm/Makefile\n> create mode 100644 arch/arm/mach-npcm/headsmp.S\n> create mode 100644 arch/arm/mach-npcm/npcm7xx.c\n> create mode 100644 arch/arm/mach-npcm/platsmp.c\n> \n> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\n> index 61a0cb15067e..05543f1cfbde 100644\n> --- a/arch/arm/Kconfig\n> +++ b/arch/arm/Kconfig\n> @@ -782,6 +782,8 @@ source \"arch/arm/mach-netx/Kconfig\"\n> \n> source \"arch/arm/mach-nomadik/Kconfig\"\n> \n> +source \"arch/arm/mach-npcm/Kconfig\"\n> +\n> source \"arch/arm/mach-nspire/Kconfig\"\n> \n> source \"arch/arm/plat-omap/Kconfig\"\n> diff --git a/arch/arm/Makefile b/arch/arm/Makefile\n> index 47d3a1ab08d2..60ca50c7d762 100644\n> --- a/arch/arm/Makefile\n> +++ b/arch/arm/Makefile\n> @@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MEDIATEK)\t\t+= mediatek\n> machine-$(CONFIG_ARCH_MXS)\t\t+= mxs\n> machine-$(CONFIG_ARCH_NETX)\t\t+= netx\n> machine-$(CONFIG_ARCH_NOMADIK)\t\t+= nomadik\n> +machine-$(CONFIG_ARCH_NPCM)\t\t+= npcm\n> machine-$(CONFIG_ARCH_NSPIRE)\t\t+= nspire\n> machine-$(CONFIG_ARCH_OXNAS)\t\t+= oxnas\n> machine-$(CONFIG_ARCH_OMAP1)\t\t+= omap1\n> diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig\n> new file mode 100644\n> index 000000000000..a45670e516b4\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/Kconfig\n> @@ -0,0 +1,58 @@\n> +menuconfig ARCH_NPCM\n> +\tbool \"Nuvoton NPCM Architecture\"\n> +\tselect ARCH_REQUIRE_GPIOLIB\n> +\tselect USE_OF\n> +\tselect PINCTRL\n> +\tselect PINCTRL_NPCM7XX\n> +\n> +if ARCH_NPCM\n> +\n> +comment \"NPCMX50 CPU type\"\n> +\n> +config CPU_NPCM750\n> +\tdepends on ARCH_NPCM && ARCH_MULTI_V7 && !CPU_V6 && !CPU_V6K\n\nWhy the !CPU_V6 and !CPU_V6K, you indicate in your cover letter that\nthis is because headsmp.S requires ARMv7 instructions, so just tell the\nassembler that with:\n\nAFLAGS_headsmp.o\t+= -march=armv7-a\n\n> +\tbool \"Support for NPCM750 BMC CPU (Poleg)\"\n> +\tselect CACHE_L2X0\n> +\tselect CPU_V7\n> +\tselect ARM_GIC\n> +\tselect ARM_ERRATA_754322\n> +\tselect ARM_ERRATA_764369\n> +\tselect USB_EHCI_ROOT_HUB_TT\n> +\tselect USB_ARCH_HAS_HCD\n> +\tselect USB_ARCH_HAS_EHCI\n> +\tselect USB_EHCI_HCD\n> +\tselect USB_ARCH_HAS_OHCI\n> +\tselect USB_OHCI_HCD\n> +\tselect USB\n> +\tselect FIQ\n> +\tselect CPU_USE_DOMAINS\n> +\tselect COMMON_CLK if OF\n> +\tselect NPCM750_TIMER\n> +\tselect MFD_SYSCON\n> +\thelp\n> +\t Support for single core NPCM750 BMC CPU (Poleg).\n> +\n> +\t Single core variant of the Nuvoton NPCM750 BMC based on the Cortex A9.\n> +\n> +config CPU_NPCM750_SMP\n> +\tdepends on CPU_NPCM750\n> +\tbool \"Support for NPCM750 BMC CPU SMP (Poleg)\"\n> +\tselect HAVE_SMP\n> +\tselect HAVE_ARM_SCU\n> +\tselect ARM_ERRATA_794072\n> +\tselect PL310_ERRATA_588369\n> +\tselect PL310_ERRATA_727915\n> +\tselect ARM_ERRATA_720789\n> +\tselect DEBUG_SPINLOCK\n> +\tselect GENERIC_CLOCKEVENTS\n> +\tselect SMP\n> +\tselect HAVE_ARM_TWD if SMP\n> +\tselect HAVE_ARM_SCU if SMP\n> +\tselect CLKDEV_LOOKUP\n> +\tselect COMMON_CLK if OF\n> +\thelp\n> +\t Support for dual core NPCM750 BMC CPU (Poleg).\n> +\n> +\t Dual core variant of the Nuvoton NPCM750 BMC based on the Cortex A9.\n\nThis is something that you could determine entirely from Device Tree and\njust have this code unconditionally be built into the kernel and have\nyour SMP operations do nothing if only one CPU is enabled/declared in\nDT. The runtime overhead of running SMP_ON_UP is largely negligible that\nit is worth having fewer configuration options to support.\n\n\n> diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S\n> new file mode 100644\n> index 000000000000..d22d2fc1a35c\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/headsmp.S\n> @@ -0,0 +1,120 @@\n> +/*\n> + * linux/arch/arm/mach-realview/headsmp.S\n\nThe filename no longer matches but this also indicates that this was\nlargely based on the realview board's SMP bring-up code which Russell\nKing repeatedly tells people to move away from since it is made for a\nboard with a ton of limitations.\n\n> + *\n> + * Copyright (c) 2003 ARM Limited\n> + * Copyright 2017 Google, Inc.\n> + * All Rights Reserved\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation.\n> + */\n> +\n> +#include \n> +#include \n> +\n> +.equ SVC_MODE, 0x13\n> +.equ I_BIT, 0x80\n> +.equ F_BIT, 0x40\n\nYou can use the C preprocessor to make this more readable and/or re-use\nexisting defines from other header files.\n\n> +\n> +ENTRY(npcm7xx_wakeup_z1)\n> +\tstmfd\tsp!, {r0-r12, lr}\n> +\tldr\tr0, =0x01\n> +\tldr\tr1, =0x01\n> +\tldr\tr2, =0x01\n> +\n> +\tand\tr3, r0, #0x0F /* Mask off unused bits of ID, and move to r3 */\n> +\tand\tr1, r1, #0x0F /* Mask off unused bits of target_filter */\n> +\tand\tr2, r2, #0x0F /* Mask off unused bits of filter_list */\n> +\n> +\torr\tr3, r3, r1, LSL #16 /* Combine ID and target_filter */\n> +\torr\tr3, r3, r2, LSL #24 /* and now the filter list */\n> +\n> +\t/* Get the address of the GIC */\n> +\tmrc\tp15, 4, r0, c15, c0, 0 /* Read periph base address */\n> +\tadd\tr0, r0, #0x1F00 /* Add offset of the sgi_trigger reg */\n> +\n> +\t/* Write to the Software Generated Interrupt Register (ICDSGIR) */\n> +\tstr\tr3, [r0]\n\nDon't you need some kind of barrier here?\n\n> +\n> +\tldmfd\tsp!, {r0-r12, pc}\n> +ENDPROC(npcm7xx_wakeup_z1)\n> +\n> +ENTRY(v7_invalidate_l1_npcmX50)\n> +\tmov\tr0, #0\n> +\tmcr\tp15, 0, r0, c7, c5, 0 /* invalidate I cache */\n> +\tmcr\tp15, 2, r0, c0, c0, 0\n> +\tmrc\tp15, 1, r0, c0, c0, 0\n> +\n> +\tldr\tr1, =0x7fff\n> +\tand\tr2, r1, r0, lsr #13\n> +\n> +\tldr\tr1, =0x3ff\n> +\n> +\tand\tr3, r1, r0, lsr #3 /* NumWays - 1 */\n> +\tadd\tr2, r2, #1 /* NumSets */\n> +\n> +\tand\tr0, r0, #0x7\n> +\tadd\tr0, r0, #4 /* SetShift */\n> +\n> +\tclz\tr1, r3 /* WayShift */\n> +\tadd\tr4, r3, #1 /* NumWays */\n> +1:\tsub\tr2, r2, #1 /* NumSets-- */\n> +\tmov\tr3, r4 /* Temp = NumWays */\n> +2:\tsubs\tr3, r3, #1 /* Temp-- */\n> +\tmov\tr5, r3, lsl r1\n> +\tmov\tr6, r2, lsl r0\n> +\t/* Reg = (Temp << WayShift) | (NumSets << SetShift) */\n> +\torr\tr5, r5, r6\n> +\tmcr\tp15, 0, r5, c7, c6, 2\n> +\tbgt\t2b\n> +\tcmp\tr2, #0\n> +\tbgt\t1b\n> +\tdsb\n> +\tisb\n> +\tmov\tpc, lr\n> +ENDPROC(v7_invalidate_l1_npcmX50)\n\nThis looks a lot, if not nearly the same thing as v7_invalidate_l1 which\nis already called by secondary_startup, can you see if you can re-use it\ndirectly?\n\n> +\n> +/*\n> + * MSM specific entry point for secondary CPUs. This provides\n> + * a \"holding pen\" into which all secondary cores are held until we're\n> + * ready for them to initialise.\n> + */\n\nAssuming this was copied from a Qualcomm MSM routine, you may want to\nfix the comment, typo on \"initialis.\n\n> +ENTRY(npcm7xx_secondary_startup)\n> +\tmsr\tCPSR_c, #(SVC_MODE)\n\nIs there a BootROM or something that would not make the secondary cores\nstart in supervisor mode?\n\n> +\n> +\tbl\tv7_invalidate_l1_npcmX50\n> +\t/* disable vector table remapping */\n> +\tmrc\tp15, 0,r0, c1, c0, 0\n> +\tand\tr0, #0xffffdfff\n> +\tmcr\tp15, 0,r0, c1, c0, 0\n> +\n> +#ifdef CONFIG_CACHE_L2X0\n> +\t/* Enable L1 & L2 prefetch + Zero line */\n> +\tmrc\tp15, 0, r0, c1, c0, 1\n> +\torr\tr0, r0, #(7 << 1)\n> +\tmcr\tp15, 0, r0, c1, c0, 1\n> +#endif /* CONFIG_CACHE_L2X0 */\n> +\n> +\tmrc\tp15, 0, r0, c0, c0, 5\n> +\tand\tr0, r0, #15\n> +\tadr\tr4, 1f\n> +\tldmia\tr4, {r5, r6}\n> +\tsub\tr4, r4, r5\n> +\tadd\tr6, r6, r4\n> +\tstr r3,[r2]\n> +\n> +pen:\tldr\tr7, [r6]\n> +\tcmp\tr7, r0\n> +\tbne\tpen\n> +\n> +\t/*\n> +\t * we've been released from the holding pen: secondary_stack\n> +\t * should now contain the SVC stack for this core\n> +\t */\n> +\tb\tsecondary_startup\n> +ENDPROC(npcm7xx_secondary_startup)\n> +\n> +\t.align\n> +1:\t.long\t.\n> +\t.long\tpen_release\n> diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c\n> new file mode 100644\n> index 000000000000..106dc62dd62b\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/npcm7xx.c\n> @@ -0,0 +1,34 @@\n> +/*\n> + * Copyright (c) 2014 Nuvoton Technology corporation.\n> + * Copyright 2017 Google, Inc.\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License as published by\n> + * the Free Software Foundation;version 2 of the License.\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#define NPCM7XX_AUX_VAL (L310_AUX_CTRL_INSTR_PREFETCH |\t\t\t \\\n> +\t\t\t L310_AUX_CTRL_DATA_PREFETCH |\t\t\t \\\n> +\t\t\t L310_AUX_CTRL_NS_LOCKDOWN |\t\t\t \\\n> +\t\t\t L310_AUX_CTRL_CACHE_REPLACE_RR |\t\t \\\n> +\t\t\t L2C_AUX_CTRL_SHARED_OVERRIDE |\t\t\t \\\n> +\t\t\t L310_AUX_CTRL_FULL_LINE_ZERO)\n> +\n> +static const char *const npcm7xx_dt_match[] = {\n> +\t\"nuvoton,npcm750\",\n> +\tNULL\n> +};\n> +\n> +DT_MACHINE_START(NPCM7XX_DT, \"NPCMX50 Chip family\")\n> +\t.atag_offset\t= 0x100,\n> +\t.dt_compat\t= npcm7xx_dt_match,\n> +\t.l2c_aux_val\t= NPCM7XX_AUX_VAL,\n> +\t.l2c_aux_mask\t= ~NPCM7XX_AUX_VAL,\n> +MACHINE_END\n> diff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c\n> new file mode 100644\n> index 000000000000..4b53adb467fc\n> --- /dev/null\n> +++ b/arch/arm/mach-npcm/platsmp.c\n> @@ -0,0 +1,168 @@\n> +/*\n> + * Copyright (C) 2002 ARM Ltd.\n> + * Copyright (C) 2008 STMicroelctronics.\n> + * Copyright (C) 2009 ST-Ericsson.\n> + * Copyright 2017 Google, Inc.\n> + *\n> + * This file is based on arm realview platform\n> + *\n> + * This program is free software; you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation.\n> + */\n> +\n> +#define pr_fmt(fmt) \"PLATSMP: \" fmt\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#define NPCM7XX_SCRPAD_REG 0x13c\n> +\n> +static void __iomem *gcr_base;\n> +static void __iomem *scu_base;\n> +\n> +/* This is called from headsmp.S to wakeup the secondary core */\n> +extern void npcm7xx_secondary_startup(void);\n> +extern void npcm7xx_wakeup_z1(void);\n\nThis routine is not called, was it for an early revision of the silicon,\nor is it for CPU hotplugging maybe?\n\n> +\n> +/*\n> + * Write pen_release in a way that is guaranteed to be visible to all\n> + * observers, irrespective of whether they're taking part in coherency\n> + * or not. This is necessary for the hotplug code to work reliably.\n> + */\n> +static void npcm7xx_write_pen_release(int val)\n> +{\n> +\tpen_release = val;\n> +\t/* write to pen_release must be visible to all observers. */\n> +\tsmp_wmb();\n> +\t__cpuc_flush_dcache_area((void *) &pen_release, sizeof(pen_release));\n> +\touter_clean_range(__pa(&pen_release), __pa(&pen_release + 1));\n> +}\n> +\n> +static DEFINE_SPINLOCK(boot_lock);\n> +\n> +static void npcm7xx_smp_secondary_init(unsigned int cpu)\n> +{\n> +\t/*\n> +\t * let the primary processor know we're out of the\n> +\t * pen, then head off into the C entry point\n> +\t */\n> +\tnpcm7xx_write_pen_release(-1);\n> +\n> +\t/*\n> +\t * Synchronise with the boot thread.\n> +\t */\n> +\tspin_lock(&boot_lock);\n> +\tspin_unlock(&boot_lock);\n> +}\n> +\n> +static int npcm7xx_smp_boot_secondary(unsigned int cpu, struct task_struct *idle)\n> +{\n> +\tunsigned long timeout;\n> +\n> +\tif (!gcr_base)\n> +\t\treturn -EIO;\n> +\n> +\t/*\n> +\t * set synchronisation state between this boot processor\n> +\t * and the secondary one\n> +\t */\n> +\tspin_lock(&boot_lock);\n> +\n> +\t/*\n> +\t * The secondary processor is waiting to be released from\n> +\t * the holding pen - release it, then wait for it to flag\n> +\t * that it has been released by resetting pen_release.\n> +\t */\n> +\tnpcm7xx_write_pen_release(cpu_logical_map(cpu));\n> +\tiowrite32(virt_to_phys(npcm7xx_secondary_startup),\n> +\t\t gcr_base + NPCM7XX_SCRPAD_REG);\n\nPlease use __pa_symbol here instead of virt_to_phys() since you are\ncalling this against a kernel image symbol.\n\n> +\t/* make npcm7xx_secondary_startup visible to all observers. */\n> +\tsmp_rmb();\n> +\n> +\tarch_send_wakeup_ipi_mask(cpumask_of(cpu));\n> +\ttimeout = jiffies + (HZ * 1);\n> +\twhile (time_before(jiffies, timeout)) {\n> +\t\t/* make sure we see any writes to pen_release. */\n> +\t\tsmp_rmb();\n> +\t\tif (pen_release == -1)\n> +\t\t\tbreak;\n> +\n> +\t\tudelay(10);\n> +\t}\n> +\n> +\t/*\n> +\t * now the secondary core is starting up let it run its\n> +\t * calibrations, then wait for it to finish\n> +\t */\n> +\tspin_unlock(&boot_lock);\n> +\n> +\treturn pen_release != -1 ? -EIO : 0;\n> +}\n> +\n> +\n> +static void __init npcm7xx_wakeup_secondary(void)\n> +{\n> +\t/*\n> +\t * write the address of secondary startup into the backup ram register\n> +\t * at offset 0x1FF4, then write the magic number 0xA1FEED01f to the\n> +\t * backup ram register at offset 0x1FF0, which is what boot rom code\n> +\t * is waiting for. This would wake up the secondary core from WFE\n> +\t */\n\nThe comment does not seem to match what you are doing.\n\n> +\tiowrite32(virt_to_phys(npcm7xx_secondary_startup), gcr_base +\n> +\t\t NPCM7XX_SCRPAD_REG);\n\nSame here please use __pa_symbol().\n\n> +\t/* make sure npcm7xx_secondary_startup is seen by all observers. */\n> +\tsmp_wmb();\n> +\tdsb_sev();\n> +\n> +\t/* make sure write buffer is drained */\n> +\tmb();\n> +}\n> +\n> +static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)\n> +{\n> +\tstruct device_node *gcr_np, *scu_np;\n> +\n> +\tgcr_np = of_find_compatible_node(NULL, NULL, \"nuvoton,npcm750-gcr\");\n> +\tif (!gcr_np) {\n> +\t\tpr_err(\"no gcr device node\\n\");\n> +\t\treturn;\n> +\t}\n> +\tgcr_base = of_iomap(gcr_np, 0);\n> +\tif (!gcr_base) {\n> +\t\tpr_err(\"could not iomap gcr at: 0x%llx\\n\", gcr_base);\n> +\t\treturn;\n> +\t}\n> +\n> +\tscu_np = of_find_compatible_node(NULL, NULL, \"arm,cortex-a9-scu\");\n> +\tif (!scu_np) {\n> +\t\tpr_err(\"no scu device node\\n\");\n> +\t\treturn;\n> +\t}\n> +\tscu_base = of_iomap(scu_np, 0);\n> +\tif (!scu_base) {\n> +\t\tpr_err(\"could not iomap gcr at: 0x%llx\\n\", scu_base);\n> +\t\treturn;\n> +\t}\n> +\n> +\tscu_enable(scu_base);\n> +\tnpcm7xx_wakeup_secondary();\n> +}\n> +\n> +static struct smp_operations npcm7xx_smp_ops __initdata = {\n> +\t.smp_prepare_cpus = npcm7xx_smp_prepare_cpus,\n> +\t.smp_boot_secondary = npcm7xx_smp_boot_secondary,\n> +\t.smp_secondary_init = npcm7xx_smp_secondary_init,\n> +};\n\nOverall you have copied the realview pen hold/release mechanism and this\nis really frowned upon especially if you have a better way to control\nthe bring-up of secondary cores, e.g: via writing a special word to a\nspecific register, or setting a special address bit (e.g: bit 31 of the\nphysical address | secondary_startup) or anything that acts as a \"GO\"\nsignal of some sort.","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20170831225400.19756-2-brendanhiggins@google.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1763749,"web_url":"http://patchwork.ozlabs.org/comment/1763749/","msgid":"","list_archive_url":null,"date":"2017-09-06T00:42:46","subject":"Re: [PATCH v2 1/3] arm: npcm: add basic support for Nuvoton BMCs","submitter":{"id":69647,"url":"http://patchwork.ozlabs.org/api/people/69647/","name":"Brendan Higgins","email":"brendanhiggins@google.com"},"content":"With the exception of one comment, which I have responded to\nbelow, I have addressed your comments in my new version of\nthis patch: https://patchwork.kernel.org/patch/9914153/\n\nOn Mon, Sep 4, 2017 at 7:47 PM, Florian Fainelli wrote:\n...\n>> +\n>> +ENTRY(v7_invalidate_l1_npcmX50)\n>> + mov r0, #0\n>> + mcr p15, 0, r0, c7, c5, 0 /* invalidate I cache */\n>> + mcr p15, 2, r0, c0, c0, 0\n>> + mrc p15, 1, r0, c0, c0, 0\n>> +\n>> + ldr r1, =0x7fff\n>> + and r2, r1, r0, lsr #13\n>> +\n>> + ldr r1, =0x3ff\n>> +\n>> + and r3, r1, r0, lsr #3 /* NumWays - 1 */\n>> + add r2, r2, #1 /* NumSets */\n>> +\n>> + and r0, r0, #0x7\n>> + add r0, r0, #4 /* SetShift */\n>> +\n>> + clz r1, r3 /* WayShift */\n>> + add r4, r3, #1 /* NumWays */\n>> +1: sub r2, r2, #1 /* NumSets-- */\n>> + mov r3, r4 /* Temp = NumWays */\n>> +2: subs r3, r3, #1 /* Temp-- */\n>> + mov r5, r3, lsl r1\n>> + mov r6, r2, lsl r0\n>> + /* Reg = (Temp << WayShift) | (NumSets << SetShift) */\n>> + orr r5, r5, r6\n>> + mcr p15, 0, r5, c7, c6, 2\n>> + bgt 2b\n>> + cmp r2, #0\n>> + bgt 1b\n>> + dsb\n>> + isb\n>> + mov pc, lr\n>> +ENDPROC(v7_invalidate_l1_npcmX50)\n>\n> This looks a lot, if not nearly the same thing as v7_invalidate_l1 which\n> is already called by secondary_startup, can you see if you can re-use it\n> directly?\n>\n>> +\n>> +/*\n>> + * MSM specific entry point for secondary CPUs. This provides\n>> + * a \"holding pen\" into which all secondary cores are held until we're\n>> + * ready for them to initialise.\n>> + */\n>\n> Assuming this was copied from a Qualcomm MSM routine, you may want to\n> fix the comment, typo on \"initialis.\n>\n>> +ENTRY(npcm7xx_secondary_startup)\n>> + msr CPSR_c, #(SVC_MODE)\n>\n> Is there a BootROM or something that would not make the secondary cores\n> start in supervisor mode?\n\nUnfortunately, yes; however, I was able to cut all of the other code out of\nnpcm7xx_secondary_startup, so now it just puts the core in SVC mode and\nrelies on secondary_startup to do all of the L1 cache invalidation.\n\n>\n>> +\n>> + bl v7_invalidate_l1_npcmX50\n>> + /* disable vector table remapping */\n>> + mrc p15, 0,r0, c1, c0, 0\n>> + and r0, #0xffffdfff\n>> + mcr p15, 0,r0, c1, c0, 0\n>> +\n>> +#ifdef CONFIG_CACHE_L2X0\n>> + /* Enable L1 & L2 prefetch + Zero line */\n>> + mrc p15, 0, r0, c1, c0, 1\n>> + orr r0, r0, #(7 << 1)\n>> + mcr p15, 0, r0, c1, c0, 1\n>> +#endif /* CONFIG_CACHE_L2X0 */\n>> +\n>> + mrc p15, 0, r0, c0, c0, 5\n>> + and r0, r0, #15\n>> + adr r4, 1f\n>> + ldmia r4, {r5, r6}\n>> + sub r4, r4, r5\n>> + add r6, r6, r4\n>> + str r3,[r2]\n>> +\n>> +pen: ldr r7, [r6]\n>> + cmp r7, r0\n>> + bne pen\n>> +\n...\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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\n\tTue, 05 Sep 2017 17:42:46 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<8fd55a57-946d-f53f-e10b-c73d1f70d1dc@gmail.com>","References":"<20170831225400.19756-1-brendanhiggins@google.com>\n\t<20170831225400.19756-2-brendanhiggins@google.com>\n\t<8fd55a57-946d-f53f-e10b-c73d1f70d1dc@gmail.com>","From":"Brendan Higgins ","Date":"Tue, 5 Sep 2017 17:42:46 -0700","Message-ID":"","Subject":"Re: [PATCH v2 1/3] arm: npcm: add basic support for Nuvoton BMCs","To":"Florian Fainelli ","Cc":"Rob Herring ,\n\tMark Rutland , linux@armlinux.org.uk,\n\tavifishman70@gmail.com, tmaimon77@gmail.com,\n\tRick Altherr ,\n\tdevicetree ,\n\tLinux Kernel Mailing List ,\n\tlinux-arm-kernel@lists.infradead.org,\n\tOpenBMC Maillist ","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]