[{"id":1767936,"web_url":"http://patchwork.ozlabs.org/comment/1767936/","msgid":"<87r2vaacll.fsf@linaro.org>","list_archive_url":null,"date":"2017-09-13T14:37:42","subject":"Re: [PATCH v2 02/28] arm64: KVM: Hide unsupported AArch64 CPU\n\tfeatures from guests","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"content":"Dave Martin writes:\n\n> Currently, a guest kernel sees the true CPU feature registers\n> (ID_*_EL1) when it reads them using MRS instructions. This means\n> that the guest will observe features that are present in the\n> hardware but the host doesn't understand or doesn't provide support\n> for. A guest may legimitately try to use such a feature as per the\n> architecture, but use of the feature may trap instead of working\n> normally, triggering undef injection into the guest.\n>\n> This is not a problem for the host, but the guest may go wrong when\n> running on newer hardware than the host knows about.\n>\n> This patch hides from guest VMs any AArch64-specific CPU features\n> that the host doesn't support, by exposing to the guest the\n> sanitised versions of the registers computed by the cpufeatures\n> framework, instead of the true hardware registers. To achieve\n> this, HCR_EL2.TID3 is now set for AArch64 guests, and emulation\n> code is added to KVM to report the sanitised versions of the\n> affected registers in response to MRS and register reads from\n> userspace.\n>\n> The affected registers are removed from invariant_sys_regs[] (since\n> the invariant_sys_regs handling is no longer quite correct for\n> them) and added to sys_reg_desgs[], with appropriate access(),\n> get_user() and set_user() methods. No runtime vcpu storage is\n> allocated for the registers: instead, they are read on demand from\n> the cpufeatures framework. This may need modification in the\n> future if there is a need for userspace to customise the features\n> visible to the guest.\n>\n> Attempts by userspace to write the registers are handled similarly\n> to the current invariant_sys_regs handling: writes are permitted,\n> but only if they don't attempt to change the value. This is\n> sufficient to support VM snapshot/restore from userspace.\n>\n> Because of the additional registers, restoring a VM on an older\n> kernel may not work unless userspace knows how to handle the extra\n> VM registers exposed to the KVM user ABI by this patch.\n>\n> Under the principle of least damage, this patch makes no attempt to\n> handle any of the other registers currently in\n> invariant_sys_regs[], or to emulate registers for AArch32: however,\n> these could be handled in a similar way in future, as necessary.\n>\n> Signed-off-by: Dave Martin \n> Cc: Marc Zyngier \n>\n> ---\n>\n> Changes since v1\n> ----------------\n>\n> Requested by Marc Zyngier:\n>\n> * Get rid of ternary operator use in walk_sys_regs().\n>\n> * Call write_to_read_only() if an attempt to write an ID reg is\n> trapped, rather than reinventing.\n> Probably we won't get there anyway: the architecture says that this\n> should undef at EL1 instead.\n>\n> * Make ID register sysreg table less cryptic and spread the entries one\n> per line.\n> Also, make the architecturally unallocated and allocated but hidden\n> cases more clearly distinct. These require the same behaviour but for\n> different reasons, so it's better to identify them as separate.\n>\n> Other:\n>\n> * Delete BUG_ON()s that are skipped by construction:\n> These check that the result of sys_reg_to_index() is a 64-bit\n> register, which is always true because sys_reg_to_index()\n> explicitly sets this.\n>\n> * Remove duplicate const in __access_id_reg args [sparse]\n> ---\n> arch/arm64/include/asm/sysreg.h | 3 +\n> arch/arm64/kvm/hyp/switch.c | 6 +\n> arch/arm64/kvm/sys_regs.c | 282 +++++++++++++++++++++++++++++++++-------\n> 3 files changed, 246 insertions(+), 45 deletions(-)\n>\n> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h\n> index f707fed..480ecd6 100644\n> --- a/arch/arm64/include/asm/sysreg.h\n> +++ b/arch/arm64/include/asm/sysreg.h\n> @@ -149,6 +149,9 @@\n> #define SYS_ID_AA64DFR0_EL1\t\tsys_reg(3, 0, 0, 5, 0)\n> #define SYS_ID_AA64DFR1_EL1\t\tsys_reg(3, 0, 0, 5, 1)\n>\n> +#define SYS_ID_AA64AFR0_EL1\t\tsys_reg(3, 0, 0, 5, 4)\n> +#define SYS_ID_AA64AFR1_EL1\t\tsys_reg(3, 0, 0, 5, 5)\n> +\n> #define SYS_ID_AA64ISAR0_EL1\t\tsys_reg(3, 0, 0, 6, 0)\n> #define SYS_ID_AA64ISAR1_EL1\t\tsys_reg(3, 0, 0, 6, 1)\n>\n> diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c\n> index 945e79c..35a90b8 100644\n> --- a/arch/arm64/kvm/hyp/switch.c\n> +++ b/arch/arm64/kvm/hyp/switch.c\n> @@ -81,11 +81,17 @@ static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu)\n> \t * it will cause an exception.\n> \t */\n> \tval = vcpu->arch.hcr_el2;\n> +\n> \tif (!(val & HCR_RW) && system_supports_fpsimd()) {\n> \t\twrite_sysreg(1 << 30, fpexc32_el2);\n> \t\tisb();\n> \t}\n> +\n> +\tif (val & HCR_RW) /* for AArch64 only: */\n> +\t\tval |= HCR_TID3; /* TID3: trap feature register accesses */\n> +\n\nI wondered as this is the hyp switch can we make use of testing val &\nHCR_RW for both this and above. But it seems minimal in the generated\ncode so probably not.\n\n> \twrite_sysreg(val, hcr_el2);\n> +\n> \t/* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */\n> \twrite_sysreg(1 << 15, hstr_el2);\n> \t/*\n> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c\n> index 2e070d3..b1f7552 100644\n> --- a/arch/arm64/kvm/sys_regs.c\n> +++ b/arch/arm64/kvm/sys_regs.c\n> @@ -892,6 +892,137 @@ static bool access_cntp_cval(struct kvm_vcpu *vcpu,\n> \treturn true;\n> }\n>\n> +/* Read a sanitised cpufeature ID register by sys_reg_desc */\n> +static u64 read_id_reg(struct sys_reg_desc const *r, bool raz)\n> +{\n> +\tu32 id = sys_reg((u32)r->Op0, (u32)r->Op1,\n> +\t\t\t (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);\n> +\n> +\treturn raz ? 0 : read_sanitised_ftr_reg(id);\n> +}\n> +\n> +/* cpufeature ID register access trap handlers */\n> +\n> +static bool __access_id_reg(struct kvm_vcpu *vcpu,\n> +\t\t\t struct sys_reg_params *p,\n> +\t\t\t const struct sys_reg_desc *r,\n> +\t\t\t bool raz)\n> +{\n> +\tif (p->is_write)\n> +\t\treturn write_to_read_only(vcpu, p, r);\n> +\n> +\tp->regval = read_id_reg(r, raz);\n> +\treturn true;\n> +}\n> +\n> +static bool access_id_reg(struct kvm_vcpu *vcpu,\n> +\t\t\t struct sys_reg_params *p,\n> +\t\t\t const struct sys_reg_desc *r)\n> +{\n> +\treturn __access_id_reg(vcpu, p, r, false);\n> +}\n> +\n> +static bool access_raz_id_reg(struct kvm_vcpu *vcpu,\n> +\t\t\t struct sys_reg_params *p,\n> +\t\t\t const struct sys_reg_desc *r)\n> +{\n> +\treturn __access_id_reg(vcpu, p, r, true);\n> +}\n> +\n> +static int reg_from_user(u64 *val, const void __user *uaddr, u64 id);\n> +static int reg_to_user(void __user *uaddr, const u64 *val, u64 id);\n> +static u64 sys_reg_to_index(const struct sys_reg_desc *reg);\n> +\n> +/*\n> + * cpufeature ID register user accessors\n> + *\n> + * For now, these registers are immutable for userspace, so no values\n> + * are stored, and for set_id_reg() we don't allow the effective value\n> + * to be changed.\n> + */\n> +static int __get_id_reg(const struct sys_reg_desc *rd, void __user *uaddr,\n> +\t\t\tbool raz)\n> +{\n> +\tconst u64 id = sys_reg_to_index(rd);\n> +\tconst u64 val = read_id_reg(rd, raz);\n> +\n> +\treturn reg_to_user(uaddr, &val, id);\n> +}\n> +\n> +static int __set_id_reg(const struct sys_reg_desc *rd, void __user *uaddr,\n> +\t\t\tbool raz)\n> +{\n> +\tconst u64 id = sys_reg_to_index(rd);\n> +\tint err;\n> +\tu64 val;\n> +\n> +\terr = reg_from_user(&val, uaddr, id);\n> +\tif (err)\n> +\t\treturn err;\n> +\n> +\t/* This is what we mean by invariant: you can't change it. */\n> +\tif (val != read_id_reg(rd, raz))\n> +\t\treturn -EINVAL;\n> +\n> +\treturn 0;\n> +}\n> +\n> +static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,\n> +\t\t const struct kvm_one_reg *reg, void __user *uaddr)\n> +{\n> +\treturn __get_id_reg(rd, uaddr, false);\n> +}\n> +\n> +static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,\n> +\t\t const struct kvm_one_reg *reg, void __user *uaddr)\n> +{\n> +\treturn __set_id_reg(rd, uaddr, false);\n> +}\n> +\n> +static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,\n> +\t\t\t const struct kvm_one_reg *reg, void __user *uaddr)\n> +{\n> +\treturn __get_id_reg(rd, uaddr, true);\n> +}\n> +\n> +static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,\n> +\t\t\t const struct kvm_one_reg *reg, void __user *uaddr)\n> +{\n> +\treturn __set_id_reg(rd, uaddr, true);\n> +}\n> +\n> +/* sys_reg_desc initialiser for known cpufeature ID registers */\n> +#define ID_SANITISED(name) {\t\t\t\\\n> +\tSYS_DESC(SYS_##name),\t\t\t\\\n> +\t.access\t= access_id_reg,\t\t\\\n> +\t.get_user = get_id_reg,\t\t\t\\\n> +\t.set_user = set_id_reg,\t\t\t\\\n> +}\n> +\n> +/*\n> + * sys_reg_desc initialiser for architecturally unallocated cpufeature ID\n> + * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2\n> + * (1 <= crm < 8, 0 <= Op2 < 8).\n> + */\n> +#define ID_UNALLOCATED(crm, op2) {\t\t\t\\\n> +\tOp0(3), Op1(0), CRn(0), CRm(crm), Op2(op2),\t\\\n> +\t.access = access_raz_id_reg,\t\t\t\\\n> +\t.get_user = get_raz_id_reg,\t\t\t\\\n> +\t.set_user = set_raz_id_reg,\t\t\t\\\n> +}\n> +\n> +/*\n> + * sys_reg_desc initialiser for known ID registers that we hide from guests.\n> + * For now, these are exposed just like unallocated ID regs: they appear\n> + * RAZ for the guest.\n> + */\n> +#define ID_HIDDEN(name) {\t\t\t\\\n> +\tSYS_DESC(SYS_##name),\t\t\t\\\n> +\t.access = access_raz_id_reg,\t\t\\\n> +\t.get_user = get_raz_id_reg,\t\t\\\n> +\t.set_user = set_raz_id_reg,\t\t\\\n> +}\n> +\n> /*\n> * Architected system registers.\n> * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2\n> @@ -944,6 +1075,84 @@ static const struct sys_reg_desc sys_reg_descs[] = {\n> \t{ SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },\n>\n> \t{ SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },\n> +\n> +\t/*\n> +\t * ID regs: all ID_SANITISED() entries here must have corresponding\n> +\t * entries in arm64_ftr_regs[].\n> +\t */\n\narm64_ftr_regs isn't updated in this commit. Does this break bisection?\n\n> +\n> +\t/* AArch64 mappings of the AArch32 ID registers */\n> +\t/* CRm=1 */\n> +\tID_SANITISED(ID_PFR0_EL1),\n> +\tID_SANITISED(ID_PFR1_EL1),\n> +\tID_SANITISED(ID_DFR0_EL1),\n> +\tID_HIDDEN(ID_AFR0_EL1),\n> +\tID_SANITISED(ID_MMFR0_EL1),\n> +\tID_SANITISED(ID_MMFR1_EL1),\n> +\tID_SANITISED(ID_MMFR2_EL1),\n> +\tID_SANITISED(ID_MMFR3_EL1),\n> +\n> +\t/* CRm=2 */\n> +\tID_SANITISED(ID_ISAR0_EL1),\n> +\tID_SANITISED(ID_ISAR1_EL1),\n> +\tID_SANITISED(ID_ISAR2_EL1),\n> +\tID_SANITISED(ID_ISAR3_EL1),\n> +\tID_SANITISED(ID_ISAR4_EL1),\n> +\tID_SANITISED(ID_ISAR5_EL1),\n> +\tID_SANITISED(ID_MMFR4_EL1),\n> +\tID_UNALLOCATED(2,7),\n> +\n> +\t/* CRm=3 */\n> +\tID_SANITISED(MVFR0_EL1),\n> +\tID_SANITISED(MVFR1_EL1),\n> +\tID_SANITISED(MVFR2_EL1),\n> +\tID_UNALLOCATED(3,3),\n> +\tID_UNALLOCATED(3,4),\n> +\tID_UNALLOCATED(3,5),\n> +\tID_UNALLOCATED(3,6),\n> +\tID_UNALLOCATED(3,7),\n> +\n> +\t/* AArch64 ID registers */\n> +\t/* CRm=4 */\n> +\tID_SANITISED(ID_AA64PFR0_EL1),\n> +\tID_SANITISED(ID_AA64PFR1_EL1),\n> +\tID_UNALLOCATED(4,2),\n> +\tID_UNALLOCATED(4,3),\n> +\tID_UNALLOCATED(4,4),\n> +\tID_UNALLOCATED(4,5),\n> +\tID_UNALLOCATED(4,6),\n> +\tID_UNALLOCATED(4,7),\n> +\n> +\t/* CRm=5 */\n> +\tID_SANITISED(ID_AA64DFR0_EL1),\n> +\tID_SANITISED(ID_AA64DFR1_EL1),\n> +\tID_UNALLOCATED(5,2),\n> +\tID_UNALLOCATED(5,3),\n> +\tID_HIDDEN(ID_AA64AFR0_EL1),\n> +\tID_HIDDEN(ID_AA64AFR1_EL1),\n> +\tID_UNALLOCATED(5,6),\n> +\tID_UNALLOCATED(5,7),\n> +\n> +\t/* CRm=6 */\n> +\tID_SANITISED(ID_AA64ISAR0_EL1),\n> +\tID_SANITISED(ID_AA64ISAR1_EL1),\n> +\tID_UNALLOCATED(6,2),\n> +\tID_UNALLOCATED(6,3),\n> +\tID_UNALLOCATED(6,4),\n> +\tID_UNALLOCATED(6,5),\n> +\tID_UNALLOCATED(6,6),\n> +\tID_UNALLOCATED(6,7),\n> +\n> +\t/* CRm=7 */\n> +\tID_SANITISED(ID_AA64MMFR0_EL1),\n> +\tID_SANITISED(ID_AA64MMFR1_EL1),\n> +\tID_SANITISED(ID_AA64MMFR2_EL1),\n> +\tID_UNALLOCATED(7,3),\n> +\tID_UNALLOCATED(7,4),\n> +\tID_UNALLOCATED(7,5),\n> +\tID_UNALLOCATED(7,6),\n> +\tID_UNALLOCATED(7,7),\n> +\n\nI think it might be worthwhile adding a test to kvm-unit-tests to walk\nall the ID registers to check this.\n\n> \t{ SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },\n> \t{ SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },\n> \t{ SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },\n> @@ -1790,8 +1999,8 @@ static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,\n> \tif (!r)\n> \t\tr = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));\n>\n> -\t/* Not saved in the sys_reg array? */\n> -\tif (r && !r->reg)\n> +\t/* Not saved in the sys_reg array and not otherwise accessible? */\n> +\tif (r && !(r->reg || r->get_user))\n> \t\tr = NULL;\n>\n> \treturn r;\n> @@ -1815,20 +2024,6 @@ static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,\n> FUNCTION_INVARIANT(midr_el1)\n> FUNCTION_INVARIANT(ctr_el0)\n> FUNCTION_INVARIANT(revidr_el1)\n> -FUNCTION_INVARIANT(id_pfr0_el1)\n> -FUNCTION_INVARIANT(id_pfr1_el1)\n> -FUNCTION_INVARIANT(id_dfr0_el1)\n> -FUNCTION_INVARIANT(id_afr0_el1)\n> -FUNCTION_INVARIANT(id_mmfr0_el1)\n> -FUNCTION_INVARIANT(id_mmfr1_el1)\n> -FUNCTION_INVARIANT(id_mmfr2_el1)\n> -FUNCTION_INVARIANT(id_mmfr3_el1)\n> -FUNCTION_INVARIANT(id_isar0_el1)\n> -FUNCTION_INVARIANT(id_isar1_el1)\n> -FUNCTION_INVARIANT(id_isar2_el1)\n> -FUNCTION_INVARIANT(id_isar3_el1)\n> -FUNCTION_INVARIANT(id_isar4_el1)\n> -FUNCTION_INVARIANT(id_isar5_el1)\n> FUNCTION_INVARIANT(clidr_el1)\n> FUNCTION_INVARIANT(aidr_el1)\n>\n> @@ -1836,20 +2031,6 @@ FUNCTION_INVARIANT(aidr_el1)\n> static struct sys_reg_desc invariant_sys_regs[] = {\n> \t{ SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },\n> \t{ SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },\n> -\t{ SYS_DESC(SYS_ID_PFR0_EL1), NULL, get_id_pfr0_el1 },\n> -\t{ SYS_DESC(SYS_ID_PFR1_EL1), NULL, get_id_pfr1_el1 },\n> -\t{ SYS_DESC(SYS_ID_DFR0_EL1), NULL, get_id_dfr0_el1 },\n> -\t{ SYS_DESC(SYS_ID_AFR0_EL1), NULL, get_id_afr0_el1 },\n> -\t{ SYS_DESC(SYS_ID_MMFR0_EL1), NULL, get_id_mmfr0_el1 },\n> -\t{ SYS_DESC(SYS_ID_MMFR1_EL1), NULL, get_id_mmfr1_el1 },\n> -\t{ SYS_DESC(SYS_ID_MMFR2_EL1), NULL, get_id_mmfr2_el1 },\n> -\t{ SYS_DESC(SYS_ID_MMFR3_EL1), NULL, get_id_mmfr3_el1 },\n> -\t{ SYS_DESC(SYS_ID_ISAR0_EL1), NULL, get_id_isar0_el1 },\n> -\t{ SYS_DESC(SYS_ID_ISAR1_EL1), NULL, get_id_isar1_el1 },\n> -\t{ SYS_DESC(SYS_ID_ISAR2_EL1), NULL, get_id_isar2_el1 },\n> -\t{ SYS_DESC(SYS_ID_ISAR3_EL1), NULL, get_id_isar3_el1 },\n> -\t{ SYS_DESC(SYS_ID_ISAR4_EL1), NULL, get_id_isar4_el1 },\n> -\t{ SYS_DESC(SYS_ID_ISAR5_EL1), NULL, get_id_isar5_el1 },\n> \t{ SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },\n> \t{ SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },\n> \t{ SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },\n> @@ -2079,12 +2260,31 @@ static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)\n> \treturn true;\n> }\n>\n> +static int walk_one_sys_reg(const struct sys_reg_desc *rd,\n> +\t\t\t u64 __user **uind,\n> +\t\t\t unsigned int *total)\n> +{\n> +\t/*\n> +\t * Ignore registers we trap but don't save,\n> +\t * and for which no custom user accessor is provided.\n> +\t */\n> +\tif (!(rd->reg || rd->get_user))\n> +\t\treturn 0;\n> +\n> +\tif (!copy_reg_to_user(rd, uind))\n> +\t\treturn -EFAULT;\n> +\n> +\t(*total)++;\n> +\treturn 0;\n> +}\n> +\n> /* Assumed ordered tables, see kvm_sys_reg_table_init. */\n> static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)\n> {\n> \tconst struct sys_reg_desc *i1, *i2, *end1, *end2;\n> \tunsigned int total = 0;\n> \tsize_t num;\n> +\tint err;\n>\n> \t/* We check for duplicates here, to allow arch-specific overrides. */\n> \ti1 = get_target_table(vcpu->arch.target, true, &num);\n> @@ -2098,21 +2298,13 @@ static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)\n> \twhile (i1 || i2) {\n> \t\tint cmp = cmp_sys_reg(i1, i2);\n> \t\t/* target-specific overrides generic entry. */\n> -\t\tif (cmp <= 0) {\n> -\t\t\t/* Ignore registers we trap but don't save. */\n> -\t\t\tif (i1->reg) {\n> -\t\t\t\tif (!copy_reg_to_user(i1, &uind))\n> -\t\t\t\t\treturn -EFAULT;\n> -\t\t\t\ttotal++;\n> -\t\t\t}\n> -\t\t} else {\n> -\t\t\t/* Ignore registers we trap but don't save. */\n> -\t\t\tif (i2->reg) {\n> -\t\t\t\tif (!copy_reg_to_user(i2, &uind))\n> -\t\t\t\t\treturn -EFAULT;\n> -\t\t\t\ttotal++;\n> -\t\t\t}\n> -\t\t}\n> +\t\tif (cmp <= 0)\n> +\t\t\terr = walk_one_sys_reg(i1, &uind, &total);\n> +\t\telse\n> +\t\t\terr = walk_one_sys_reg(i2, &uind, &total);\n> +\n> +\t\tif (err)\n> +\t\t\treturn err;\n>\n> \t\tif (cmp <= 0 && ++i1 == end1)\n> \t\t\ti1 = NULL;\n\n\n--\nAlex Bennée","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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","Subject":"Re: [PATCH v2 02/28] arm64: KVM: Hide unsupported AArch64 CPU\n\tfeatures from guests","In-reply-to":"<1504198860-12951-3-git-send-email-Dave.Martin@arm.com>","Date":"Wed, 13 Sep 2017 15:37:42 +0100","Message-ID":"<87r2vaacll.fsf@linaro.org>","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170913_073807_511990_B40A2AB3 ","X-CRM114-Status":"GOOD ( 37.83 )","X-Spam-Score":"-2.7 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.7 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow\n\ttrust [2a00:1450:400c:c09:0:0:0:231 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID 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","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1768458,"web_url":"http://patchwork.ozlabs.org/comment/1768458/","msgid":"<87h8w5aakx.fsf@linaro.org>","list_archive_url":null,"date":"2017-09-14T09:33:34","subject":"Re: [PATCH v2 15/28] arm64: cpufeature: Move sys_caps_initialised\n\tdeclarations","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"content":"Dave Martin writes:\n\n> update_cpu_features() currently cannot tell whether it is being\n> called during early or late secondary boot. This doesn't\n> desperately matter for anything it currently does.\n>\n> However, SVE will need to know here whether the set of available\n> vector lengths is fixed of still to be determined when booting a\n> CPU so that it can be updated appropriately.\n>\n> This patch simply moves the sys_caps_initialised stuff to the top\n> of the file so that it can be more widely. There doesn't seem to\n> be a more obvious place to put it.\n>\n> Signed-off-by: Dave Martin \n> Cc: Suzuki K Poulose \n\nReviewed-by: Alex Bennée \n\n> ---\n> arch/arm64/kernel/cpufeature.c | 30 +++++++++++++++---------------\n> 1 file changed, 15 insertions(+), 15 deletions(-)\n>\n> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c\n> index cd52d36..43ba8df 100644\n> --- a/arch/arm64/kernel/cpufeature.c\n> +++ b/arch/arm64/kernel/cpufeature.c\n> @@ -51,6 +51,21 @@ unsigned int compat_elf_hwcap2 __read_mostly;\n> DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);\n> EXPORT_SYMBOL(cpu_hwcaps);\n>\n> +/*\n> + * Flag to indicate if we have computed the system wide\n> + * capabilities based on the boot time active CPUs. This\n> + * will be used to determine if a new booting CPU should\n> + * go through the verification process to make sure that it\n> + * supports the system capabilities, without using a hotplug\n> + * notifier.\n> + */\n> +static bool sys_caps_initialised;\n> +\n> +static inline void set_sys_caps_initialised(void)\n> +{\n> +\tsys_caps_initialised = true;\n> +}\n> +\n> static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)\n> {\n> \t/* file-wide pr_fmt adds \"CPU features: \" prefix */\n> @@ -1041,21 +1056,6 @@ void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)\n> }\n>\n> /*\n> - * Flag to indicate if we have computed the system wide\n> - * capabilities based on the boot time active CPUs. This\n> - * will be used to determine if a new booting CPU should\n> - * go through the verification process to make sure that it\n> - * supports the system capabilities, without using a hotplug\n> - * notifier.\n> - */\n> -static bool sys_caps_initialised;\n> -\n> -static inline void set_sys_caps_initialised(void)\n> -{\n> -\tsys_caps_initialised = true;\n> -}\n> -\n> -/*\n> * Check for CPU features that are used in early boot\n> * based on the Boot CPU value.\n> */\n\n\n--\nAlex Bennée","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"LHMCCaNs\"; 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emacs 25.2.50.3","From":"Alex =?utf-8?q?Benn=C3=A9e?= ","To":"Dave Martin ","Subject":"Re: [PATCH v2 15/28] arm64: cpufeature: Move sys_caps_initialised\n\tdeclarations","In-reply-to":"<1504198860-12951-16-git-send-email-Dave.Martin@arm.com>","Date":"Thu, 14 Sep 2017 10:33:34 +0100","Message-ID":"<87h8w5aakx.fsf@linaro.org>","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170914_023358_467413_C2448DB9 ","X-CRM114-Status":"GOOD ( 18.74 )","X-Spam-Score":"-2.7 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.7 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow\n\ttrust [2a00:1450:400c:c09:0:0:0:22d listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-arch@vger.kernel.org, libc-alpha@sourceware.org,\n\tArd Biesheuvel ,\n\tSzabolcs Nagy ,\n\tCatalin Marinas ,\n\tSuzuki K Poulose ,\n\tWill Deacon , \n\tRichard Sandiford ,\n\tkvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1768470,"web_url":"http://patchwork.ozlabs.org/comment/1768470/","msgid":"","list_archive_url":null,"date":"2017-09-14T09:35:28","subject":"Re: [PATCH v2 15/28] arm64: cpufeature: Move sys_caps_initialised\n\tdeclarations","submitter":{"id":65822,"url":"http://patchwork.ozlabs.org/api/people/65822/","name":"Suzuki K Poulose","email":"suzuki.poulose@arm.com"},"content":"On 31/08/17 18:00, Dave Martin wrote:\n> update_cpu_features() currently cannot tell whether it is being\n> called during early or late secondary boot. This doesn't\n> desperately matter for anything it currently does.\n>\n> However, SVE will need to know here whether the set of available\n> vector lengths is fixed of still to be determined when booting a\n> CPU so that it can be updated appropriately.\n>\n> This patch simply moves the sys_caps_initialised stuff to the top\n> of the file so that it can be more widely. There doesn't seem to\n> be a more obvious place to put it.\n>\n> Signed-off-by: Dave Martin \n> Cc: Suzuki K Poulose \n> ---\n> arch/arm64/kernel/cpufeature.c | 30 +++++++++++++++---------------\n> 1 file changed, 15 insertions(+), 15 deletions(-)\n>\n> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c\n> index cd52d36..43ba8df 100644\n> --- a/arch/arm64/kernel/cpufeature.c\n> +++ b/arch/arm64/kernel/cpufeature.c\n> @@ -51,6 +51,21 @@ unsigned int compat_elf_hwcap2 __read_mostly;\n> DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);\n> EXPORT_SYMBOL(cpu_hwcaps);\n>\n> +/*\n> + * Flag to indicate if we have computed the system wide\n> + * capabilities based on the boot time active CPUs. This\n> + * will be used to determine if a new booting CPU should\n> + * go through the verification process to make sure that it\n> + * supports the system capabilities, without using a hotplug\n> + * notifier.\n> + */\n> +static bool sys_caps_initialised;\n> +\n> +static inline void set_sys_caps_initialised(void)\n> +{\n> +\tsys_caps_initialised = true;\n> +}\n> +\n> static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)\n> {\n> \t/* file-wide pr_fmt adds \"CPU features: \" prefix */\n> @@ -1041,21 +1056,6 @@ void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)\n> }\n>\n> /*\n> - * Flag to indicate if we have computed the system wide\n> - * capabilities based on the boot time active CPUs. This\n> - * will be used to determine if a new booting CPU should\n> - * go through the verification process to make sure that it\n> - * supports the system capabilities, without using a hotplug\n> - * notifier.\n> - */\n> -static bool sys_caps_initialised;\n> -\n> -static inline void set_sys_caps_initialised(void)\n> -{\n> -\tsys_caps_initialised = true;\n> -}\n\nReviewed-by: Suzuki K Poulose ","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"SZInRUIN\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xtD5g0g0mz9s06\n\tfor ;\n\tThu, 14 Sep 2017 19:39:51 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dsQcb-0001SO-O8; Thu, 14 Sep 2017 09:39:45 +0000","from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]\n\thelo=foss.arm.com)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dsQYs-0007zX-5i for linux-arm-kernel@lists.infradead.org;\n\tThu, 14 Sep 2017 09:36:01 +0000","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F2FA81435;\n\tThu, 14 Sep 2017 02:35:32 -0700 (PDT)","from [10.1.206.28] (e107814-lin.cambridge.arm.com [10.1.206.28])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\tB99E93F3E1; Thu, 14 Sep 2017 02:35:30 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type:\n\tContent-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive:\n\tList-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From:\n\tReferences:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;\n\tbh=8TAWaPcyueQt1OSETwKgA/vJF1MdiVVsFbE0RqE2I3Y=;\n\tb=SZInRUINXzQTbB8n+jskTKAew\n\th8mqiBBhSBgDIncPbVwJy6DXFuYXxmzjB6V1m8wZUr6IhOWYKFxU23v1UGVU1M9ZZMafOcDUiwMcF\n\tgu5zY3x6HWP3hV/1ITRnQj/W+2m1xsiPcbFdI+6xkJj8DX+05ja8KRZ0syBqFJRUqgr91Rwa+xEQC\n\tNBotjttzsH+EHgYE/58tFdvqUBBRSMRfzjnUxxS63IXDoUaYtysnIe402vdKFvN4C0ypmjsMApMWY\n\tCtN9tG6K3cx8QzO3GlizYIuUHpafbtr0qsh6l6nCGDTXO8W+C7c9KZc3YfPcBIZgeywOf9+0I3jHM\n\t1YERRPG6w==;","Subject":"Re: [PATCH v2 15/28] arm64: cpufeature: Move sys_caps_initialised\n\tdeclarations","To":"Dave Martin , linux-arm-kernel@lists.infradead.org","References":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>\n\t<1504198860-12951-16-git-send-email-Dave.Martin@arm.com>","From":"Suzuki K Poulose ","Message-ID":"","Date":"Thu, 14 Sep 2017 10:35:28 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.8.0","MIME-Version":"1.0","In-Reply-To":"<1504198860-12951-16-git-send-email-Dave.Martin@arm.com>","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170914_023555_487296_830A70E6 ","X-CRM114-Status":"GOOD ( 18.64 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-arch@vger.kernel.org, libc-alpha@sourceware.org, Ard Biesheuvel\n\t, Szabolcs Nagy ,\n\tCatalin Marinas\n\t, Will Deacon , Richard\n\tSandiford , =?utf-8?q?Alex_Benn=C3=A9e?=\n\t, kvmarm@lists.cs.columbia.edu","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1768506,"web_url":"http://patchwork.ozlabs.org/comment/1768506/","msgid":"<87efr9a6xl.fsf@linaro.org>","list_archive_url":null,"date":"2017-09-14T10:52:22","subject":"Re: [PATCH v2 17/28] arm64/sve: Preserve SVE registers around\n\tkernel-mode NEON use","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"content":"Dave Martin writes:\n\n> Kernel-mode NEON will corrupt the SVE vector registers, due to the\n> way they alias the FPSIMD vector registers in the hardware.\n>\n> This patch ensures that any live SVE register content for the task\n> is saved by kernel_neon_begin(). The data will be restored in the\n> usual way on return to userspace.\n>\n> Signed-off-by: Dave Martin \n> Reviewed-by: Ard Biesheuvel \n\nReviewed-by: Alex Bennée \n\n> ---\n> arch/arm64/kernel/fpsimd.c | 6 ++++--\n> 1 file changed, 4 insertions(+), 2 deletions(-)\n>\n> diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c\n> index cea05a7..dd89acf 100644\n> --- a/arch/arm64/kernel/fpsimd.c\n> +++ b/arch/arm64/kernel/fpsimd.c\n> @@ -744,8 +744,10 @@ void kernel_neon_begin(void)\n> \t__this_cpu_write(kernel_neon_busy, true);\n>\n> \t/* Save unsaved task fpsimd state, if any: */\n> -\tif (current->mm && !test_and_set_thread_flag(TIF_FOREIGN_FPSTATE))\n> -\t\tfpsimd_save_state(¤t->thread.fpsimd_state);\n> +\tif (current->mm) {\n> +\t\ttask_fpsimd_save();\n> +\t\tset_thread_flag(TIF_FOREIGN_FPSTATE);\n> +\t}\n>\n> \t/* Invalidate any task state remaining in the fpsimd regs: */\n> \t__this_cpu_write(fpsimd_last_state, NULL);\n\n\n--\nAlex Bennée","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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emacs 25.2.50.3","From":"Alex =?utf-8?q?Benn=C3=A9e?= ","To":"Dave Martin ","Subject":"Re: [PATCH v2 17/28] arm64/sve: Preserve SVE registers around\n\tkernel-mode NEON use","In-reply-to":"<1504198860-12951-18-git-send-email-Dave.Martin@arm.com>","Date":"Thu, 14 Sep 2017 11:52:22 +0100","Message-ID":"<87efr9a6xl.fsf@linaro.org>","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170914_035246_489634_7D2109DA ","X-CRM114-Status":"GOOD ( 12.63 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2a00:1450:400c:c0c:0:0:0:230 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-arch@vger.kernel.org, libc-alpha@sourceware.org,\n\tArd Biesheuvel ,\n\tSzabolcs Nagy ,\n\tCatalin Marinas ,\n\tWill Deacon , \n\tRichard Sandiford ,\n\tkvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1768579,"web_url":"http://patchwork.ozlabs.org/comment/1768579/","msgid":"<87a81xa0w5.fsf@linaro.org>","list_archive_url":null,"date":"2017-09-14T13:02:50","subject":"Re: [PATCH v2 20/28] arm64/sve: Add prctl controls for userspace\n\tvector length management","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"content":"Dave Martin writes:\n\n> This patch adds two arm64-specific prctls, to permit userspace to\n> control its vector length:\n>\n> * PR_SVE_SET_VL: set the thread's SVE vector length and vector\n> length inheritance mode.\n>\n> * PR_SVE_GET_VL: get the same information.\n>\n> Although these calls shadow instruction set features in the SVE\n> architecture, these prctls provide additional control: the vector\n> length inheritance mode is Linux-specific and nothing to do with\n> the architecture, and the architecture does not permit EL0 to set\n> its own vector length directly. Both can be used in portable tools\n> without requiring the use of SVE instructions.\n>\n> Signed-off-by: Dave Martin \n\nReviewed-by: Alex Bennée \n\n> ---\n> arch/arm64/include/asm/fpsimd.h | 14 ++++++++++++\n> arch/arm64/include/asm/processor.h | 4 ++++\n> arch/arm64/kernel/fpsimd.c | 46 ++++++++++++++++++++++++++++++++++++++\n> include/uapi/linux/prctl.h | 4 ++++\n> kernel/sys.c | 12 ++++++++++\n> 5 files changed, 80 insertions(+)\n>\n> diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h\n> index 2723cca..d084968 100644\n> --- a/arch/arm64/include/asm/fpsimd.h\n> +++ b/arch/arm64/include/asm/fpsimd.h\n> @@ -17,6 +17,7 @@\n> #define __ASM_FP_H\n>\n> #include \n> +#include \n>\n> #ifndef __ASSEMBLY__\n>\n> @@ -99,6 +100,9 @@ extern void sve_sync_from_fpsimd_zeropad(struct task_struct *task);\n> extern int sve_set_vector_length(struct task_struct *task,\n> \t\t\t\t unsigned long vl, unsigned long flags);\n>\n> +extern int sve_set_current_vl(unsigned long arg);\n> +extern int sve_get_current_vl(void);\n> +\n> extern void __init sve_init_vq_map(void);\n> extern void sve_update_vq_map(void);\n> extern int sve_verify_vq_map(void);\n> @@ -114,6 +118,16 @@ static void __maybe_unused sve_sync_to_fpsimd(struct task_struct *task) { }\n> static void __maybe_unused sve_sync_from_fpsimd_zeropad(\n> \tstruct task_struct *task) { }\n>\n> +static int __maybe_unused sve_set_current_vl(unsigned long arg)\n> +{\n> +\treturn -EINVAL;\n> +}\n> +\n> +static int __maybe_unused sve_get_current_vl(void)\n> +{\n> +\treturn -EINVAL;\n> +}\n> +\n> static void __maybe_unused sve_init_vq_map(void) { }\n> static void __maybe_unused sve_update_vq_map(void) { }\n> static int __maybe_unused sve_verify_vq_map(void) { return 0; }\n> diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h\n> index 3faceac..df66452 100644\n> --- a/arch/arm64/include/asm/processor.h\n> +++ b/arch/arm64/include/asm/processor.h\n> @@ -197,4 +197,8 @@ static inline void spin_lock_prefetch(const void *ptr)\n> int cpu_enable_pan(void *__unused);\n> int cpu_enable_cache_maint_trap(void *__unused);\n>\n> +/* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */\n> +#define SVE_SET_VL(arg)\tsve_set_current_vl(arg)\n> +#define SVE_GET_VL()\tsve_get_current_vl()\n> +\n> #endif /* __ASM_PROCESSOR_H */\n> diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c\n> index 361c019..42e8331 100644\n> --- a/arch/arm64/kernel/fpsimd.c\n> +++ b/arch/arm64/kernel/fpsimd.c\n> @@ -27,6 +27,7 @@\n> #include \n> #include \n> #include \n> +#include \n> #include \n> #include \n> #include \n> @@ -420,6 +421,51 @@ int sve_set_vector_length(struct task_struct *task,\n> \treturn 0;\n> }\n>\n> +/*\n> + * Encode the current vector length and flags for return.\n> + * This is only required for prctl(): ptrace has separate fields\n> + */\n> +static int sve_prctl_status(void)\n> +{\n> +\tint ret = current->thread.sve_vl;\n> +\n> +\tif (test_thread_flag(TIF_SVE_VL_INHERIT))\n> +\t\tret |= PR_SVE_VL_INHERIT;\n> +\n> +\treturn ret;\n> +}\n> +\n> +/* PR_SVE_SET_VL */\n> +int sve_set_current_vl(unsigned long arg)\n> +{\n> +\tunsigned long vl, flags;\n> +\tint ret;\n> +\n> +\tvl = arg & PR_SVE_VL_LEN_MASK;\n> +\tflags = arg & ~vl;\n> +\n> +\tif (!system_supports_sve())\n> +\t\treturn -EINVAL;\n> +\n> +\tpreempt_disable();\n> +\tret = sve_set_vector_length(current, vl, flags);\n> +\tpreempt_enable();\n> +\n> +\tif (ret)\n> +\t\treturn ret;\n> +\n> +\treturn sve_prctl_status();\n> +}\n> +\n> +/* PR_SVE_GET_VL */\n> +int sve_get_current_vl(void)\n> +{\n> +\tif (!system_supports_sve())\n> +\t\treturn -EINVAL;\n> +\n> +\treturn sve_prctl_status();\n> +}\n> +\n> static unsigned long *sve_alloc_vq_map(void)\n> {\n> \treturn kzalloc(BITS_TO_LONGS(SVE_VQ_MAX) * sizeof(unsigned long),\n> diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h\n> index 1b64901..1ef9370 100644\n> --- a/include/uapi/linux/prctl.h\n> +++ b/include/uapi/linux/prctl.h\n> @@ -198,7 +198,11 @@ struct prctl_mm_map {\n> # define PR_CAP_AMBIENT_CLEAR_ALL\t4\n>\n> /* arm64 Scalable Vector Extension controls */\n> +/* Flag values must be kept in sync with ptrace NT_ARM_SVE interface */\n> +#define PR_SVE_SET_VL\t\t\t48\t/* set task vector length */\n> # define PR_SVE_SET_VL_ONEXEC\t\t(1 << 18) /* defer effect until exec */\n> +#define PR_SVE_GET_VL\t\t\t49\t/* get task vector length */\n> +/* Bits common to PR_SVE_SET_VL and PR_SVE_GET_VL */\n> # define PR_SVE_VL_LEN_MASK\t\t0xffff\n> # define PR_SVE_VL_INHERIT\t\t(1 << 17) /* inherit across exec */\n>\n> diff --git a/kernel/sys.c b/kernel/sys.c\n> index 2855ee7..f8215a6 100644\n> --- a/kernel/sys.c\n> +++ b/kernel/sys.c\n> @@ -110,6 +110,12 @@\n> #ifndef SET_FP_MODE\n> # define SET_FP_MODE(a,b)\t(-EINVAL)\n> #endif\n> +#ifndef SVE_SET_VL\n> +# define SVE_SET_VL(a)\t\t(-EINVAL)\n> +#endif\n> +#ifndef SVE_GET_VL\n> +# define SVE_GET_VL()\t\t(-EINVAL)\n> +#endif\n>\n> /*\n> * this is where the system-wide overflow UID and GID are defined, for\n> @@ -2389,6 +2395,12 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3,\n> \tcase PR_GET_FP_MODE:\n> \t\terror = GET_FP_MODE(me);\n> \t\tbreak;\n> +\tcase PR_SVE_SET_VL:\n> +\t\terror = SVE_SET_VL(arg2);\n> +\t\tbreak;\n> +\tcase PR_SVE_GET_VL:\n> +\t\terror = SVE_GET_VL();\n> +\t\tbreak;\n> \tdefault:\n> \t\terror = -EINVAL;\n> \t\tbreak;\n\n\n--\nAlex Bennée","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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emacs 25.2.50.3","From":"Alex =?utf-8?q?Benn=C3=A9e?= ","To":"Dave Martin ","Subject":"Re: [PATCH v2 20/28] arm64/sve: Add prctl controls for userspace\n\tvector length management","In-reply-to":"<1504198860-12951-21-git-send-email-Dave.Martin@arm.com>","Date":"Thu, 14 Sep 2017 14:02:50 +0100","Message-ID":"<87a81xa0w5.fsf@linaro.org>","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170914_140313_893974_56F9DDE2 ","X-CRM114-Status":"GOOD ( 24.38 )","X-Spam-Score":"-2.7 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on casper.infradead.org summary:\n\tContent analysis details: (-2.7 points, 5.0 required)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow\n\ttrust [2a00:1450:400c:c09:0:0:0:231 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-arch@vger.kernel.org, libc-alpha@sourceware.org,\n\tArd Biesheuvel ,\n\tSzabolcs Nagy ,\n\tCatalin Marinas ,\n\tWill Deacon , \n\tRichard Sandiford ,\n\tAndrew Morton , kvmarm@lists.cs.columbia.edu, \n\tlinux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1768586,"web_url":"http://patchwork.ozlabs.org/comment/1768586/","msgid":"<877ex19zpf.fsf@linaro.org>","list_archive_url":null,"date":"2017-09-14T13:28:28","subject":"Re: [PATCH v2 22/28] arm64/sve: KVM: Prevent guests from using SVE","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"content":"Dave Martin writes:\n\n> Until KVM has full SVE support, guests must not be allowed to\n> execute SVE instructions.\n>\n> This patch enables the necessary traps, and also ensures that the\n> traps are disabled again on exit from the guest so that the host\n> can still use SVE if it wants to.\n>\n> This patch introduces another instance of\n> __this_cpu_write(fpsimd_last_state, NULL), so this flush operation\n> is abstracted out as a separate helper fpsimd_flush_cpu_state().\n> Other instances are ported appropriately.\n>\n> As a side effect of this refactoring, a this_cpu_write() in\n> fpsimd_cpu_pm_notifier() is changed to __this_cpu_write(). This\n> should be fine, since cpu_pm_enter() is supposed to be called only\n> with interrupts disabled.\n>\n> Signed-off-by: Dave Martin \n> Cc: Marc Zyngier \n> Cc: Ard Biesheuvel \n\nReviewed-by: Alex Bennée \n\n>\n> ---\n>\n> Changes since v1\n> ----------------\n>\n> Requested by Marc Zyngier:\n>\n> * Avoid the verbose arithmetic for CPTR_EL2_DEFAULT, and just\n> describe it in terms of the set of bits known to be RES1 in\n> CPTR_EL2.\n>\n> Other:\n>\n> * Fixup to drop task SVE state cached in the CPU registers across\n> guest entry/exit.\n>\n> Without this, we may enter an EL0 process with wrong data in the\n> extended SVE bits and/or wrong trap configuration.\n>\n> This is not a problem for the FPSIMD part of the state because KVM\n> explicitly restores the host FPSIMD state on guest exit; but this\n> restore is sufficient to corrupt the extra SVE bits even if nothing\n> else does.\n>\n> * The fpsimd_flush_cpu_state() function, which was supposed to abstract\n> the underlying flush operation, wasn't used. [sparse]\n>\n> This patch is now ported to use it. Other users of the same idiom are\n> ported too (which was the original intention).\n>\n> fpsimd_flush_cpu_state() is marked inline, since all users are\n> ifdef'd and the function may be unused. Plus, it's trivially\n> suitable for inlining.\n> ---\n> arch/arm/include/asm/kvm_host.h | 3 +++\n> arch/arm64/include/asm/fpsimd.h | 1 +\n> arch/arm64/include/asm/kvm_arm.h | 4 +++-\n> arch/arm64/include/asm/kvm_host.h | 11 +++++++++++\n> arch/arm64/kernel/fpsimd.c | 31 +++++++++++++++++++++++++++++--\n> arch/arm64/kvm/hyp/switch.c | 6 +++---\n> virt/kvm/arm/arm.c | 3 +++\n> 7 files changed, 53 insertions(+), 6 deletions(-)\n>\n> diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h\n> index 127e2dd..fa4a442 100644\n> --- a/arch/arm/include/asm/kvm_host.h\n> +++ b/arch/arm/include/asm/kvm_host.h\n> @@ -299,4 +299,7 @@ int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,\n> int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,\n> \t\t\t struct kvm_device_attr *attr);\n>\n> +/* All host FP/SIMD state is restored on guest exit, so nothing to save: */\n> +static inline void kvm_fpsimd_flush_cpu_state(void) {}\n> +\n> #endif /* __ARM_KVM_HOST_H__ */\n> diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h\n> index d084968..5605fc1 100644\n> --- a/arch/arm64/include/asm/fpsimd.h\n> +++ b/arch/arm64/include/asm/fpsimd.h\n> @@ -74,6 +74,7 @@ extern void fpsimd_restore_current_state(void);\n> extern void fpsimd_update_current_state(struct fpsimd_state *state);\n>\n> extern void fpsimd_flush_task_state(struct task_struct *target);\n> +extern void sve_flush_cpu_state(void);\n>\n> /* Maximum VL that SVE VL-agnostic software can transparently support */\n> #define SVE_VL_ARCH_MAX 0x100\n> diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h\n> index dbf0537..7f069ff 100644\n> --- a/arch/arm64/include/asm/kvm_arm.h\n> +++ b/arch/arm64/include/asm/kvm_arm.h\n> @@ -186,7 +186,8 @@\n> #define CPTR_EL2_TTA\t(1 << 20)\n> #define CPTR_EL2_TFP\t(1 << CPTR_EL2_TFP_SHIFT)\n> #define CPTR_EL2_TZ\t(1 << 8)\n> -#define CPTR_EL2_DEFAULT\t0x000033ff\n> +#define CPTR_EL2_RES1\t0x000032ff /* known RES1 bits in CPTR_EL2 */\n> +#define CPTR_EL2_DEFAULT\tCPTR_EL2_RES1\n>\n> /* Hyp Debug Configuration Register bits */\n> #define MDCR_EL2_TPMS\t\t(1 << 14)\n> @@ -237,5 +238,6 @@\n>\n> #define CPACR_EL1_FPEN\t\t(3 << 20)\n> #define CPACR_EL1_TTA\t\t(1 << 28)\n> +#define CPACR_EL1_DEFAULT\t(CPACR_EL1_FPEN | CPACR_EL1_ZEN_EL1EN)\n>\n> #endif /* __ARM64_KVM_ARM_H__ */\n> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h\n> index d686300..05d8373 100644\n> --- a/arch/arm64/include/asm/kvm_host.h\n> +++ b/arch/arm64/include/asm/kvm_host.h\n> @@ -25,6 +25,7 @@\n> #include \n> #include \n> #include \n> +#include \n> #include \n> #include \n> #include \n> @@ -390,4 +391,14 @@ static inline void __cpu_init_stage2(void)\n> \t\t \"PARange is %d bits, unsupported configuration!\", parange);\n> }\n>\n> +/*\n> + * All host FP/SIMD state is restored on guest exit, so nothing needs\n> + * doing here except in the SVE case:\n> +*/\n> +static inline void kvm_fpsimd_flush_cpu_state(void)\n> +{\n> +\tif (system_supports_sve())\n> +\t\tsve_flush_cpu_state();\n> +}\n> +\n> #endif /* __ARM64_KVM_HOST_H__ */\n> diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c\n> index b430ee0..7837ced 100644\n> --- a/arch/arm64/kernel/fpsimd.c\n> +++ b/arch/arm64/kernel/fpsimd.c\n> @@ -875,6 +875,33 @@ void fpsimd_flush_task_state(struct task_struct *t)\n> \tt->thread.fpsimd_state.cpu = NR_CPUS;\n> }\n>\n> +static inline void fpsimd_flush_cpu_state(void)\n> +{\n> +\t__this_cpu_write(fpsimd_last_state, NULL);\n> +}\n> +\n> +/*\n> + * Invalidate any task SVE state currently held in this CPU's regs.\n> + *\n> + * This is used to prevent the kernel from trying to reuse SVE register data\n> + * that is detroyed by KVM guest enter/exit. This function should go away when\n> + * KVM SVE support is implemented. Don't use it for anything else.\n> + */\n> +#ifdef CONFIG_ARM64_SVE\n> +void sve_flush_cpu_state(void)\n> +{\n> +\tstruct fpsimd_state *const fpstate = __this_cpu_read(fpsimd_last_state);\n> +\tstruct task_struct *tsk;\n> +\n> +\tif (!fpstate)\n> +\t\treturn;\n> +\n> +\ttsk = container_of(fpstate, struct task_struct, thread.fpsimd_state);\n> +\tif (test_tsk_thread_flag(tsk, TIF_SVE))\n> +\t\tfpsimd_flush_cpu_state();\n> +}\n> +#endif /* CONFIG_ARM64_SVE */\n> +\n> #ifdef CONFIG_KERNEL_MODE_NEON\n>\n> DEFINE_PER_CPU(bool, kernel_neon_busy);\n> @@ -915,7 +942,7 @@ void kernel_neon_begin(void)\n> \t}\n>\n> \t/* Invalidate any task state remaining in the fpsimd regs: */\n> -\t__this_cpu_write(fpsimd_last_state, NULL);\n> +\tfpsimd_flush_cpu_state();\n>\n> \tpreempt_disable();\n>\n> @@ -1032,7 +1059,7 @@ static int fpsimd_cpu_pm_notifier(struct notifier_block *self,\n> \tcase CPU_PM_ENTER:\n> \t\tif (current->mm)\n> \t\t\ttask_fpsimd_save();\n> -\t\tthis_cpu_write(fpsimd_last_state, NULL);\n> +\t\tfpsimd_flush_cpu_state();\n> \t\tbreak;\n> \tcase CPU_PM_EXIT:\n> \t\tif (current->mm)\n> diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c\n> index 35a90b8..951f3eb 100644\n> --- a/arch/arm64/kvm/hyp/switch.c\n> +++ b/arch/arm64/kvm/hyp/switch.c\n> @@ -48,7 +48,7 @@ static void __hyp_text __activate_traps_vhe(void)\n>\n> \tval = read_sysreg(cpacr_el1);\n> \tval |= CPACR_EL1_TTA;\n> -\tval &= ~CPACR_EL1_FPEN;\n> +\tval &= ~(CPACR_EL1_FPEN | CPACR_EL1_ZEN);\n> \twrite_sysreg(val, cpacr_el1);\n>\n> \twrite_sysreg(__kvm_hyp_vector, vbar_el1);\n> @@ -59,7 +59,7 @@ static void __hyp_text __activate_traps_nvhe(void)\n> \tu64 val;\n>\n> \tval = CPTR_EL2_DEFAULT;\n> -\tval |= CPTR_EL2_TTA | CPTR_EL2_TFP;\n> +\tval |= CPTR_EL2_TTA | CPTR_EL2_TFP | CPTR_EL2_TZ;\n> \twrite_sysreg(val, cptr_el2);\n> }\n>\n> @@ -117,7 +117,7 @@ static void __hyp_text __deactivate_traps_vhe(void)\n>\n> \twrite_sysreg(mdcr_el2, mdcr_el2);\n> \twrite_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);\n> -\twrite_sysreg(CPACR_EL1_FPEN, cpacr_el1);\n> +\twrite_sysreg(CPACR_EL1_DEFAULT, cpacr_el1);\n> \twrite_sysreg(vectors, vbar_el1);\n> }\n>\n> diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c\n> index a39a1e1..af9f5da 100644\n> --- a/virt/kvm/arm/arm.c\n> +++ b/virt/kvm/arm/arm.c\n> @@ -647,6 +647,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)\n> \t\t */\n> \t\tpreempt_disable();\n>\n> +\t\t/* Flush FP/SIMD state that can't survive guest entry/exit */\n> +\t\tkvm_fpsimd_flush_cpu_state();\n> +\n> \t\tkvm_pmu_flush_hwstate(vcpu);\n>\n> \t\tkvm_timer_flush_hwstate(vcpu);\n\n\n--\nAlex Bennée","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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emacs 25.2.50.3","From":"Alex =?utf-8?q?Benn=C3=A9e?= ","To":"Dave Martin ","Subject":"Re: [PATCH v2 22/28] arm64/sve: KVM: Prevent guests from using SVE","In-reply-to":"<1504198860-12951-23-git-send-email-Dave.Martin@arm.com>","Date":"Thu, 14 Sep 2017 14:28:28 +0100","Message-ID":"<877ex19zpf.fsf@linaro.org>","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170914_062852_172749_12E5D759 ","X-CRM114-Status":"GOOD ( 28.94 )","X-Spam-Score":"-2.7 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.7 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow\n\ttrust [2a00:1450:400c:c09:0:0:0:22a listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-arch@vger.kernel.org, libc-alpha@sourceware.org,\n\tArd Biesheuvel ,\n\tSzabolcs Nagy ,\n\tCatalin Marinas ,\n\tWill Deacon , Marc Zyngier ,\n\tChristoffer Dall ,\n\tRichard Sandiford ,\n\tkvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1768588,"web_url":"http://patchwork.ozlabs.org/comment/1768588/","msgid":"<8760cl9zms.fsf@linaro.org>","list_archive_url":null,"date":"2017-09-14T13:30:03","subject":"Re: [PATCH v2 23/28] arm64/sve: KVM: Treat guest SVE use as\n\tundefined instruction execution","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"content":"Dave Martin writes:\n\n> When trapping forbidden attempts by a guest to use SVE, we want the\n> guest to see a trap consistent with SVE not being implemented.\n>\n> This patch injects an undefined instruction exception into the\n> guest in response to such an exception.\n>\n> Signed-off-by: Dave Martin \n\nReviewed-by: Alex Bennée \n\n> ---\n> arch/arm64/kvm/handle_exit.c | 8 ++++++++\n> 1 file changed, 8 insertions(+)\n>\n> diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c\n> index 17d8a16..e3e42d0 100644\n> --- a/arch/arm64/kvm/handle_exit.c\n> +++ b/arch/arm64/kvm/handle_exit.c\n> @@ -147,6 +147,13 @@ static int kvm_handle_unknown_ec(struct kvm_vcpu *vcpu, struct kvm_run *run)\n> \treturn 1;\n> }\n>\n> +static int handle_sve(struct kvm_vcpu *vcpu, struct kvm_run *run)\n> +{\n> +\t/* Until SVE is supported for guests: */\n> +\tkvm_inject_undefined(vcpu);\n> +\treturn 1;\n> +}\n> +\n> static exit_handle_fn arm_exit_handlers[] = {\n> \t[0 ... ESR_ELx_EC_MAX]\t= kvm_handle_unknown_ec,\n> \t[ESR_ELx_EC_WFx]\t= kvm_handle_wfx,\n> @@ -160,6 +167,7 @@ static exit_handle_fn arm_exit_handlers[] = {\n> \t[ESR_ELx_EC_HVC64]\t= handle_hvc,\n> \t[ESR_ELx_EC_SMC64]\t= handle_smc,\n> \t[ESR_ELx_EC_SYS64]\t= kvm_handle_sys_reg,\n> +\t[ESR_ELx_EC_SVE]\t= handle_sve,\n> \t[ESR_ELx_EC_IABT_LOW]\t= kvm_handle_guest_abort,\n> \t[ESR_ELx_EC_DABT_LOW]\t= kvm_handle_guest_abort,\n> \t[ESR_ELx_EC_SOFTSTP_LOW]= kvm_handle_guest_debug,\n\n\n--\nAlex Bennée","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"jaQ2PBIN\"; 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emacs 25.2.50.3","From":"Alex =?utf-8?q?Benn=C3=A9e?= ","To":"Dave Martin ","Subject":"Re: [PATCH v2 23/28] arm64/sve: KVM: Treat guest SVE use as\n\tundefined instruction execution","In-reply-to":"<1504198860-12951-24-git-send-email-Dave.Martin@arm.com>","Date":"Thu, 14 Sep 2017 14:30:03 +0100","Message-ID":"<8760cl9zms.fsf@linaro.org>","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170914_063026_993310_F5E109BA ","X-CRM114-Status":"GOOD ( 12.74 )","X-Spam-Score":"-2.7 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.7 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow\n\ttrust [2a00:1450:400c:c09:0:0:0:232 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-arch@vger.kernel.org, libc-alpha@sourceware.org,\n\tArd Biesheuvel ,\n\tSzabolcs Nagy ,\n\tCatalin Marinas ,\n\tWill Deacon , Marc Zyngier ,\n\tChristoffer Dall ,\n\tRichard Sandiford ,\n\tkvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1768591,"web_url":"http://patchwork.ozlabs.org/comment/1768591/","msgid":"<874ls59zku.fsf@linaro.org>","list_archive_url":null,"date":"2017-09-14T13:31:13","subject":"Re: [PATCH v2 23/28] arm64/sve: KVM: Treat guest SVE use as\n\tundefined instruction execution","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"content":"Dave Martin writes:\n\n> When trapping forbidden attempts by a guest to use SVE, we want the\n> guest to see a trap consistent with SVE not being implemented.\n>\n> This patch injects an undefined instruction exception into the\n> guest in response to such an exception.\n\nI do wonder if this should be merged with the previous trap enabling\npatch though?\n\n>\n> Signed-off-by: Dave Martin \n> ---\n> arch/arm64/kvm/handle_exit.c | 8 ++++++++\n> 1 file changed, 8 insertions(+)\n>\n> diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c\n> index 17d8a16..e3e42d0 100644\n> --- a/arch/arm64/kvm/handle_exit.c\n> +++ b/arch/arm64/kvm/handle_exit.c\n> @@ -147,6 +147,13 @@ static int kvm_handle_unknown_ec(struct kvm_vcpu *vcpu, struct kvm_run *run)\n> \treturn 1;\n> }\n>\n> +static int handle_sve(struct kvm_vcpu *vcpu, struct kvm_run *run)\n> +{\n> +\t/* Until SVE is supported for guests: */\n> +\tkvm_inject_undefined(vcpu);\n> +\treturn 1;\n> +}\n> +\n> static exit_handle_fn arm_exit_handlers[] = {\n> \t[0 ... ESR_ELx_EC_MAX]\t= kvm_handle_unknown_ec,\n> \t[ESR_ELx_EC_WFx]\t= kvm_handle_wfx,\n> @@ -160,6 +167,7 @@ static exit_handle_fn arm_exit_handlers[] = {\n> \t[ESR_ELx_EC_HVC64]\t= handle_hvc,\n> \t[ESR_ELx_EC_SMC64]\t= handle_smc,\n> \t[ESR_ELx_EC_SYS64]\t= kvm_handle_sys_reg,\n> +\t[ESR_ELx_EC_SVE]\t= handle_sve,\n> \t[ESR_ELx_EC_IABT_LOW]\t= kvm_handle_guest_abort,\n> \t[ESR_ELx_EC_DABT_LOW]\t= kvm_handle_guest_abort,\n> \t[ESR_ELx_EC_SOFTSTP_LOW]= kvm_handle_guest_debug,\n\n\n--\nAlex Bennée","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"oT2RpLwA\"; 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emacs 25.2.50.3","From":"Alex =?utf-8?q?Benn=C3=A9e?= ","To":"Dave Martin ","Subject":"Re: [PATCH v2 23/28] arm64/sve: KVM: Treat guest SVE use as\n\tundefined instruction execution","In-reply-to":"<1504198860-12951-24-git-send-email-Dave.Martin@arm.com>","Date":"Thu, 14 Sep 2017 14:31:13 +0100","Message-ID":"<874ls59zku.fsf@linaro.org>","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170914_063137_108318_C64CBEAB ","X-CRM114-Status":"GOOD ( 13.18 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2a00:1450:400c:c0c:0:0:0:22c listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-arch@vger.kernel.org, libc-alpha@sourceware.org,\n\tArd Biesheuvel ,\n\tSzabolcs Nagy ,\n\tCatalin Marinas ,\n\tWill Deacon , Marc Zyngier ,\n\tChristoffer Dall ,\n\tRichard Sandiford ,\n\tkvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1768594,"web_url":"http://patchwork.ozlabs.org/comment/1768594/","msgid":"<87377p9zja.fsf@linaro.org>","list_archive_url":null,"date":"2017-09-14T13:32:09","subject":"Re: [PATCH v2 24/28] arm64/sve: KVM: Hide SVE from CPU features\n\texposed to guests","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"content":"Dave Martin writes:\n\n> KVM guests cannot currently use SVE, because SVE is always\n> configured to trap to EL2.\n>\n> However, a guest that sees SVE reported as present in\n> ID_AA64PFR0_EL1 may legitimately expect that SVE works and try to\n> use it. Instead of working, the guest will receive an injected\n> undef exception, which may cause the guest to oops or go into a\n> spin.\n>\n> To avoid misleading the guest into believing that SVE will work,\n> this patch masks out the SVE field from ID_AA64PFR0_EL1 when a\n> guest attempts to read this register. No support is explicitly\n> added for ID_AA64ZFR0_EL1 either, so that is still emulated as\n> reading as zero, which is consistent with SVE not being\n> implemented.\n>\n> This is a temporary measure, and will be removed in a later series\n> when full KVM support for SVE is implemented.\n>\n> Signed-off-by: Dave Martin \n> Cc: Marc Zyngier \n\nReviewed-by: Alex Bennée \n\n>\n> ---\n>\n> Changes since v1\n> ----------------\n>\n> Requested by Marc Zyngier:\n>\n> * Use pr_err() instead inventing \"kvm_info_once\" ad-hoc.\n> ---\n> arch/arm64/kvm/sys_regs.c | 12 +++++++++++-\n> 1 file changed, 11 insertions(+), 1 deletion(-)\n>\n> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c\n> index b1f7552..a0ee9b0 100644\n> --- a/arch/arm64/kvm/sys_regs.c\n> +++ b/arch/arm64/kvm/sys_regs.c\n> @@ -23,6 +23,7 @@\n> #include \n> #include \n> #include \n> +#include \n> #include \n>\n> #include \n> @@ -897,8 +898,17 @@ static u64 read_id_reg(struct sys_reg_desc const *r, bool raz)\n> {\n> \tu32 id = sys_reg((u32)r->Op0, (u32)r->Op1,\n> \t\t\t (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);\n> +\tu64 val = raz ? 0 : read_sanitised_ftr_reg(id);\n>\n> -\treturn raz ? 0 : read_sanitised_ftr_reg(id);\n> +\tif (id == SYS_ID_AA64PFR0_EL1) {\n> +\t\tif (val & (0xfUL << ID_AA64PFR0_SVE_SHIFT))\n> +\t\t\tpr_err_once(\"kvm [%i]: SVE unsupported for guests, suppressing\\n\",\n> +\t\t\t\t task_pid_nr(current));\n> +\n> +\t\tval &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);\n> +\t}\n> +\n> +\treturn val;\n> }\n>\n> /* cpufeature ID register access trap handlers */\n\n\n--\nAlex Bennée","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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emacs 25.2.50.3","From":"Alex =?utf-8?q?Benn=C3=A9e?= ","To":"Dave Martin ","Subject":"Re: [PATCH v2 24/28] arm64/sve: KVM: Hide SVE from CPU features\n\texposed to guests","In-reply-to":"<1504198860-12951-25-git-send-email-Dave.Martin@arm.com>","Date":"Thu, 14 Sep 2017 14:32:09 +0100","Message-ID":"<87377p9zja.fsf@linaro.org>","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170914_063233_226588_46C56087 ","X-CRM114-Status":"GOOD ( 19.24 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2a00:1450:400c:c0c:0:0:0:235 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-arch@vger.kernel.org, libc-alpha@sourceware.org,\n\tArd Biesheuvel ,\n\tSzabolcs Nagy ,\n\tCatalin Marinas ,\n\tWill Deacon , Marc Zyngier ,\n\tChristoffer Dall ,\n\tRichard Sandiford ,\n\tkvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1768877,"web_url":"http://patchwork.ozlabs.org/comment/1768877/","msgid":"<20170915000424.GD24231@e103592.cambridge.arm.com>","list_archive_url":null,"date":"2017-09-15T00:04:24","subject":"Re: [PATCH v2 02/28] arm64: KVM: Hide unsupported AArch64 CPU\n\tfeatures from guests","submitter":{"id":26612,"url":"http://patchwork.ozlabs.org/api/people/26612/","name":"Dave Martin","email":"Dave.Martin@arm.com"},"content":"On Wed, Sep 13, 2017 at 03:37:42PM +0100, Alex Bennée wrote:\n> \n> Dave Martin writes:\n\n[...]\n\n> > diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c\n> > index 945e79c..35a90b8 100644\n> > --- a/arch/arm64/kvm/hyp/switch.c\n> > +++ b/arch/arm64/kvm/hyp/switch.c\n> > @@ -81,11 +81,17 @@ static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu)\n> > \t * it will cause an exception.\n> > \t */\n> > \tval = vcpu->arch.hcr_el2;\n> > +\n> > \tif (!(val & HCR_RW) && system_supports_fpsimd()) {\n> > \t\twrite_sysreg(1 << 30, fpexc32_el2);\n> > \t\tisb();\n> > \t}\n> > +\n> > +\tif (val & HCR_RW) /* for AArch64 only: */\n> > +\t\tval |= HCR_TID3; /* TID3: trap feature register accesses */\n> > +\n> \n> I wondered as this is the hyp switch can we make use of testing val &\n> HCR_RW for both this and above. But it seems minimal in the generated\n> code so probably not.\n\nI figured that the code was cleaner ths way, since they're independent\nbits of code that both happen to be applicable only to AArch64 guests.\n\n[...]\n\n> > +\n> > +\t/*\n> > +\t * ID regs: all ID_SANITISED() entries here must have corresponding\n> > +\t * entries in arm64_ftr_regs[].\n> > +\t */\n> \n> arm64_ftr_regs isn't updated in this commit. Does this break bisection?\n\nThis commit only adds ID_SANITISED() entries for regs that are already\npresent in arm64_ftr_regs[]. (If you spot any that are missing, give me\na shout...)\n\nSVE only adds one new ID register, ID_AA64ZFR0_EL1 -- but SVE defines no\nfields in there yet, so I just leave it ID_UNALLOCATED() which will\ncause it to read as zero for the guest.\n\n> > +\n> > +\t/* AArch64 mappings of the AArch32 ID registers */\n> > +\t/* CRm=1 */\n> > +\tID_SANITISED(ID_PFR0_EL1),\n> > +\tID_SANITISED(ID_PFR1_EL1),\n\n[...]\n\n> > +\t/* CRm=7 */\n> > +\tID_SANITISED(ID_AA64MMFR0_EL1),\n> > +\tID_SANITISED(ID_AA64MMFR1_EL1),\n> > +\tID_SANITISED(ID_AA64MMFR2_EL1),\n> > +\tID_UNALLOCATED(7,3),\n> > +\tID_UNALLOCATED(7,4),\n> > +\tID_UNALLOCATED(7,5),\n> > +\tID_UNALLOCATED(7,6),\n> > +\tID_UNALLOCATED(7,7),\n> > +\n> \n> I think it might be worthwhile adding a test to kvm-unit-tests to walk\n> all the ID registers to check this.\n\nSounds sensible, I'll take a look at that.\n\n[...]\n\nCheers\n---Dave","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"PBsGxW5j\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xtbHx2XXjz9s72\n\tfor ;\n\tFri, 15 Sep 2017 10:04:59 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dse7q-0003Lr-MU; Fri, 15 Sep 2017 00:04:54 +0000","from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]\n\thelo=foss.arm.com)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dse7n-0003I5-Ek for linux-arm-kernel@lists.infradead.org;\n\tFri, 15 Sep 2017 00:04:52 +0000","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2ACF91435;\n\tThu, 14 Sep 2017 17:04:29 -0700 (PDT)","from e103592.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com\n\t[10.72.51.249])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\t0FE703F483; Thu, 14 Sep 2017 17:04:26 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=hlf03oMYs15WwZfkK8lSs3/k6+AdDLdLmzAbuPCOZrY=;\n\tb=PBsGxW5j3k7Ipf\n\t91yVbp8tRi9nwVS/BQqbbG7k5q8DFeq6yihPvPQAf9iximCHnffklWx7LrzDaZNzX4bz7PElFhOjG\n\t9e6xsTJDd+JSD7lVwJdcGylyaptFpTm5QVruqrLsQEJ8j37DqbiMCHrsowEm/g2Pv6zIK2nJByl/C\n\tnH/aNeDyp/4wEgPzpE7Qb15Z0muhN1SPvDSf/JPZ4/ZkTtGRIHgo2uRTyK475HdhwME+HVzX3f2ho\n\t+1YM02ID+ozu4VzUBdP8BtZs8gqp8BCCIZnYjX3TPcS+UI22zaU1SQxyzSR/AYMAKFeuXEGpQosmh\n\tRdWdB/I7JvWasevSKgYA==;","Date":"Fri, 15 Sep 2017 01:04:24 +0100","From":"Dave Martin ","To":"Alex =?iso-8859-1?q?Benn=E9e?= ","Subject":"Re: [PATCH v2 02/28] arm64: KVM: Hide unsupported AArch64 CPU\n\tfeatures from guests","Message-ID":"<20170915000424.GD24231@e103592.cambridge.arm.com>","References":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>\n\t<1504198860-12951-3-git-send-email-Dave.Martin@arm.com>\n\t<87r2vaacll.fsf@linaro.org>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<87r2vaacll.fsf@linaro.org>","User-Agent":"Mutt/1.5.23 (2014-03-12)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170914_170451_514575_E010762C ","X-CRM114-Status":"GOOD ( 17.51 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-arch@vger.kernel.org, libc-alpha@sourceware.org,\n\tArd Biesheuvel ,\n\tSzabolcs Nagy ,\n\tCatalin Marinas ,\n\tWill Deacon , Marc Zyngier ,\n\tlinux-arm-kernel@lists.infradead.org, \n\tRichard Sandiford ,\n\tkvmarm@lists.cs.columbia.edu, \n\tChristoffer Dall ","Content-Type":"text/plain; charset=\"iso-8859-1\"","Content-Transfer-Encoding":"quoted-printable","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1777529,"web_url":"http://patchwork.ozlabs.org/comment/1777529/","msgid":"<20170929130029.GG3611@e103592.cambridge.arm.com>","list_archive_url":null,"date":"2017-09-29T13:00:30","subject":"Re: [PATCH v2 23/28] arm64/sve: KVM: Treat guest SVE use as\n\tundefined instruction execution","submitter":{"id":26612,"url":"http://patchwork.ozlabs.org/api/people/26612/","name":"Dave Martin","email":"Dave.Martin@arm.com"},"content":"On Thu, Sep 14, 2017 at 02:31:13PM +0100, Alex Bennée wrote:\n> \n> Dave Martin writes:\n> \n> > When trapping forbidden attempts by a guest to use SVE, we want the\n> > guest to see a trap consistent with SVE not being implemented.\n> >\n> > This patch injects an undefined instruction exception into the\n> > guest in response to such an exception.\n> \n> I do wonder if this should be merged with the previous trap enabling\n> patch though?\n\nYes, that would make sense now I look at it.\n\nCan I keep your Reviewed-by on the combined patch?\n\nCheers\n---Dave\n\n> \n> >\n> > Signed-off-by: Dave Martin \n> > ---\n> > arch/arm64/kvm/handle_exit.c | 8 ++++++++\n> > 1 file changed, 8 insertions(+)\n> >\n> > diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c\n> > index 17d8a16..e3e42d0 100644\n> > --- a/arch/arm64/kvm/handle_exit.c\n> > +++ b/arch/arm64/kvm/handle_exit.c\n> > @@ -147,6 +147,13 @@ static int kvm_handle_unknown_ec(struct kvm_vcpu *vcpu, struct kvm_run *run)\n> > \treturn 1;\n> > }\n> >\n> > +static int handle_sve(struct kvm_vcpu *vcpu, struct kvm_run *run)\n> > +{\n> > +\t/* Until SVE is supported for guests: */\n> > +\tkvm_inject_undefined(vcpu);\n> > +\treturn 1;\n> > +}\n> > +\n> > static exit_handle_fn arm_exit_handlers[] = {\n> > \t[0 ... ESR_ELx_EC_MAX]\t= kvm_handle_unknown_ec,\n> > \t[ESR_ELx_EC_WFx]\t= kvm_handle_wfx,\n> > @@ -160,6 +167,7 @@ static exit_handle_fn arm_exit_handlers[] = {\n> > \t[ESR_ELx_EC_HVC64]\t= handle_hvc,\n> > \t[ESR_ELx_EC_SMC64]\t= handle_smc,\n> > \t[ESR_ELx_EC_SYS64]\t= kvm_handle_sys_reg,\n> > +\t[ESR_ELx_EC_SVE]\t= handle_sve,\n> > \t[ESR_ELx_EC_IABT_LOW]\t= kvm_handle_guest_abort,\n> > \t[ESR_ELx_EC_DABT_LOW]\t= kvm_handle_guest_abort,\n> > \t[ESR_ELx_EC_SOFTSTP_LOW]= kvm_handle_guest_debug,\n> \n> \n> --\n> Alex Bennée\n> \n> _______________________________________________\n> linux-arm-kernel mailing list\n> linux-arm-kernel@lists.infradead.org\n> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; 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Fri, 29 Sep 2017 06:00:32 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=gywmgVnJoKFFDt6oI6JNpTm8ZO66gKVynV2p/fBO+ag=;\n\tb=HabjpIz84AAIkw\n\tRry71XGl3oZyB/7v+yyKkk8HoFATL7VtTryi6Ae6KXKn8Bt2VaJ4LD+A/oS6Njlp6DLaMUReWdiJe\n\tqXnkDftuFOCh9KOcV87jrYmT5SqoJmkyGMpVrWPsrGrNxqJng7EmyuOXPum0Bi+hrpbQjCDA5Bi/6\n\tnX2UxYtDPuAK21ODL3IMhTpSZCSCjGC0z60Fc5pPSeRRzf50Yxle7jiSBJb4PNrFZGpH8k4vU18Yn\n\tmEEASSYKhnw6/Zxy7392fo14kqekmcTq0oIeikt6JsCS6l25D8et7rBhudCwcRDHDMwg4ZMGORidw\n\t1kfzzrnJj2AmhlfF9XLQ==;","Date":"Fri, 29 Sep 2017 14:00:30 +0100","From":"Dave Martin ","To":"Alex =?iso-8859-1?q?Benn=E9e?= ","Subject":"Re: [PATCH v2 23/28] arm64/sve: KVM: Treat guest SVE use as\n\tundefined instruction execution","Message-ID":"<20170929130029.GG3611@e103592.cambridge.arm.com>","References":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>\n\t<1504198860-12951-24-git-send-email-Dave.Martin@arm.com>\n\t<874ls59zku.fsf@linaro.org>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<874ls59zku.fsf@linaro.org>","User-Agent":"Mutt/1.5.23 (2014-03-12)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170929_060055_209310_30BE15A8 ","X-CRM114-Status":"GOOD ( 16.68 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-arch@vger.kernel.org, libc-alpha@sourceware.org,\n\tArd Biesheuvel ,\n\tSzabolcs Nagy ,\n\tCatalin Marinas ,\n\tWill Deacon , Marc Zyngier ,\n\tlinux-arm-kernel@lists.infradead.org, \n\tRichard Sandiford ,\n\tkvmarm@lists.cs.columbia.edu, \n\tChristoffer Dall ","Content-Type":"text/plain; charset=\"iso-8859-1\"","Content-Transfer-Encoding":"quoted-printable","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1777583,"web_url":"http://patchwork.ozlabs.org/comment/1777583/","msgid":"<87bmltd0pv.fsf@linaro.org>","list_archive_url":null,"date":"2017-09-29T14:43:40","subject":"Re: [PATCH v2 23/28] arm64/sve: KVM: Treat guest SVE use as\n\tundefined instruction execution","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"content":"Dave Martin writes:\n\n> On Thu, Sep 14, 2017 at 02:31:13PM +0100, Alex Bennée wrote:\n>>\n>> Dave Martin writes:\n>>\n>> > When trapping forbidden attempts by a guest to use SVE, we want the\n>> > guest to see a trap consistent with SVE not being implemented.\n>> >\n>> > This patch injects an undefined instruction exception into the\n>> > guest in response to such an exception.\n>>\n>> I do wonder if this should be merged with the previous trap enabling\n>> patch though?\n>\n> Yes, that would make sense now I look at it.\n>\n> Can I keep your Reviewed-by on the combined patch?\n\nSure.\n\n>\n> Cheers\n> ---Dave\n>\n>>\n>> >\n>> > Signed-off-by: Dave Martin \n>> > ---\n>> > arch/arm64/kvm/handle_exit.c | 8 ++++++++\n>> > 1 file changed, 8 insertions(+)\n>> >\n>> > diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c\n>> > index 17d8a16..e3e42d0 100644\n>> > --- a/arch/arm64/kvm/handle_exit.c\n>> > +++ b/arch/arm64/kvm/handle_exit.c\n>> > @@ -147,6 +147,13 @@ static int kvm_handle_unknown_ec(struct kvm_vcpu *vcpu, struct kvm_run *run)\n>> > \treturn 1;\n>> > }\n>> >\n>> > +static int handle_sve(struct kvm_vcpu *vcpu, struct kvm_run *run)\n>> > +{\n>> > +\t/* Until SVE is supported for guests: */\n>> > +\tkvm_inject_undefined(vcpu);\n>> > +\treturn 1;\n>> > +}\n>> > +\n>> > static exit_handle_fn arm_exit_handlers[] = {\n>> > \t[0 ... ESR_ELx_EC_MAX]\t= kvm_handle_unknown_ec,\n>> > \t[ESR_ELx_EC_WFx]\t= kvm_handle_wfx,\n>> > @@ -160,6 +167,7 @@ static exit_handle_fn arm_exit_handlers[] = {\n>> > \t[ESR_ELx_EC_HVC64]\t= handle_hvc,\n>> > \t[ESR_ELx_EC_SMC64]\t= handle_smc,\n>> > \t[ESR_ELx_EC_SYS64]\t= kvm_handle_sys_reg,\n>> > +\t[ESR_ELx_EC_SVE]\t= handle_sve,\n>> > \t[ESR_ELx_EC_IABT_LOW]\t= kvm_handle_guest_abort,\n>> > \t[ESR_ELx_EC_DABT_LOW]\t= kvm_handle_guest_abort,\n>> > \t[ESR_ELx_EC_SOFTSTP_LOW]= kvm_handle_guest_debug,\n>>\n>>\n>> --\n>> Alex Bennée\n>>\n>> _______________________________________________\n>> linux-arm-kernel mailing list\n>> linux-arm-kernel@lists.infradead.org\n>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel\n\n\n--\nAlex Bennée","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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