[{"id":1763316,"web_url":"http://patchwork.ozlabs.org/comment/1763316/","msgid":"<039adc54-00f5-bf4e-e509-ffdc67baa15e@arm.com>","list_archive_url":null,"date":"2017-09-05T12:53:17","subject":"Re: [RFC PATCH 4/6] iommu/arm-smmu-v3: Add SVM support for platform\n\tdevices","submitter":{"id":68357,"url":"http://patchwork.ozlabs.org/api/people/68357/","name":"Jean-Philippe Brucker","email":"Jean-Philippe.Brucker@arm.com"},"content":"On 31/08/17 09:20, Yisheng Xie wrote:\n> From: Jean-Philippe Brucker \n> \n> Platform device can realise SVM function by using the stall mode. That\n> is to say, when device access a memory via iova which is not populated,\n> it will stalled and when SMMU try to translate this iova, it also will\n> stall and meanwhile send an event to CPU via MSI.\n> \n> After SMMU driver handle the event and populated the iova, it will send\n> a RESUME command to SMMU to exit the stall mode, therefore the platform\n> device can contiue access the memory.\n> \n> Signed-off-by: Jean-Philippe Brucker \n\nNo. Please don't forge a signed-off-by under a commit message you wrote,\nit's rude. I didn't sign it, didn't consider it fit for mainline or even\nas an RFC, and wanted to have another read before sending. My mistake,\nI'll think twice before sharing prototypes in the future.\n\nThanks,\nJean\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xmmlr6ylyz9sRV\n\tfor ;\n\tTue, 5 Sep 2017 22:50:32 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751119AbdIEMuQ (ORCPT\n\t);\n\tTue, 5 Sep 2017 08:50:16 -0400","from foss.arm.com ([217.140.101.70]:40226 \"EHLO foss.arm.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751758AbdIEMuA (ORCPT );\n\tTue, 5 Sep 2017 08:50:00 -0400","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6BC402B;\n\tTue, 5 Sep 2017 05:50:00 -0700 (PDT)","from [10.1.211.72] (e106794-lin.cambridge.arm.com [10.1.211.72])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\tD49613F3E1; Tue, 5 Sep 2017 05:49:56 -0700 (PDT)"],"Subject":"Re: [RFC PATCH 4/6] iommu/arm-smmu-v3: Add SVM support for platform\n\tdevices","To":"Yisheng Xie ","Cc":"joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com,\n\tlorenzo.pieralisi@arm.com, hanjun.guo@linaro.org,\n\tsudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org,\n\twill.deacon@arm.com, robin.murphy@arm.com, robert.moore@intel.com,\n\tlv.zheng@intel.com, iommu@lists.linux-foundation.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tdevel@acpica.org, liubo95@huawei.com, chenjiankang1@huawei.com,\n\txieyisheng@huawei.com","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>\n\t<1504167642-14922-5-git-send-email-xieyisheng1@huawei.com>","From":"Jean-Philippe Brucker ","Message-ID":"<039adc54-00f5-bf4e-e509-ffdc67baa15e@arm.com>","Date":"Tue, 5 Sep 2017 13:53:17 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<1504167642-14922-5-git-send-email-xieyisheng1@huawei.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1763317,"web_url":"http://patchwork.ozlabs.org/comment/1763317/","msgid":"<923f307b-17f4-db04-9586-f27a949ce943@arm.com>","list_archive_url":null,"date":"2017-09-05T12:52:56","subject":"Re: [RFC PATCH 2/6] iommu/of: Add stall and pasid properties to\n\tiommu_fwspec","submitter":{"id":68357,"url":"http://patchwork.ozlabs.org/api/people/68357/","name":"Jean-Philippe Brucker","email":"Jean-Philippe.Brucker@arm.com"},"content":"On 31/08/17 09:20, Yisheng Xie wrote:\n> From: Jean-Philippe Brucker \n> \n> Add stall and pasid properties to iommu_fwspec.\n> \n> Signed-off-by: Jean-Philippe Brucker \n\nNo. This is a draft, I didn't sign it off.\n\nThanks,\nJean\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xmmly3l2vz9sRm\n\tfor ;\n\tTue, 5 Sep 2017 22:50:38 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751110AbdIEMto (ORCPT\n\t);\n\tTue, 5 Sep 2017 08:49:44 -0400","from foss.arm.com ([217.140.101.70]:40200 \"EHLO foss.arm.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751674AbdIEMtk (ORCPT );\n\tTue, 5 Sep 2017 08:49:40 -0400","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 87D952B;\n\tTue, 5 Sep 2017 05:49:39 -0700 (PDT)","from [10.1.211.72] (e106794-lin.cambridge.arm.com [10.1.211.72])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\tDD4243F3E1; Tue, 5 Sep 2017 05:49:35 -0700 (PDT)"],"Subject":"Re: [RFC PATCH 2/6] iommu/of: Add stall and pasid properties to\n\tiommu_fwspec","To":"Yisheng Xie ","Cc":"joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com,\n\tlorenzo.pieralisi@arm.com, hanjun.guo@linaro.org,\n\tsudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org,\n\twill.deacon@arm.com, robin.murphy@arm.com, robert.moore@intel.com,\n\tlv.zheng@intel.com, iommu@lists.linux-foundation.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tdevel@acpica.org, liubo95@huawei.com, chenjiankang1@huawei.com,\n\txieyisheng@huawei.com","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>\n\t<1504167642-14922-3-git-send-email-xieyisheng1@huawei.com>","From":"Jean-Philippe Brucker ","Message-ID":"<923f307b-17f4-db04-9586-f27a949ce943@arm.com>","Date":"Tue, 5 Sep 2017 13:52:56 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<1504167642-14922-3-git-send-email-xieyisheng1@huawei.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1763318,"web_url":"http://patchwork.ozlabs.org/comment/1763318/","msgid":"<50b249e6-8224-26fe-364f-c63b78601c6f@arm.com>","list_archive_url":null,"date":"2017-09-05T12:53:53","subject":"Re: [RFC PATCH 5/6] iommu/arm-smmu-v3: fix panic when handle stall\n\tmode irq","submitter":{"id":68357,"url":"http://patchwork.ozlabs.org/api/people/68357/","name":"Jean-Philippe Brucker","email":"Jean-Philippe.Brucker@arm.com"},"content":"On 31/08/17 09:20, Yisheng Xie wrote:\n> When SMMU do not support SVM feature, however the master support SVM,\n> which means matser can stall and with mult-pasid number, then the user\n> can bind a task to device using API like iommu_bind_task(). however,\n> when device trigger a stall mode fault i will cause panic:\n> \n> [ 106.996087] Unable to handle kernel NULL pointer dereference at virtual address 00000100\n> [ 106.996122] user pgtable: 4k pages, 48-bit VAs, pgd = ffff80003e023000\n> [ 106.996150] [0000000000000100] *pgd=000000003e04a003, *pud=000000003e04b003, *pmd=0000000000000000\n> [ 106.996201] Internal error: Oops: 96000006 [#1] PREEMPT SM\n> [ 106.996224] Modules linked in:\n> [ 106.996256] CPU: 0 PID: 916 Comm: irq/14-arm-smmu Not tainted 4.13.0-rc5-00035-g1235ddd-dirty #67\n> [ 106.996288] Hardware name: Hisilicon PhosphorHi1383 ESL (DT)\n> [ 106.996317] task: ffff80003adc1c00 task.stack: ffff80003a9f8000\n> [ 106.996347] PC is at __queue_work+0x30/0x3a8\n> [ 106.996374] LR is at queue_work_on+0x60/0x78\n> [ 106.996401] pc : [] lr : [] pstate: 40c001c9\n> [ 106.996430] sp : ffff80003a9fbc20\n> [ 106.996451] x29: ffff80003a9fbc20 x28: ffff80003adc1c00\n> [ 106.996488] x27: ffff000008d05080 x26: ffff80003ab0e028\n> [ 106.996526] x25: ffff80003a9900ac x24: 0000000000000001\n> [ 106.996562] x23: 0000000000000040 x22: 0000000000000000\n> [ 106.996598] x21: 0000000000000000 x20: 0000000000000140\n> [ 106.996634] x19: ffff80003ab0e028 x18: 0000000000000010\n> [ 106.996670] x17: 0000ffffa52a5040 x16: ffff00000820f260\n> [ 106.996708] x15: 00000018e97629e0 x14: ffff80003fb89468\n> [ 106.996744] x13: 0000000000000000 x12: ffff80003abb0600\n> [ 106.996781] x11: 0000000000000000 x10: 0000010100000100\n> [ 106.996817] x9 : 0000ffff85de5010 x8 : 00000000e4830001\n> [ 106.996854] x7 : ffff80003a9fbcf8 x6 : 0000000fffffffe0\n> [ 106.996890] x5 : 0000000000000000 x4 : 0000000000000001\n> [ 106.996926] x3 : 0000000000000000 x2 : ffff80003ab0e028\n> [ 106.996962] x1 : 0000000000000000 x0 : 00000000000001c0\n> [ 106.997002] Process irq/14-arm-smmu (pid: 916, stack limit =0xffff80003a9f8000)\n> [ 106.997035] Stack: (0xffff80003a9fbc20 to 0xffff80003a9fc000)\n> [...]\n> [ 106.998366] Call trace:\n> [ 106.998842] [] __queue_work+0x30/0x3a8\n> [ 106.998874] [] queue_work_on+0x60/0x78\n> [ 106.998912] [] arm_smmu_handle_stall+0x104/0x138\n> [ 106.998952] [] arm_smmu_evtq_thread+0xc0/0x158\n> [ 106.998989] [] irq_thread_fn+0x28/0x68\n> [ 106.999025] [] irq_thread+0x128/0x1d0\n> [ 106.999060] [] kthread+0xfc/0x128\n> [ 106.999093] [] ret_from_fork+0x10/0x50\n> [ 106.999130] Code: a90153f3 a90573fb d53b4220 363814c0 (b94102a0)\n> [ 106.999159] ---[ end trace 7e5c9f0cb1f2fecd ]---\n> \n> And the resean is we donot init fault_queue while the fault handle need\n> to use it. \n>\n> Fix by return -EINVAL in arm_smmu_bind_task() when smmu do not\n> support the feature of SVM.\n> \n> Signed-off-by: Yisheng Xie \n> ---\n> drivers/iommu/arm-smmu-v3.c | 2 ++\n> 1 file changed, 2 insertions(+)\n> \n> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c\n> index d44256a..dbda2eb 100644\n> --- a/drivers/iommu/arm-smmu-v3.c\n> +++ b/drivers/iommu/arm-smmu-v3.c\n> @@ -2922,6 +2922,8 @@ static int arm_smmu_bind_task(struct device *dev, struct task_struct *task,\n> \t\treturn -EINVAL;\n> \n> \tsmmu = master->smmu;\n> +\tif (!(smmu->features & ARM_SMMU_FEAT_SVM))\n> +\t\treturn -EINVAL;\n\nFEAT_SVM is set when the SMMU supports the same page table format as the\nMMU, it doesn't say anything about PRI/stall ability. To fix the above\nsplat we should either instantiate fault_queue even when !FEAT_SVM, or\navoid enabling master->can_fault and can_stall if !FEAT_SVM. I prefer the\nlatter.\n\nThanks,\nJean\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xmmmH4cQsz9sRV\n\tfor ;\n\tTue, 5 Sep 2017 22:50:55 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751808AbdIEMuk (ORCPT\n\t);\n\tTue, 5 Sep 2017 08:50:40 -0400","from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:40264 \"EHLO\n\tfoss.arm.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751002AbdIEMug (ORCPT );\n\tTue, 5 Sep 2017 08:50:36 -0400","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 571B82B;\n\tTue, 5 Sep 2017 05:50:36 -0700 (PDT)","from [10.1.211.72] (e106794-lin.cambridge.arm.com [10.1.211.72])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\tCC3C93F3E1; Tue, 5 Sep 2017 05:50:32 -0700 (PDT)"],"Subject":"Re: [RFC PATCH 5/6] iommu/arm-smmu-v3: fix panic when handle stall\n\tmode irq","To":"Yisheng Xie ","Cc":"joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com,\n\tlorenzo.pieralisi@arm.com, hanjun.guo@linaro.org,\n\tsudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org,\n\twill.deacon@arm.com, robin.murphy@arm.com, robert.moore@intel.com,\n\tlv.zheng@intel.com, iommu@lists.linux-foundation.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tdevel@acpica.org, liubo95@huawei.com, chenjiankang1@huawei.com,\n\txieyisheng@huawei.com","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>\n\t<1504167642-14922-6-git-send-email-xieyisheng1@huawei.com>","From":"Jean-Philippe Brucker ","Message-ID":"<50b249e6-8224-26fe-364f-c63b78601c6f@arm.com>","Date":"Tue, 5 Sep 2017 13:53:53 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<1504167642-14922-6-git-send-email-xieyisheng1@huawei.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1763319,"web_url":"http://patchwork.ozlabs.org/comment/1763319/","msgid":"<738977bb-4cd7-7d86-0ea0-0c88b6af721c@arm.com>","list_archive_url":null,"date":"2017-09-05T12:54:19","subject":"Re: [RFC PATCH 6/6] iommu/arm-smmu-v3: Avoid ILLEGAL setting of\n\tSTE.S1STALLD and CD.S","submitter":{"id":68357,"url":"http://patchwork.ozlabs.org/api/people/68357/","name":"Jean-Philippe Brucker","email":"Jean-Philippe.Brucker@arm.com"},"content":"On 31/08/17 09:20, Yisheng Xie wrote:\n> It is ILLEGAL to set STE.S1STALLD if STALL_MODEL is not 0b00, which\n> means we should not disable stall mode if stall/terminate mode is not\n> configuable.\n> \n> Meanwhile, it is also ILLEGAL when STALL_MODEL==0b10 && CD.S==0 which\n> means if stall mode is force we should always set CD.S.\n> \n> This patch add ARM_SMMU_FEAT_TERMINATE feature bit for smmu, and use\n> TERMINATE feature checking to ensue above ILLEGAL cases from happening.\n> \n> Signed-off-by: Yisheng Xie \n> ---\n> drivers/iommu/arm-smmu-v3.c | 22 ++++++++++++++++------\n> 1 file changed, 16 insertions(+), 6 deletions(-)\n> \n> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c\n> index dbda2eb..0745522 100644\n> --- a/drivers/iommu/arm-smmu-v3.c\n> +++ b/drivers/iommu/arm-smmu-v3.c\n> @@ -55,6 +55,7 @@\n> #define IDR0_STALL_MODEL_SHIFT\t\t24\n> #define IDR0_STALL_MODEL_MASK\t\t0x3\n> #define IDR0_STALL_MODEL_STALL\t\t(0 << IDR0_STALL_MODEL_SHIFT)\n> +#define IDR0_STALL_MODEL_NS\t\t(1 << IDR0_STALL_MODEL_SHIFT)\n> #define IDR0_STALL_MODEL_FORCE\t\t(2 << IDR0_STALL_MODEL_SHIFT)\n> #define IDR0_TTENDIAN_SHIFT\t\t21\n> #define IDR0_TTENDIAN_MASK\t\t0x3\n> @@ -766,6 +767,7 @@ struct arm_smmu_device {\n> #define ARM_SMMU_FEAT_SVM\t\t(1 << 15)\n> #define ARM_SMMU_FEAT_HA\t\t(1 << 16)\n> #define ARM_SMMU_FEAT_HD\t\t(1 << 17)\n> +#define ARM_SMMU_FEAT_TERMINATE\t\t(1 << 18)\n\nI'd rather introduce something like \"ARM_SMMU_FEAT_STALL_FORCE\" instead.\nTerminate model has another meaning, and is defined by a different bit in\nIDR0.\n\nThanks,\nJean\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xmmmV277Gz9sRV\n\tfor ;\n\tTue, 5 Sep 2017 22:51:06 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751638AbdIEMvE (ORCPT\n\t);\n\tTue, 5 Sep 2017 08:51:04 -0400","from foss.arm.com ([217.140.101.70]:40312 \"EHLO foss.arm.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751276AbdIEMvC (ORCPT );\n\tTue, 5 Sep 2017 08:51:02 -0400","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6D79B2B;\n\tTue, 5 Sep 2017 05:51:02 -0700 (PDT)","from [10.1.211.72] (e106794-lin.cambridge.arm.com [10.1.211.72])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\tE22E03F3E1; Tue, 5 Sep 2017 05:50:58 -0700 (PDT)"],"Subject":"Re: [RFC PATCH 6/6] iommu/arm-smmu-v3: Avoid ILLEGAL setting of\n\tSTE.S1STALLD and CD.S","To":"Yisheng Xie ","Cc":"joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com,\n\tlorenzo.pieralisi@arm.com, hanjun.guo@linaro.org,\n\tsudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org,\n\twill.deacon@arm.com, robin.murphy@arm.com, robert.moore@intel.com,\n\tlv.zheng@intel.com, iommu@lists.linux-foundation.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tdevel@acpica.org, liubo95@huawei.com, chenjiankang1@huawei.com,\n\txieyisheng@huawei.com","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>\n\t<1504167642-14922-7-git-send-email-xieyisheng1@huawei.com>","From":"Jean-Philippe Brucker ","Message-ID":"<738977bb-4cd7-7d86-0ea0-0c88b6af721c@arm.com>","Date":"Tue, 5 Sep 2017 13:54:19 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<1504167642-14922-7-git-send-email-xieyisheng1@huawei.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1763324,"web_url":"http://patchwork.ozlabs.org/comment/1763324/","msgid":"<95d1a9e2-1816-ff7d-9a8d-98406a6c2c22@arm.com>","list_archive_url":null,"date":"2017-09-05T12:56:00","subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","submitter":{"id":68357,"url":"http://patchwork.ozlabs.org/api/people/68357/","name":"Jean-Philippe Brucker","email":"Jean-Philippe.Brucker@arm.com"},"content":"On 31/08/17 09:20, Yisheng Xie wrote:\n> Jean-Philippe has post a patchset for Adding PCIe SVM support to ARM SMMUv3:\n> https://www.spinics.net/lists/arm-kernel/msg565155.html\n> \n> But for some platform devices(aka on-chip integrated devices), there is also\n> SVM requirement, which works based on the SMMU stall mode.\n> Jean-Philippe has prepared a prototype patchset to support it:\n> git://linux-arm.org/linux-jpb.git svm/stall\n\nOnly meant for testing at that point, and unfit even for an RFC.\n\n> We tested this patchset with some fixes on a on-chip integrated device. The\n> basic function is ok, so I just send them out for review, although this\n> patchset heavily depends on the former patchset (PCIe SVM support for ARM\n> SMMUv3), which is still under discussion.\n> \n> Patch Overview:\n> *1 to 3 prepare for device tree or acpi get the device stall ability and pasid bits\n> *4 is to realise the SVM function for platform device\n> *5 is fix a bug when test SVM function while SMMU donnot support this feature\n> *6 avoid ILLEGAL setting of STE and CD entry about stall\n> \n> Acctually here, I also have a question about SVM on SMMUv3:\n> \n> 1. Why the SVM feature on SMMUv3 depends on BTM feature? when bind a task to device,\n> it will register a mmu_notify. Therefore, when a page range is invalid, we can\n> send TLBI or ATC invalid without BTM?\n\nWe could, but the end goal for SVM is to perfectly mirror the CPU page\ntables. So for platform SVM we would like to get rid of MMU notifiers\nentirely.\n\n> 2. According to ACPI IORT spec, named component specific data has a node flags field\n> whoes bit0 is for Stall support. However, it do not have any field for pasid bit.\n> Can we use other 5 bits[5:1] for pasid bit numbers, so we can have 32 pasid bit for\n> a single platform device which should be enough, because SMMU only support 20 bit pasid\n> \n> 3. Presently, the pasid is allocate for a task but not for a context, if a task is trying\n> to bind to 2 device A and B:\n> a) A support 5 pasid bits\n> b) B support 2 pasid bits\n> c) when the task bind to device A, it allocate pasid = 16\n> d) then it must be fail when trying to bind to task B, for its highest pasid is 4.\n> So it should allocate a single pasid for a context to avoid this?\n\nIdeally yes, but the model chosen for the IOMMU API was one PASID per\ntask, so I implemented this model (the PASID allocator will be common to\nIOMMU core in the future).\n\nTherefore the PASID allocation will fail in your example, and there is no\nway around it. If you do (d) then (c), the task will have PASID 4.\n\nThanks,\nJean\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xmmpP4g5mz9sRm\n\tfor ;\n\tTue, 5 Sep 2017 22:52:45 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751458AbdIEMwo (ORCPT\n\t);\n\tTue, 5 Sep 2017 08:52:44 -0400","from foss.arm.com ([217.140.101.70]:40402 \"EHLO foss.arm.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751002AbdIEMwn (ORCPT );\n\tTue, 5 Sep 2017 08:52:43 -0400","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D993A2B;\n\tTue, 5 Sep 2017 05:52:42 -0700 (PDT)","from [10.1.211.72] (e106794-lin.cambridge.arm.com [10.1.211.72])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\t65B1B3F3E1; Tue, 5 Sep 2017 05:52:39 -0700 (PDT)"],"Subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","To":"Yisheng Xie ","Cc":"joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com,\n\tlorenzo.pieralisi@arm.com, hanjun.guo@linaro.org,\n\tsudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org,\n\twill.deacon@arm.com, robin.murphy@arm.com, robert.moore@intel.com,\n\tlv.zheng@intel.com, iommu@lists.linux-foundation.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tdevel@acpica.org, liubo95@huawei.com, chenjiankang1@huawei.com,\n\txieyisheng@huawei.com","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>","From":"Jean-Philippe Brucker ","Message-ID":"<95d1a9e2-1816-ff7d-9a8d-98406a6c2c22@arm.com>","Date":"Tue, 5 Sep 2017 13:56:00 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1763752,"web_url":"http://patchwork.ozlabs.org/comment/1763752/","msgid":"<3f4e17fa-dcd0-5692-099a-73105e0e0095@huawei.com>","list_archive_url":null,"date":"2017-09-06T00:51:05","subject":"Re: [RFC PATCH 4/6] iommu/arm-smmu-v3: Add SVM support for platform\n\tdevices","submitter":{"id":72301,"url":"http://patchwork.ozlabs.org/api/people/72301/","name":"Bob Liu","email":"liubo95@huawei.com"},"content":"On 2017/9/5 20:53, Jean-Philippe Brucker wrote:\n> On 31/08/17 09:20, Yisheng Xie wrote:\n>> From: Jean-Philippe Brucker \n>>\n>> Platform device can realise SVM function by using the stall mode. That\n>> is to say, when device access a memory via iova which is not populated,\n>> it will stalled and when SMMU try to translate this iova, it also will\n>> stall and meanwhile send an event to CPU via MSI.\n>>\n>> After SMMU driver handle the event and populated the iova, it will send\n>> a RESUME command to SMMU to exit the stall mode, therefore the platform\n>> device can contiue access the memory.\n>>\n>> Signed-off-by: Jean-Philippe Brucker \n> \n> No. Please don't forge a signed-off-by under a commit message you wrote,\n\nReally sorry for that.\nWe sent out the wrong version, I should take more careful review.\n\nRegards,\nLiubo\n\n> it's rude. I didn't sign it, didn't consider it fit for mainline or even\n> as an RFC, and wanted to have another read before sending. My mistake,\n> I'll think twice before sharing prototypes in the future.\n> \n> Thanks,\n> Jean\n> \n\n\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xn4mG5mKVz9t3P\n\tfor ;\n\tWed, 6 Sep 2017 10:51:58 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752943AbdIFAvo (ORCPT\n\t);\n\tTue, 5 Sep 2017 20:51:44 -0400","from szxga04-in.huawei.com ([45.249.212.190]:5973 \"EHLO\n\tszxga04-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752459AbdIFAvn (ORCPT\n\t); Tue, 5 Sep 2017 20:51:43 -0400","from 172.30.72.60 (EHLO DGGEMS413-HUB.china.huawei.com)\n\t([172.30.72.60])\n\tby dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DGP10990; Wed, 06 Sep 2017 08:51:20 +0800 (CST)","from [127.0.0.1] (10.142.83.150) by DGGEMS413-HUB.china.huawei.com\n\t(10.3.19.213) with Microsoft SMTP Server id 14.3.301.0;\n\tWed, 6 Sep 2017 08:51:07 +0800"],"Subject":"Re: [RFC PATCH 4/6] iommu/arm-smmu-v3: Add SVM support for platform\n\tdevices","To":"Jean-Philippe Brucker ,\n\tYisheng Xie ","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>\n\t<1504167642-14922-5-git-send-email-xieyisheng1@huawei.com>\n\t<039adc54-00f5-bf4e-e509-ffdc67baa15e@arm.com>","CC":", , ,\n\t, ,\n\t, , ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ","From":"Bob Liu ","Message-ID":"<3f4e17fa-dcd0-5692-099a-73105e0e0095@huawei.com>","Date":"Wed, 6 Sep 2017 08:51:05 +0800","User-Agent":"Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101\n\tThunderbird/45.8.0","MIME-Version":"1.0","In-Reply-To":"<039adc54-00f5-bf4e-e509-ffdc67baa15e@arm.com>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","X-Originating-IP":"[10.142.83.150]","X-CFilter-Loop":"Reflected","X-Mirapoint-Virus-RAPID-Raw":"score=unknown(0),\n\trefid=str=0001.0A090206.59AF4689.00D7, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32","X-Mirapoint-Loop-Id":"24a9ec2911777dee5e4fad9c696703e0","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1763757,"web_url":"http://patchwork.ozlabs.org/comment/1763757/","msgid":"","list_archive_url":null,"date":"2017-09-06T01:02:59","subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","submitter":{"id":72301,"url":"http://patchwork.ozlabs.org/api/people/72301/","name":"Bob Liu","email":"liubo95@huawei.com"},"content":"On 2017/9/5 20:56, Jean-Philippe Brucker wrote:\n> On 31/08/17 09:20, Yisheng Xie wrote:\n>> Jean-Philippe has post a patchset for Adding PCIe SVM support to ARM SMMUv3:\n>> https://www.spinics.net/lists/arm-kernel/msg565155.html\n>>\n>> But for some platform devices(aka on-chip integrated devices), there is also\n>> SVM requirement, which works based on the SMMU stall mode.\n>> Jean-Philippe has prepared a prototype patchset to support it:\n>> git://linux-arm.org/linux-jpb.git svm/stall\n> \n> Only meant for testing at that point, and unfit even for an RFC.\n> \n\nSorry for the misunderstanding.\nThe PRI mode patches is in RFC even no hardware for testing, so I thought it's fine for \"Stall mode\" patches sent as RFC.\nWe have tested the Stall mode on our platform.\nAnyway, I should confirm with you in advance.\n\nBtw, Would you consider the \"stall mode\" upstream at first? Since there is no hardware for testing the PRI mode.\n(We can provide you the hardware which support SMMU stall mode if necessary.)\n\n>> We tested this patchset with some fixes on a on-chip integrated device. The\n>> basic function is ok, so I just send them out for review, although this\n>> patchset heavily depends on the former patchset (PCIe SVM support for ARM\n>> SMMUv3), which is still under discussion.\n>>\n>> Patch Overview:\n>> *1 to 3 prepare for device tree or acpi get the device stall ability and pasid bits\n>> *4 is to realise the SVM function for platform device\n>> *5 is fix a bug when test SVM function while SMMU donnot support this feature\n>> *6 avoid ILLEGAL setting of STE and CD entry about stall\n>>\n>> Acctually here, I also have a question about SVM on SMMUv3:\n>>\n>> 1. Why the SVM feature on SMMUv3 depends on BTM feature? when bind a task to device,\n>> it will register a mmu_notify. Therefore, when a page range is invalid, we can\n>> send TLBI or ATC invalid without BTM?\n> \n> We could, but the end goal for SVM is to perfectly mirror the CPU page\n> tables. So for platform SVM we would like to get rid of MMU notifiers\n> entirely.\n> \n>> 2. According to ACPI IORT spec, named component specific data has a node flags field\n>> whoes bit0 is for Stall support. However, it do not have any field for pasid bit.\n>> Can we use other 5 bits[5:1] for pasid bit numbers, so we can have 32 pasid bit for\n>> a single platform device which should be enough, because SMMU only support 20 bit pasid\n>>\n\nAny comment on this?\nThe ACPI IORT spec may need be updated?\n\nRegards,\nLiubo\n\n>> 3. Presently, the pasid is allocate for a task but not for a context, if a task is trying\n>> to bind to 2 device A and B:\n>> a) A support 5 pasid bits\n>> b) B support 2 pasid bits\n>> c) when the task bind to device A, it allocate pasid = 16\n>> d) then it must be fail when trying to bind to task B, for its highest pasid is 4.\n>> So it should allocate a single pasid for a context to avoid this?\n> \n> Ideally yes, but the model chosen for the IOMMU API was one PASID per\n> task, so I implemented this model (the PASID allocator will be common to\n> IOMMU core in the future).\n> \n> Therefore the PASID allocation will fail in your example, and there is no\n> way around it. If you do (d) then (c), the task will have PASID 4.\n> \n> Thanks,\n> Jean\n> \n> .\n> \n\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xn51r1VDWz9s7h\n\tfor ;\n\tWed, 6 Sep 2017 11:03:43 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752145AbdIFBDm (ORCPT\n\t);\n\tTue, 5 Sep 2017 21:03:42 -0400","from szxga05-in.huawei.com ([45.249.212.191]:5541 \"EHLO\n\tszxga05-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752471AbdIFBDm (ORCPT\n\t); Tue, 5 Sep 2017 21:03:42 -0400","from 172.30.72.60 (EHLO DGGEMS404-HUB.china.huawei.com)\n\t([172.30.72.60])\n\tby dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DGR13790; Wed, 06 Sep 2017 09:03:12 +0800 (CST)","from [127.0.0.1] (10.142.83.150) by DGGEMS404-HUB.china.huawei.com\n\t(10.3.19.204) with Microsoft SMTP Server id 14.3.301.0;\n\tWed, 6 Sep 2017 09:03:01 +0800"],"Subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","To":"Jean-Philippe Brucker ,\n\tYisheng Xie ","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>\n\t<95d1a9e2-1816-ff7d-9a8d-98406a6c2c22@arm.com>","CC":", , ,\n\t, ,\n\t, , ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ","From":"Bob Liu ","Message-ID":"","Date":"Wed, 6 Sep 2017 09:02:59 +0800","User-Agent":"Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101\n\tThunderbird/45.8.0","MIME-Version":"1.0","In-Reply-To":"<95d1a9e2-1816-ff7d-9a8d-98406a6c2c22@arm.com>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","X-Originating-IP":"[10.142.83.150]","X-CFilter-Loop":"Reflected","X-Mirapoint-Virus-RAPID-Raw":"score=unknown(0),\n\trefid=str=0001.0A020204.59AF4951.0196, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32","X-Mirapoint-Loop-Id":"d7765235516df6b4b4b943d0efef56cd","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1763765,"web_url":"http://patchwork.ozlabs.org/comment/1763765/","msgid":"","list_archive_url":null,"date":"2017-09-06T01:16:38","subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","submitter":{"id":72263,"url":"http://patchwork.ozlabs.org/api/people/72263/","name":"Yisheng Xie","email":"xieyisheng1@huawei.com"},"content":"Hi Jean-Philippe,\n\nOn 2017/9/5 20:56, Jean-Philippe Brucker wrote:\n> On 31/08/17 09:20, Yisheng Xie wrote:\n>> Jean-Philippe has post a patchset for Adding PCIe SVM support to ARM SMMUv3:\n>> https://www.spinics.net/lists/arm-kernel/msg565155.html\n>>\n>> But for some platform devices(aka on-chip integrated devices), there is also\n>> SVM requirement, which works based on the SMMU stall mode.\n>> Jean-Philippe has prepared a prototype patchset to support it:\n>> git://linux-arm.org/linux-jpb.git svm/stall\n> \n> Only meant for testing at that point, and unfit even for an RFC.\n\nSorry about that, I should ask you before send it out. It's my mistake. For I also\nhave some question about this patchset.\n\nWe have related device, and would like to do some help about it. Do you have\nany plan about upstream ?\n\n> \n>> We tested this patchset with some fixes on a on-chip integrated device. The\n>> basic function is ok, so I just send them out for review, although this\n>> patchset heavily depends on the former patchset (PCIe SVM support for ARM\n>> SMMUv3), which is still under discussion.\n>>\n>> Patch Overview:\n>> *1 to 3 prepare for device tree or acpi get the device stall ability and pasid bits\n>> *4 is to realise the SVM function for platform device\n>> *5 is fix a bug when test SVM function while SMMU donnot support this feature\n>> *6 avoid ILLEGAL setting of STE and CD entry about stall\n>>\n>> Acctually here, I also have some questions about SVM on SMMUv3:\n>>\n>> 1. Why the SVM feature on SMMUv3 depends on BTM feature? when bind a task to device,\n>> it will register a mmu_notify. Therefore, when a page range is invalid, we can\n>> send TLBI or ATC invalid without BTM?\n> \n> We could, but the end goal for SVM is to perfectly mirror the CPU page\n> tables. So for platform SVM we would like to get rid of MMU notifiers\n> entirely.\n\nI see, but for some SMMU which do not support BTM, it cannot benefit from SVM.\n\nMeanwhile, do you mean even with BTM feature, the PCI-e device also need to send a\nATC invalid by MMU notify? It seems not fair, why not hardware do the entirely work\nin this case? It may costly for send ATC invalid and sync.\n\n> \n>> 2. According to ACPI IORT spec, named component specific data has a node flags field\n>> whoes bit0 is for Stall support. However, it do not have any field for pasid bit.\n>> Can we use other 5 bits[5:1] for pasid bit numbers, so we can have 32 pasid bit for\n>> a single platform device which should be enough, because SMMU only support 20 bit pasid\n>>\n>> 3. Presently, the pasid is allocate for a task but not for a context, if a task is trying\n>> to bind to 2 device A and B:\n>> a) A support 5 pasid bits\n>> b) B support 2 pasid bits\n>> c) when the task bind to device A, it allocate pasid = 16\n>> d) then it must be fail when trying to bind to task B, for its highest pasid is 4.\n>> So it should allocate a single pasid for a context to avoid this?\n> \n> Ideally yes, but the model chosen for the IOMMU API was one PASID per\n> task, so I implemented this model (the PASID allocator will be common to\n> IOMMU core in the future).\nIt is fair, for each IOMMU need PASID allocator to support SVM.\n\nThanks\nYisheng Xie\n\n> \n> Therefore the PASID allocation will fail in your example, and there is no\n> way around it. If you do (d) then (c), the task will have PASID 4.\n> \n> Thanks,\n> Jean\n> \n> .\n> \n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xn5LC4Lxpz9t3Z\n\tfor ;\n\tWed, 6 Sep 2017 11:17:55 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753013AbdIFBRx (ORCPT\n\t);\n\tTue, 5 Sep 2017 21:17:53 -0400","from szxga05-in.huawei.com ([45.249.212.191]:5542 \"EHLO\n\tszxga05-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752221AbdIFBRx (ORCPT\n\t); Tue, 5 Sep 2017 21:17:53 -0400","from 172.30.72.58 (EHLO DGGEMS407-HUB.china.huawei.com)\n\t([172.30.72.58])\n\tby dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DGR16375; Wed, 06 Sep 2017 09:17:00 +0800 (CST)","from [127.0.0.1] (10.177.29.40) by DGGEMS407-HUB.china.huawei.com\n\t(10.3.19.207) with Microsoft SMTP Server id 14.3.301.0;\n\tWed, 6 Sep 2017 09:16:51 +0800"],"Subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","To":"Jean-Philippe Brucker ","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>\n\t<95d1a9e2-1816-ff7d-9a8d-98406a6c2c22@arm.com>","CC":", , ,\n\t, ,\n\t, , ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, , ","From":"Yisheng Xie ","Message-ID":"","Date":"Wed, 6 Sep 2017 09:16:38 +0800","User-Agent":"Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101\n\tThunderbird/45.1.0","MIME-Version":"1.0","In-Reply-To":"<95d1a9e2-1816-ff7d-9a8d-98406a6c2c22@arm.com>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","X-Originating-IP":"[10.177.29.40]","X-CFilter-Loop":"Reflected","X-Mirapoint-Virus-RAPID-Raw":"score=unknown(0),\n\trefid=str=0001.0A020206.59AF4C8D.003D, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32","X-Mirapoint-Loop-Id":"d7765235516df6b4b4b943d0efef56cd","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1763767,"web_url":"http://patchwork.ozlabs.org/comment/1763767/","msgid":"","list_archive_url":null,"date":"2017-09-06T01:20:32","subject":"Re: [RFC PATCH 4/6] iommu/arm-smmu-v3: Add SVM support for platform\n\tdevices","submitter":{"id":72263,"url":"http://patchwork.ozlabs.org/api/people/72263/","name":"Yisheng Xie","email":"xieyisheng1@huawei.com"},"content":"Hi Jean-Philippe,\n\nOn 2017/9/6 8:51, Bob Liu wrote:\n> On 2017/9/5 20:53, Jean-Philippe Brucker wrote:\n>> On 31/08/17 09:20, Yisheng Xie wrote:\n>>> From: Jean-Philippe Brucker \n>>>\n>>> Platform device can realise SVM function by using the stall mode. That\n>>> is to say, when device access a memory via iova which is not populated,\n>>> it will stalled and when SMMU try to translate this iova, it also will\n>>> stall and meanwhile send an event to CPU via MSI.\n>>>\n>>> After SMMU driver handle the event and populated the iova, it will send\n>>> a RESUME command to SMMU to exit the stall mode, therefore the platform\n>>> device can contiue access the memory.\n>>>\n>>> Signed-off-by: Jean-Philippe Brucker \n>>\n>> No. Please don't forge a signed-off-by under a commit message you wrote,\n\nSorry about that, it is my mistake.\n\n> \n> Really sorry for that.\n> We sent out the wrong version, I should take more careful review.\n> \n> Regards,\n> Liubo\n> \n>> it's rude. I didn't sign it, didn't consider it fit for mainline or even\n>> as an RFC, and wanted to have another read before sending. My mistake,\n>> I'll think twice before sharing prototypes in the future.\n>>\n>> Thanks,\n>> Jean\n>>\n> \n> \n> \n> \n> .\n> \n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xn5Q16p7Mz9t3Z\n\tfor ;\n\tWed, 6 Sep 2017 11:21:13 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752727AbdIFBVM (ORCPT\n\t);\n\tTue, 5 Sep 2017 21:21:12 -0400","from szxga05-in.huawei.com ([45.249.212.191]:5543 \"EHLO\n\tszxga05-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750880AbdIFBVL (ORCPT\n\t); Tue, 5 Sep 2017 21:21:11 -0400","from 172.30.72.60 (EHLO DGGEMS410-HUB.china.huawei.com)\n\t([172.30.72.60])\n\tby dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DGR17097; Wed, 06 Sep 2017 09:20:54 +0800 (CST)","from [127.0.0.1] (10.177.29.40) by DGGEMS410-HUB.china.huawei.com\n\t(10.3.19.210) with Microsoft SMTP Server id 14.3.301.0;\n\tWed, 6 Sep 2017 09:20:45 +0800"],"Subject":"Re: [RFC PATCH 4/6] iommu/arm-smmu-v3: Add SVM support for platform\n\tdevices","To":"Bob Liu ,\n\tJean-Philippe Brucker ","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>\n\t<1504167642-14922-5-git-send-email-xieyisheng1@huawei.com>\n\t<039adc54-00f5-bf4e-e509-ffdc67baa15e@arm.com>\n\t<3f4e17fa-dcd0-5692-099a-73105e0e0095@huawei.com>","CC":", , ,\n\t, ,\n\t, , ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ","From":"Yisheng Xie ","Message-ID":"","Date":"Wed, 6 Sep 2017 09:20:32 +0800","User-Agent":"Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101\n\tThunderbird/45.1.0","MIME-Version":"1.0","In-Reply-To":"<3f4e17fa-dcd0-5692-099a-73105e0e0095@huawei.com>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","X-Originating-IP":"[10.177.29.40]","X-CFilter-Loop":"Reflected","X-Mirapoint-Virus-RAPID-Raw":"score=unknown(0),\n\trefid=str=0001.0A020205.59AF4D76.0053, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32","X-Mirapoint-Loop-Id":"49fbd273253cce5d78dd53395dbcdca1","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1763769,"web_url":"http://patchwork.ozlabs.org/comment/1763769/","msgid":"<1bd8a485-d915-5d82-1ffe-0754b32a7656@linaro.org>","list_archive_url":null,"date":"2017-09-06T01:24:23","subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","submitter":{"id":47236,"url":"http://patchwork.ozlabs.org/api/people/47236/","name":"Hanjun Guo","email":"hanjun.guo@linaro.org"},"content":"On 2017/8/31 16:20, Yisheng Xie wrote:\n> Jean-Philippe has post a patchset for Adding PCIe SVM support to ARM SMMUv3:\n> https://www.spinics.net/lists/arm-kernel/msg565155.html\n> \n> But for some platform devices(aka on-chip integrated devices), there is also\n> SVM requirement, which works based on the SMMU stall mode.\n> Jean-Philippe has prepared a prototype patchset to support it:\n> git://linux-arm.org/linux-jpb.git svm/stall\n> \n> We tested this patchset with some fixes on a on-chip integrated device. The\n> basic function is ok, so I just send them out for review, although this\n> patchset heavily depends on the former patchset (PCIe SVM support for ARM\n> SMMUv3), which is still under discussion.\n> \n> Patch Overview:\n> *1 to 3 prepare for device tree or acpi get the device stall ability and pasid bits\n> *4 is to realise the SVM function for platform device\n> *5 is fix a bug when test SVM function while SMMU donnot support this feature\n> *6 avoid ILLEGAL setting of STE and CD entry about stall\n> \n> Acctually here, I also have a question about SVM on SMMUv3:\n> \n> 1. Why the SVM feature on SMMUv3 depends on BTM feature? when bind a task to device,\n> it will register a mmu_notify. Therefore, when a page range is invalid, we can\n> send TLBI or ATC invalid without BTM?\n> \n> 2. According to ACPI IORT spec, named component specific data has a node flags field\n> whoes bit0 is for Stall support. However, it do not have any field for pasid bit.\n> Can we use other 5 bits[5:1] for pasid bit numbers, so we can have 32 pasid bit for\n> a single platform device which should be enough, because SMMU only support 20 bit pasid\n\nI think we can propose something similar, it's a missing function in\nIORT.\n\nThanks\nHanjun\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"FKjiz7z2\"; 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\n\tTue, 05 Sep 2017 18:24:31 -0700 (PDT)","Subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","To":"Yisheng Xie , jean-philippe.brucker@arm.com","Cc":"joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com,\n\tlorenzo.pieralisi@arm.com, sudeep.holla@arm.com, rjw@rjwysocki.net,\n\tlenb@kernel.org, will.deacon@arm.com, robin.murphy@arm.com,\n\trobert.moore@intel.com, lv.zheng@intel.com,\n\tiommu@lists.linux-foundation.org, devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, devel@acpica.org,\n\tliubo95@huawei.com, chenjiankang1@huawei.com, xieyisheng@huawei.com","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>","From":"Hanjun Guo ","Message-ID":"<1bd8a485-d915-5d82-1ffe-0754b32a7656@linaro.org>","Date":"Wed, 6 Sep 2017 09:24:23 +0800","User-Agent":"Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1763787,"web_url":"http://patchwork.ozlabs.org/comment/1763787/","msgid":"","list_archive_url":null,"date":"2017-09-06T02:23:00","subject":"Re: [RFC PATCH 6/6] iommu/arm-smmu-v3: Avoid ILLEGAL setting of\n\tSTE.S1STALLD and CD.S","submitter":{"id":72263,"url":"http://patchwork.ozlabs.org/api/people/72263/","name":"Yisheng Xie","email":"xieyisheng1@huawei.com"},"content":"Hi Jean-Philippe,\n\nOn 2017/9/5 20:54, Jean-Philippe Brucker wrote:\n> On 31/08/17 09:20, Yisheng Xie wrote:\n>> It is ILLEGAL to set STE.S1STALLD if STALL_MODEL is not 0b00, which\n>> means we should not disable stall mode if stall/terminate mode is not\n>> configuable.\n>>\n>> Meanwhile, it is also ILLEGAL when STALL_MODEL==0b10 && CD.S==0 which\n>> means if stall mode is force we should always set CD.S.\n>>\n>> This patch add ARM_SMMU_FEAT_TERMINATE feature bit for smmu, and use\n>> TERMINATE feature checking to ensue above ILLEGAL cases from happening.\n>>\n>> Signed-off-by: Yisheng Xie \n>> ---\n>> drivers/iommu/arm-smmu-v3.c | 22 ++++++++++++++++------\n>> 1 file changed, 16 insertions(+), 6 deletions(-)\n>>\n>> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c\n>> index dbda2eb..0745522 100644\n>> --- a/drivers/iommu/arm-smmu-v3.c\n>> +++ b/drivers/iommu/arm-smmu-v3.c\n>> @@ -55,6 +55,7 @@\n>> #define IDR0_STALL_MODEL_SHIFT\t\t24\n>> #define IDR0_STALL_MODEL_MASK\t\t0x3\n>> #define IDR0_STALL_MODEL_STALL\t\t(0 << IDR0_STALL_MODEL_SHIFT)\n>> +#define IDR0_STALL_MODEL_NS\t\t(1 << IDR0_STALL_MODEL_SHIFT)\n>> #define IDR0_STALL_MODEL_FORCE\t\t(2 << IDR0_STALL_MODEL_SHIFT)\n>> #define IDR0_TTENDIAN_SHIFT\t\t21\n>> #define IDR0_TTENDIAN_MASK\t\t0x3\n>> @@ -766,6 +767,7 @@ struct arm_smmu_device {\n>> #define ARM_SMMU_FEAT_SVM\t\t(1 << 15)\n>> #define ARM_SMMU_FEAT_HA\t\t(1 << 16)\n>> #define ARM_SMMU_FEAT_HD\t\t(1 << 17)\n>> +#define ARM_SMMU_FEAT_TERMINATE\t\t(1 << 18)\n> \n> I'd rather introduce something like \"ARM_SMMU_FEAT_STALL_FORCE\" instead.\n> Terminate model has another meaning, and is defined by a different bit in\n> IDR0.\n\nOk, sound more reasonable.\n\nThanks\nYisheng Xie\n\n> \n> Thanks,\n> Jean\n> \n> .\n> \n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xn6pn26Kwz9t3Z\n\tfor ;\n\tWed, 6 Sep 2017 12:24:17 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753540AbdIFCYN (ORCPT\n\t);\n\tTue, 5 Sep 2017 22:24:13 -0400","from szxga04-in.huawei.com ([45.249.212.190]:5975 \"EHLO\n\tszxga04-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752340AbdIFCYM (ORCPT\n\t); Tue, 5 Sep 2017 22:24:12 -0400","from 172.30.72.59 (EHLO DGGEMS407-HUB.china.huawei.com)\n\t([172.30.72.59])\n\tby dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DGP26697; Wed, 06 Sep 2017 10:23:22 +0800 (CST)","from [127.0.0.1] (10.177.29.40) by DGGEMS407-HUB.china.huawei.com\n\t(10.3.19.207) with Microsoft SMTP Server id 14.3.301.0;\n\tWed, 6 Sep 2017 10:23:12 +0800"],"Subject":"Re: [RFC PATCH 6/6] iommu/arm-smmu-v3: Avoid ILLEGAL setting of\n\tSTE.S1STALLD and CD.S","To":"Jean-Philippe Brucker ","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>\n\t<1504167642-14922-7-git-send-email-xieyisheng1@huawei.com>\n\t<738977bb-4cd7-7d86-0ea0-0c88b6af721c@arm.com>","CC":", , ,\n\t, ,\n\t, , ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, , ","From":"Yisheng Xie ","Message-ID":"","Date":"Wed, 6 Sep 2017 10:23:00 +0800","User-Agent":"Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101\n\tThunderbird/45.1.0","MIME-Version":"1.0","In-Reply-To":"<738977bb-4cd7-7d86-0ea0-0c88b6af721c@arm.com>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","X-Originating-IP":"[10.177.29.40]","X-CFilter-Loop":"Reflected","X-Mirapoint-Virus-RAPID-Raw":"score=unknown(0),\n\trefid=str=0001.0A020201.59AF5C1A.00C2, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32","X-Mirapoint-Loop-Id":"eaac97f5f94b6b047243d4909bd1c3ff","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1763970,"web_url":"http://patchwork.ozlabs.org/comment/1763970/","msgid":"<2874a1f3-22f1-20d4-4009-50add127a10f@arm.com>","list_archive_url":null,"date":"2017-09-06T09:57:34","subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","submitter":{"id":68357,"url":"http://patchwork.ozlabs.org/api/people/68357/","name":"Jean-Philippe Brucker","email":"Jean-Philippe.Brucker@arm.com"},"content":"On 06/09/17 02:02, Bob Liu wrote:\n> On 2017/9/5 20:56, Jean-Philippe Brucker wrote:\n>> On 31/08/17 09:20, Yisheng Xie wrote:\n>>> Jean-Philippe has post a patchset for Adding PCIe SVM support to ARM SMMUv3:\n>>> https://www.spinics.net/lists/arm-kernel/msg565155.html\n>>>\n>>> But for some platform devices(aka on-chip integrated devices), there is also\n>>> SVM requirement, which works based on the SMMU stall mode.\n>>> Jean-Philippe has prepared a prototype patchset to support it:\n>>> git://linux-arm.org/linux-jpb.git svm/stall\n>>\n>> Only meant for testing at that point, and unfit even for an RFC.\n>>\n> \n> Sorry for the misunderstanding.\n> The PRI mode patches is in RFC even no hardware for testing, so I thought it's fine for \"Stall mode\" patches sent as RFC.\n> We have tested the Stall mode on our platform.\n> Anyway, I should confirm with you in advance.\n> \n> Btw, Would you consider the \"stall mode\" upstream at first? Since there is no hardware for testing the PRI mode.\n> (We can provide you the hardware which support SMMU stall mode if necessary.)\n\nYes. What's blocking the ATS, PRI and PASID patches at the moment is the\nlack of endpoints for testing. There has been lots of discussion on the\nAPI side since my first RFC and I'd like to resubmit the API changes soon.\nIt is the same API for ATS+PRI+PASID and SSID+Stall, so the backend\ndoesn't matter.\n\nI'm considering upstreaming SSID+Stall first if it can be tested on\nhardware (having direct access to it would certainly speed things up).\nThis would require some work in moving the PCI bits at the end of the\nseries. I can reserve some time in the coming months to do it, but I need\nto know what to focus on. Are you able to test SSID as well?\n\n>>> We tested this patchset with some fixes on a on-chip integrated device. The\n>>> basic function is ok, so I just send them out for review, although this\n>>> patchset heavily depends on the former patchset (PCIe SVM support for ARM\n>>> SMMUv3), which is still under discussion.\n>>>\n>>> Patch Overview:\n>>> *1 to 3 prepare for device tree or acpi get the device stall ability and pasid bits\n>>> *4 is to realise the SVM function for platform device\n>>> *5 is fix a bug when test SVM function while SMMU donnot support this feature\n>>> *6 avoid ILLEGAL setting of STE and CD entry about stall\n>>>\n>>> Acctually here, I also have a question about SVM on SMMUv3:\n>>>\n>>> 1. Why the SVM feature on SMMUv3 depends on BTM feature? when bind a task to device,\n>>> it will register a mmu_notify. Therefore, when a page range is invalid, we can\n>>> send TLBI or ATC invalid without BTM?\n>>\n>> We could, but the end goal for SVM is to perfectly mirror the CPU page\n>> tables. So for platform SVM we would like to get rid of MMU notifiers\n>> entirely.\n>>\n>>> 2. According to ACPI IORT spec, named component specific data has a node flags field\n>>> whoes bit0 is for Stall support. However, it do not have any field for pasid bit.\n>>> Can we use other 5 bits[5:1] for pasid bit numbers, so we can have 32 pasid bit for\n>>> a single platform device which should be enough, because SMMU only support 20 bit pasid\n>>>\n> \n> Any comment on this?\n> The ACPI IORT spec may need be updated?\n\nI suppose that the Named Component Node could be used for SSID and stall\ncapability bits. Can't the ACPI namespace entries be extended to host\nthese capabilities in a more generic way? Platforms with different IOMMUs\nmight also need this information some day.\n\nThanks,\nJean\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xnJpK0Wshz9sNc\n\tfor ;\n\tWed, 6 Sep 2017 19:54:33 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752686AbdIFJyR (ORCPT\n\t);\n\tWed, 6 Sep 2017 05:54:17 -0400","from foss.arm.com ([217.140.101.70]:48386 \"EHLO foss.arm.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1752624AbdIFJyQ (ORCPT );\n\tWed, 6 Sep 2017 05:54:16 -0400","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C151515AD;\n\tWed, 6 Sep 2017 02:54:15 -0700 (PDT)","from [10.1.211.72] (e106794-lin.cambridge.arm.com [10.1.211.72])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\t3B2CD3F3E1; Wed, 6 Sep 2017 02:54:12 -0700 (PDT)"],"Subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","To":"Bob Liu , Yisheng Xie ","Cc":"joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com,\n\tlorenzo.pieralisi@arm.com, hanjun.guo@linaro.org,\n\tsudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org,\n\twill.deacon@arm.com, robin.murphy@arm.com, robert.moore@intel.com,\n\tlv.zheng@intel.com, iommu@lists.linux-foundation.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tdevel@acpica.org, chenjiankang1@huawei.com, xieyisheng@huawei.com","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>\n\t<95d1a9e2-1816-ff7d-9a8d-98406a6c2c22@arm.com>\n\t","From":"Jean-Philippe Brucker ","Message-ID":"<2874a1f3-22f1-20d4-4009-50add127a10f@arm.com>","Date":"Wed, 6 Sep 2017 10:57:34 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1763974,"web_url":"http://patchwork.ozlabs.org/comment/1763974/","msgid":"","list_archive_url":null,"date":"2017-09-06T09:59:43","subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","submitter":{"id":68357,"url":"http://patchwork.ozlabs.org/api/people/68357/","name":"Jean-Philippe Brucker","email":"Jean-Philippe.Brucker@arm.com"},"content":"On 06/09/17 02:16, Yisheng Xie wrote:\n> Hi Jean-Philippe,\n> \n> On 2017/9/5 20:56, Jean-Philippe Brucker wrote:\n>> On 31/08/17 09:20, Yisheng Xie wrote:\n>>> Jean-Philippe has post a patchset for Adding PCIe SVM support to ARM SMMUv3:\n>>> https://www.spinics.net/lists/arm-kernel/msg565155.html\n>>>\n>>> But for some platform devices(aka on-chip integrated devices), there is also\n>>> SVM requirement, which works based on the SMMU stall mode.\n>>> Jean-Philippe has prepared a prototype patchset to support it:\n>>> git://linux-arm.org/linux-jpb.git svm/stall\n>>\n>> Only meant for testing at that point, and unfit even for an RFC.\n> \n> Sorry about that, I should ask you before send it out. It's my mistake. For I also\n> have some question about this patchset.\n> \n> We have related device, and would like to do some help about it. Do you have\n> any plan about upstream ?\n> \n>>\n>>> We tested this patchset with some fixes on a on-chip integrated device. The\n>>> basic function is ok, so I just send them out for review, although this\n>>> patchset heavily depends on the former patchset (PCIe SVM support for ARM\n>>> SMMUv3), which is still under discussion.\n>>>\n>>> Patch Overview:\n>>> *1 to 3 prepare for device tree or acpi get the device stall ability and pasid bits\n>>> *4 is to realise the SVM function for platform device\n>>> *5 is fix a bug when test SVM function while SMMU donnot support this feature\n>>> *6 avoid ILLEGAL setting of STE and CD entry about stall\n>>>\n>>> Acctually here, I also have some questions about SVM on SMMUv3:\n>>>\n>>> 1. Why the SVM feature on SMMUv3 depends on BTM feature? when bind a task to device,\n>>> it will register a mmu_notify. Therefore, when a page range is invalid, we can\n>>> send TLBI or ATC invalid without BTM?\n>>\n>> We could, but the end goal for SVM is to perfectly mirror the CPU page\n>> tables. So for platform SVM we would like to get rid of MMU notifiers\n>> entirely.\n> \n> I see, but for some SMMU which do not support BTM, it cannot benefit from SVM.\n> \n> Meanwhile, do you mean even with BTM feature, the PCI-e device also need to send a\n> ATC invalid by MMU notify? It seems not fair, why not hardware do the entirely work\n> in this case? It may costly for send ATC invalid and sync.\n\nIt will certainly be costly. But there are major problems with\ntransforming broadcast TLB maintenance into ATC invalidations in HW:\n\n* VMID:ASID to SID:SSID conversion. TLBIs use VMID:ASID, while ATCIs use\nSID:SSID.\n\n* Most importantly, ATC invalidations accounting. Each endpoint has a\nlimited number of in-flight ATC invalidate requests. The conversion module\nwould have to buffer incoming invalidations and wait for in-flight ATC\ninvalidation to complete before sending the next ones. In case of\noverflow, either we lose invalidation (which opens security holes) or we\nsomehow put back-pressure on the interconnect (no idea how feasible this\nis, I suspect really hard).\n\nSolving the last one is also quite difficult in software, but at least we\ncan still invalidate a range. In hardware we would invalidate the ATC\npage-by-page and quickly jam the bus.\n\nThanks,\nJean\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xnJrW1KXmz9sNc\n\tfor ;\n\tWed, 6 Sep 2017 19:56:27 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752391AbdIFJ4Z (ORCPT\n\t);\n\tWed, 6 Sep 2017 05:56:25 -0400","from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:48534 \"EHLO\n\tfoss.arm.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1752220AbdIFJ4Y (ORCPT );\n\tWed, 6 Sep 2017 05:56:24 -0400","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D960A13D5;\n\tWed, 6 Sep 2017 02:56:23 -0700 (PDT)","from [10.1.211.72] (e106794-lin.cambridge.arm.com [10.1.211.72])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\t6B4E03F3E1; Wed, 6 Sep 2017 02:56:20 -0700 (PDT)"],"Subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","To":"Yisheng Xie ","Cc":"joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com,\n\tlorenzo.pieralisi@arm.com, hanjun.guo@linaro.org,\n\tsudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org,\n\twill.deacon@arm.com, robin.murphy@arm.com, robert.moore@intel.com,\n\tlv.zheng@intel.com, iommu@lists.linux-foundation.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tdevel@acpica.org, liubo95@huawei.com, chenjiankang1@huawei.com,\n\txieyisheng@huawei.com","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>\n\t<95d1a9e2-1816-ff7d-9a8d-98406a6c2c22@arm.com>\n\t","From":"Jean-Philippe Brucker ","Message-ID":"","Date":"Wed, 6 Sep 2017 10:59:43 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1764462,"web_url":"http://patchwork.ozlabs.org/comment/1764462/","msgid":"<1d358989-48bb-ccde-d7d9-36e004bc2d78@huawei.com>","list_archive_url":null,"date":"2017-09-07T01:41:42","subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","submitter":{"id":72301,"url":"http://patchwork.ozlabs.org/api/people/72301/","name":"Bob Liu","email":"liubo95@huawei.com"},"content":"On 2017/9/6 17:57, Jean-Philippe Brucker wrote:\n> On 06/09/17 02:02, Bob Liu wrote:\n>> On 2017/9/5 20:56, Jean-Philippe Brucker wrote:\n>>> On 31/08/17 09:20, Yisheng Xie wrote:\n>>>> Jean-Philippe has post a patchset for Adding PCIe SVM support to ARM SMMUv3:\n>>>> https://www.spinics.net/lists/arm-kernel/msg565155.html\n>>>>\n>>>> But for some platform devices(aka on-chip integrated devices), there is also\n>>>> SVM requirement, which works based on the SMMU stall mode.\n>>>> Jean-Philippe has prepared a prototype patchset to support it:\n>>>> git://linux-arm.org/linux-jpb.git svm/stall\n>>>\n>>> Only meant for testing at that point, and unfit even for an RFC.\n>>>\n>>\n>> Sorry for the misunderstanding.\n>> The PRI mode patches is in RFC even no hardware for testing, so I thought it's fine for \"Stall mode\" patches sent as RFC.\n>> We have tested the Stall mode on our platform.\n>> Anyway, I should confirm with you in advance.\n>>\n>> Btw, Would you consider the \"stall mode\" upstream at first? Since there is no hardware for testing the PRI mode.\n>> (We can provide you the hardware which support SMMU stall mode if necessary.)\n> \n> Yes. What's blocking the ATS, PRI and PASID patches at the moment is the\n> lack of endpoints for testing. There has been lots of discussion on the\n> API side since my first RFC and I'd like to resubmit the API changes soon.\n> It is the same API for ATS+PRI+PASID and SSID+Stall, so the backend\n> doesn't matter.\n> \n\nIndeed!\n\n> I'm considering upstreaming SSID+Stall first if it can be tested on\n> hardware (having direct access to it would certainly speed things up).\n\nGlad to hear that.\n\n> This would require some work in moving the PCI bits at the end of the\n> series. I can reserve some time in the coming months to do it, but I need\n> to know what to focus on. Are you able to test SSID as well?\n> \n\nYes, but the difficulty is our devices are on-chip integrated hardware accelerators which requires complicate driver.\nYou may need much time to understand the driver.\nThat's the same case as intel/amd SVM, the current user is their GPU :-(\n\nBtw, what kind of device/method do you think is ideal for testing arm-SVM?\n\n>>>> We tested this patchset with some fixes on a on-chip integrated device. The\n>>>> basic function is ok, so I just send them out for review, although this\n>>>> patchset heavily depends on the former patchset (PCIe SVM support for ARM\n>>>> SMMUv3), which is still under discussion.\n>>>>\n>>>> Patch Overview:\n>>>> *1 to 3 prepare for device tree or acpi get the device stall ability and pasid bits\n>>>> *4 is to realise the SVM function for platform device\n>>>> *5 is fix a bug when test SVM function while SMMU donnot support this feature\n>>>> *6 avoid ILLEGAL setting of STE and CD entry about stall\n>>>>\n>>>> Acctually here, I also have a question about SVM on SMMUv3:\n>>>>\n>>>> 1. Why the SVM feature on SMMUv3 depends on BTM feature? when bind a task to device,\n>>>> it will register a mmu_notify. Therefore, when a page range is invalid, we can\n>>>> send TLBI or ATC invalid without BTM?\n>>>\n>>> We could, but the end goal for SVM is to perfectly mirror the CPU page\n>>> tables. So for platform SVM we would like to get rid of MMU notifiers\n>>> entirely.\n>>>\n>>>> 2. According to ACPI IORT spec, named component specific data has a node flags field\n>>>> whoes bit0 is for Stall support. However, it do not have any field for pasid bit.\n>>>> Can we use other 5 bits[5:1] for pasid bit numbers, so we can have 32 pasid bit for\n>>>> a single platform device which should be enough, because SMMU only support 20 bit pasid\n>>>>\n>>\n>> Any comment on this?\n>> The ACPI IORT spec may need be updated?\n> \n> I suppose that the Named Component Node could be used for SSID and stall\n> capability bits. Can't the ACPI namespace entries be extended to host\n> these capabilities in a more generic way? Platforms with different IOMMUs\n> might also need this information some day.\n> \n\nHmm, that would be better.\nBut in anyway, it depends on the ACPI IORT Spec would be extended in next version.\n\n--\nThanks,\nBob Liu\n\n\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xnjt139fhz9t2r\n\tfor ;\n\tThu, 7 Sep 2017 11:44:09 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751875AbdIGBoH (ORCPT\n\t);\n\tWed, 6 Sep 2017 21:44:07 -0400","from szxga04-in.huawei.com ([45.249.212.190]:5989 \"EHLO\n\tszxga04-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751369AbdIGBoG (ORCPT\n\t); Wed, 6 Sep 2017 21:44:06 -0400","from 172.30.72.60 (EHLO DGGEMS407-HUB.china.huawei.com)\n\t([172.30.72.60])\n\tby dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DGQ99641; Thu, 07 Sep 2017 09:43:38 +0800 (CST)","from [127.0.0.1] (10.142.83.150) by DGGEMS407-HUB.china.huawei.com\n\t(10.3.19.207) with Microsoft SMTP Server id 14.3.301.0;\n\tThu, 7 Sep 2017 09:43:29 +0800"],"Subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","To":"Jean-Philippe Brucker ,\n\tYisheng Xie ","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>\n\t<95d1a9e2-1816-ff7d-9a8d-98406a6c2c22@arm.com>\n\t\n\t<2874a1f3-22f1-20d4-4009-50add127a10f@arm.com>","CC":", , ,\n\t, ,\n\t, , ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ","From":"Bob Liu ","Message-ID":"<1d358989-48bb-ccde-d7d9-36e004bc2d78@huawei.com>","Date":"Thu, 7 Sep 2017 09:41:42 +0800","User-Agent":"Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101\n\tThunderbird/45.8.0","MIME-Version":"1.0","In-Reply-To":"<2874a1f3-22f1-20d4-4009-50add127a10f@arm.com>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","X-Originating-IP":"[10.142.83.150]","X-CFilter-Loop":"Reflected","X-Mirapoint-Virus-RAPID-Raw":"score=unknown(0),\n\trefid=str=0001.0A090204.59B0A44A.0112, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32","X-Mirapoint-Loop-Id":"1fbf0095867358040b476e1df2032556","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1764472,"web_url":"http://patchwork.ozlabs.org/comment/1764472/","msgid":"<8e4764f5-0e5d-7fd6-529b-35914e1e3668@huawei.com>","list_archive_url":null,"date":"2017-09-07T01:55:49","subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","submitter":{"id":72301,"url":"http://patchwork.ozlabs.org/api/people/72301/","name":"Bob Liu","email":"liubo95@huawei.com"},"content":"On 2017/9/6 17:59, Jean-Philippe Brucker wrote:\n> On 06/09/17 02:16, Yisheng Xie wrote:\n>> Hi Jean-Philippe,\n>>\n>> On 2017/9/5 20:56, Jean-Philippe Brucker wrote:\n>>> On 31/08/17 09:20, Yisheng Xie wrote:\n>>>> Jean-Philippe has post a patchset for Adding PCIe SVM support to ARM SMMUv3:\n>>>> https://www.spinics.net/lists/arm-kernel/msg565155.html\n>>>>\n>>>> But for some platform devices(aka on-chip integrated devices), there is also\n>>>> SVM requirement, which works based on the SMMU stall mode.\n>>>> Jean-Philippe has prepared a prototype patchset to support it:\n>>>> git://linux-arm.org/linux-jpb.git svm/stall\n>>>\n>>> Only meant for testing at that point, and unfit even for an RFC.\n>>\n>> Sorry about that, I should ask you before send it out. It's my mistake. For I also\n>> have some question about this patchset.\n>>\n>> We have related device, and would like to do some help about it. Do you have\n>> any plan about upstream ?\n>>\n>>>\n>>>> We tested this patchset with some fixes on a on-chip integrated device. The\n>>>> basic function is ok, so I just send them out for review, although this\n>>>> patchset heavily depends on the former patchset (PCIe SVM support for ARM\n>>>> SMMUv3), which is still under discussion.\n>>>>\n>>>> Patch Overview:\n>>>> *1 to 3 prepare for device tree or acpi get the device stall ability and pasid bits\n>>>> *4 is to realise the SVM function for platform device\n>>>> *5 is fix a bug when test SVM function while SMMU donnot support this feature\n>>>> *6 avoid ILLEGAL setting of STE and CD entry about stall\n>>>>\n>>>> Acctually here, I also have some questions about SVM on SMMUv3:\n>>>>\n>>>> 1. Why the SVM feature on SMMUv3 depends on BTM feature? when bind a task to device,\n>>>> it will register a mmu_notify. Therefore, when a page range is invalid, we can\n>>>> send TLBI or ATC invalid without BTM?\n>>>\n>>> We could, but the end goal for SVM is to perfectly mirror the CPU page\n>>> tables. So for platform SVM we would like to get rid of MMU notifiers\n>>> entirely.\n>>\n>> I see, but for some SMMU which do not support BTM, it cannot benefit from SVM.\n>>\n>> Meanwhile, do you mean even with BTM feature, the PCI-e device also need to send a\n>> ATC invalid by MMU notify? It seems not fair, why not hardware do the entirely work\n>> in this case? It may costly for send ATC invalid and sync.\n> \n> It will certainly be costly. But there are major problems with\n> transforming broadcast TLB maintenance into ATC invalidations in HW:\n> \n> * VMID:ASID to SID:SSID conversion. TLBIs use VMID:ASID, while ATCIs use\n> SID:SSID.\n> \n> * Most importantly, ATC invalidations accounting. Each endpoint has a\n> limited number of in-flight ATC invalidate requests. The conversion module\n> would have to buffer incoming invalidations and wait for in-flight ATC\n> invalidation to complete before sending the next ones. In case of\n> overflow, either we lose invalidation (which opens security holes) or we\n> somehow put back-pressure on the interconnect (no idea how feasible this\n> is, I suspect really hard).\n> \n> Solving the last one is also quite difficult in software, but at least we\n> can still invalidate a range. In hardware we would invalidate the ATC\n> page-by-page and quickly jam the bus.\n> \n\nSpeak to the invalidation, I have one more question.\n\nThere is a time window between 1) modify page table; 2) tlb invalidate;\n\nARM-CPU Device\n\n1. modify page table\n\n ^^^^^\n Can still write data through smmu tlb even page table was already modified.\n (At this point, the same virtual addr may not point to the same thing for CPU and device!!!\n I'm afraid there may be some data-loss or other potential problems if this situation happens.)\n\n2. tlb invalidate range\n\n--\nThanks,\nBob\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xnkC15044z9s8J\n\tfor ;\n\tThu, 7 Sep 2017 11:58:53 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752063AbdIGB6u (ORCPT\n\t);\n\tWed, 6 Sep 2017 21:58:50 -0400","from szxga05-in.huawei.com ([45.249.212.191]:5566 \"EHLO\n\tszxga05-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751287AbdIGB6t (ORCPT\n\t); Wed, 6 Sep 2017 21:58:49 -0400","from 172.30.72.59 (EHLO DGGEMS407-HUB.china.huawei.com)\n\t([172.30.72.59])\n\tby dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DGT01547; Thu, 07 Sep 2017 09:58:20 +0800 (CST)","from [127.0.0.1] (10.142.83.150) by DGGEMS407-HUB.china.huawei.com\n\t(10.3.19.207) with Microsoft SMTP Server id 14.3.301.0;\n\tThu, 7 Sep 2017 09:58:07 +0800"],"Subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","To":"Jean-Philippe Brucker ,\n\tYisheng Xie ","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>\n\t<95d1a9e2-1816-ff7d-9a8d-98406a6c2c22@arm.com>\n\t\n\t","CC":", , ,\n\t, ,\n\t, , ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ","From":"Bob Liu ","Message-ID":"<8e4764f5-0e5d-7fd6-529b-35914e1e3668@huawei.com>","Date":"Thu, 7 Sep 2017 09:55:49 +0800","User-Agent":"Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101\n\tThunderbird/45.8.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","X-Originating-IP":"[10.142.83.150]","X-CFilter-Loop":"Reflected","X-Mirapoint-Virus-RAPID-Raw":"score=unknown(0),\n\trefid=str=0001.0A020201.59B0A7BD.00D2, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32","X-Mirapoint-Loop-Id":"d7765235516df6b4b4b943d0efef56cd","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1764815,"web_url":"http://patchwork.ozlabs.org/comment/1764815/","msgid":"<24e7e405-ad4a-4847-6177-987966182cbd@arm.com>","list_archive_url":null,"date":"2017-09-07T16:30:37","subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","submitter":{"id":68357,"url":"http://patchwork.ozlabs.org/api/people/68357/","name":"Jean-Philippe Brucker","email":"Jean-Philippe.Brucker@arm.com"},"content":"On 07/09/17 02:55, Bob Liu wrote:\n> Speak to the invalidation, I have one more question.\n> \n> There is a time window between 1) modify page table; 2) tlb invalidate;\n> \n> ARM-CPU Device\n> \n> 1. modify page table\n> \n> ^^^^^\n> Can still write data through smmu tlb even page table was already modified.\n> (At this point, the same virtual addr may not point to the same thing for CPU and device!!!\n> I'm afraid there may be some data-loss or other potential problems if this situation happens.)\n> \n> 2. tlb invalidate range\n\nThe mm code serializes map/unmap operations with mm->mmap_sem, and at a\nlower level I think the pte lock is used to prevent more subtle races.\nDon't take my word for it though, mm/ is still very obscure to me. So the\nkernel shouldn't be able to reuse the VA for something else before the tlb\ninvalidation completes. Even if you're using the CMDQ to invalidate\ninstead of TLBI instructions, you're still called by a notifier from the\nmm code so there is no problem.\n\nThanks,\nJean\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xp5TF5Pg8z9t2R\n\tfor ;\n\tFri, 8 Sep 2017 02:27:29 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S932365AbdIGQ1Q (ORCPT );\n\tThu, 7 Sep 2017 12:27:16 -0400","from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:60986 \"EHLO\n\tfoss.arm.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S932373AbdIGQ1O (ORCPT );\n\tThu, 7 Sep 2017 12:27:14 -0400","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 42D3515AD;\n\tThu, 7 Sep 2017 09:27:14 -0700 (PDT)","from [10.1.211.72] (e106794-lin.cambridge.arm.com [10.1.211.72])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\tC34343F483; Thu, 7 Sep 2017 09:27:10 -0700 (PDT)"],"Subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","To":"Bob Liu , Yisheng Xie ","Cc":"joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com,\n\tlorenzo.pieralisi@arm.com, hanjun.guo@linaro.org,\n\tsudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org,\n\twill.deacon@arm.com, robin.murphy@arm.com, robert.moore@intel.com,\n\tlv.zheng@intel.com, iommu@lists.linux-foundation.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tdevel@acpica.org, chenjiankang1@huawei.com, xieyisheng@huawei.com","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>\n\t<95d1a9e2-1816-ff7d-9a8d-98406a6c2c22@arm.com>\n\t\n\t\n\t<8e4764f5-0e5d-7fd6-529b-35914e1e3668@huawei.com>","From":"Jean-Philippe Brucker ","Message-ID":"<24e7e405-ad4a-4847-6177-987966182cbd@arm.com>","Date":"Thu, 7 Sep 2017 17:30:37 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<8e4764f5-0e5d-7fd6-529b-35914e1e3668@huawei.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1764817,"web_url":"http://patchwork.ozlabs.org/comment/1764817/","msgid":"","list_archive_url":null,"date":"2017-09-07T16:32:13","subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","submitter":{"id":68357,"url":"http://patchwork.ozlabs.org/api/people/68357/","name":"Jean-Philippe Brucker","email":"Jean-Philippe.Brucker@arm.com"},"content":"On 07/09/17 02:41, Bob Liu wrote:\n>> This would require some work in moving the PCI bits at the end of the\n>> series. I can reserve some time in the coming months to do it, but I need\n>> to know what to focus on. Are you able to test SSID as well?\n>>\n> \n> Yes, but the difficulty is our devices are on-chip integrated hardware accelerators which requires complicate driver.\n> You may need much time to understand the driver.\n> That's the same case as intel/amd SVM, the current user is their GPU :-(\n> \n> Btw, what kind of device/method do you think is ideal for testing arm-SVM?\n\nA simple, bare DMA engine would be ideal. Something just capable of\nperforming memcpy with parameters (PASID, input IOVA, output IOVA, size)\ncan be used for validating SVM and virtualization. You could easily create\nreproducible unit tests and userspace drivers. If it supports isolated\nchannels (as in SR-IOV), even better.\n\nAs you said, having a useful device like a full GPU/accelerator as opposed\nto a dummy validation engine makes it difficult to fully test the SMMU.\nHowever it can be helpful for evaluating driver performances and is still\ngood enough for confirming that the IOMMU works.\n\nThanks,\nJean\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xp5Vr6Bfvz9t2R\n\tfor ;\n\tFri, 8 Sep 2017 02:28:52 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S932271AbdIGQ2v (ORCPT );\n\tThu, 7 Sep 2017 12:28:51 -0400","from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:32800 \"EHLO\n\tfoss.arm.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S932105AbdIGQ2u (ORCPT );\n\tThu, 7 Sep 2017 12:28:50 -0400","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 47E2615AD;\n\tThu, 7 Sep 2017 09:28:50 -0700 (PDT)","from [10.1.211.72] (e106794-lin.cambridge.arm.com [10.1.211.72])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\tD3DCB3F483; Thu, 7 Sep 2017 09:28:46 -0700 (PDT)"],"From":"Jean-Philippe Brucker ","Subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","To":"Bob Liu , Yisheng Xie ","Cc":"joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com,\n\tlorenzo.pieralisi@arm.com, hanjun.guo@linaro.org,\n\tsudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org,\n\twill.deacon@arm.com, robin.murphy@arm.com, robert.moore@intel.com,\n\tlv.zheng@intel.com, iommu@lists.linux-foundation.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tdevel@acpica.org, chenjiankang1@huawei.com, xieyisheng@huawei.com","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>\n\t<95d1a9e2-1816-ff7d-9a8d-98406a6c2c22@arm.com>\n\t\n\t<2874a1f3-22f1-20d4-4009-50add127a10f@arm.com>\n\t<1d358989-48bb-ccde-d7d9-36e004bc2d78@huawei.com>","Message-ID":"","Date":"Thu, 7 Sep 2017 17:32:13 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<1d358989-48bb-ccde-d7d9-36e004bc2d78@huawei.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1767444,"web_url":"http://patchwork.ozlabs.org/comment/1767444/","msgid":"<9d7083a7-fc67-26a3-0d3d-f1a5a4942eaf@huawei.com>","list_archive_url":null,"date":"2017-09-13T01:11:03","subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","submitter":{"id":72301,"url":"http://patchwork.ozlabs.org/api/people/72301/","name":"Bob Liu","email":"liubo95@huawei.com"},"content":"On 2017/9/6 17:57, Jean-Philippe Brucker wrote:\n> On 06/09/17 02:02, Bob Liu wrote:\n>> On 2017/9/5 20:56, Jean-Philippe Brucker wrote:\n>>> On 31/08/17 09:20, Yisheng Xie wrote:\n>>>> Jean-Philippe has post a patchset for Adding PCIe SVM support to ARM SMMUv3:\n>>>> https://www.spinics.net/lists/arm-kernel/msg565155.html\n>>>>\n>>>> But for some platform devices(aka on-chip integrated devices), there is also\n>>>> SVM requirement, which works based on the SMMU stall mode.\n>>>> Jean-Philippe has prepared a prototype patchset to support it:\n>>>> git://linux-arm.org/linux-jpb.git svm/stall\n>>>\n>>> Only meant for testing at that point, and unfit even for an RFC.\n>>>\n>>\n>> Sorry for the misunderstanding.\n>> The PRI mode patches is in RFC even no hardware for testing, so I thought it's fine for \"Stall mode\" patches sent as RFC.\n>> We have tested the Stall mode on our platform.\n>> Anyway, I should confirm with you in advance.\n>>\n>> Btw, Would you consider the \"stall mode\" upstream at first? Since there is no hardware for testing the PRI mode.\n>> (We can provide you the hardware which support SMMU stall mode if necessary.)\n> \n> Yes. What's blocking the ATS, PRI and PASID patches at the moment is the\n> lack of endpoints for testing. There has been lots of discussion on the\n> API side since my first RFC and I'd like to resubmit the API changes soon.\n> It is the same API for ATS+PRI+PASID and SSID+Stall, so the backend\n> doesn't matter.\n> \n> I'm considering upstreaming SSID+Stall first if it can be tested on\n> hardware (having direct access to it would certainly speed things up).\n> This would require some work in moving the PCI bits at the end of the\n> series. I can reserve some time in the coming months to do it, but I need\n> to know what to focus on. Are you able to test SSID as well?\n> \n\nUpdate:\nOur current platform device has only one SSID register, so that have to do manually \nswitch(write different ssid to that register) if want to use by different processes.\n\nBut we're going to have an new platform who's platform device can support multi ssid.\n\nRegards,\nBob\n\n>>>> We tested this patchset with some fixes on a on-chip integrated device. The\n>>>> basic function is ok, so I just send them out for review, although this\n>>>> patchset heavily depends on the former patchset (PCIe SVM support for ARM\n>>>> SMMUv3), which is still under discussion.\n>>>>\n>>>> Patch Overview:\n>>>> *1 to 3 prepare for device tree or acpi get the device stall ability and pasid bits\n>>>> *4 is to realise the SVM function for platform device\n>>>> *5 is fix a bug when test SVM function while SMMU donnot support this feature\n>>>> *6 avoid ILLEGAL setting of STE and CD entry about stall\n>>>>\n>>>> Acctually here, I also have a question about SVM on SMMUv3:\n>>>>\n>>>> 1. Why the SVM feature on SMMUv3 depends on BTM feature? when bind a task to device,\n>>>> it will register a mmu_notify. Therefore, when a page range is invalid, we can\n>>>> send TLBI or ATC invalid without BTM?\n>>>\n>>> We could, but the end goal for SVM is to perfectly mirror the CPU page\n>>> tables. So for platform SVM we would like to get rid of MMU notifiers\n>>> entirely.\n>>>\n>>>> 2. According to ACPI IORT spec, named component specific data has a node flags field\n>>>> whoes bit0 is for Stall support. However, it do not have any field for pasid bit.\n>>>> Can we use other 5 bits[5:1] for pasid bit numbers, so we can have 32 pasid bit for\n>>>> a single platform device which should be enough, because SMMU only support 20 bit pasid\n>>>>\n>>\n>> Any comment on this?\n>> The ACPI IORT spec may need be updated?\n> \n> I suppose that the Named Component Node could be used for SSID and stall\n> capability bits. Can't the ACPI namespace entries be extended to host\n> these capabilities in a more generic way? Platforms with different IOMMUs\n> might also need this information some day.\n> \n\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xsNtV6HfWz9t4X\n\tfor ;\n\tWed, 13 Sep 2017 11:12:18 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751435AbdIMBMJ (ORCPT\n\t);\n\tTue, 12 Sep 2017 21:12:09 -0400","from szxga04-in.huawei.com ([45.249.212.190]:6460 \"EHLO\n\tszxga04-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751105AbdIMBMI (ORCPT\n\t); Tue, 12 Sep 2017 21:12:08 -0400","from 172.30.72.59 (EHLO DGGEMS410-HUB.china.huawei.com)\n\t([172.30.72.59])\n\tby dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DHC62917; Wed, 13 Sep 2017 09:11:43 +0800 (CST)","from [127.0.0.1] (10.142.83.150) by DGGEMS410-HUB.china.huawei.com\n\t(10.3.19.210) with Microsoft SMTP Server id 14.3.301.0;\n\tWed, 13 Sep 2017 09:11:31 +0800"],"Subject":"Re: [RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","To":"Jean-Philippe Brucker ,\n\tYisheng Xie ","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>\n\t<95d1a9e2-1816-ff7d-9a8d-98406a6c2c22@arm.com>\n\t\n\t<2874a1f3-22f1-20d4-4009-50add127a10f@arm.com>","CC":", , ,\n\t, ,\n\t, , ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ","From":"Bob Liu ","Message-ID":"<9d7083a7-fc67-26a3-0d3d-f1a5a4942eaf@huawei.com>","Date":"Wed, 13 Sep 2017 09:11:03 +0800","User-Agent":"Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101\n\tThunderbird/45.8.0","MIME-Version":"1.0","In-Reply-To":"<2874a1f3-22f1-20d4-4009-50add127a10f@arm.com>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","X-Originating-IP":"[10.142.83.150]","X-CFilter-Loop":"Reflected","X-Mirapoint-Virus-RAPID-Raw":"score=unknown(0),\n\trefid=str=0001.0A020206.59B885D1.0080, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32","X-Mirapoint-Loop-Id":"1fbf0095867358040b476e1df2032556","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1767521,"web_url":"http://patchwork.ozlabs.org/comment/1767521/","msgid":"<20170913030643.GD12411@arm.com>","list_archive_url":null,"date":"2017-09-13T03:06:44","subject":"Re: [RFC PATCH 6/6] iommu/arm-smmu-v3: Avoid ILLEGAL setting of\n\tSTE.S1STALLD and CD.S","submitter":{"id":7916,"url":"http://patchwork.ozlabs.org/api/people/7916/","name":"Will Deacon","email":"will.deacon@arm.com"},"content":"On Tue, Sep 05, 2017 at 01:54:19PM +0100, Jean-Philippe Brucker wrote:\n> On 31/08/17 09:20, Yisheng Xie wrote:\n> > It is ILLEGAL to set STE.S1STALLD if STALL_MODEL is not 0b00, which\n> > means we should not disable stall mode if stall/terminate mode is not\n> > configuable.\n> > \n> > Meanwhile, it is also ILLEGAL when STALL_MODEL==0b10 && CD.S==0 which\n> > means if stall mode is force we should always set CD.S.\n> > \n> > This patch add ARM_SMMU_FEAT_TERMINATE feature bit for smmu, and use\n> > TERMINATE feature checking to ensue above ILLEGAL cases from happening.\n> > \n> > Signed-off-by: Yisheng Xie \n> > ---\n> > drivers/iommu/arm-smmu-v3.c | 22 ++++++++++++++++------\n> > 1 file changed, 16 insertions(+), 6 deletions(-)\n> > \n> > diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c\n> > index dbda2eb..0745522 100644\n> > --- a/drivers/iommu/arm-smmu-v3.c\n> > +++ b/drivers/iommu/arm-smmu-v3.c\n> > @@ -55,6 +55,7 @@\n> > #define IDR0_STALL_MODEL_SHIFT\t\t24\n> > #define IDR0_STALL_MODEL_MASK\t\t0x3\n> > #define IDR0_STALL_MODEL_STALL\t\t(0 << IDR0_STALL_MODEL_SHIFT)\n> > +#define IDR0_STALL_MODEL_NS\t\t(1 << IDR0_STALL_MODEL_SHIFT)\n> > #define IDR0_STALL_MODEL_FORCE\t\t(2 << IDR0_STALL_MODEL_SHIFT)\n> > #define IDR0_TTENDIAN_SHIFT\t\t21\n> > #define IDR0_TTENDIAN_MASK\t\t0x3\n> > @@ -766,6 +767,7 @@ struct arm_smmu_device {\n> > #define ARM_SMMU_FEAT_SVM\t\t(1 << 15)\n> > #define ARM_SMMU_FEAT_HA\t\t(1 << 16)\n> > #define ARM_SMMU_FEAT_HD\t\t(1 << 17)\n> > +#define ARM_SMMU_FEAT_TERMINATE\t\t(1 << 18)\n> \n> I'd rather introduce something like \"ARM_SMMU_FEAT_STALL_FORCE\" instead.\n> Terminate model has another meaning, and is defined by a different bit in\n> IDR0.\n\nYes. What we need to do is:\n\n- If STALL_MODEL is 0b00, then set S1STALLD\n- If STALL_MODEL is 0b01, then we're ok (in future, avoiding trying to use\n stalls, even for masters that claim to support it)\n- If STALL_MODEL is 0b10, then force all PCI devices and any platform\n devices that don't claim to support stalls into bypass (depending on\n disable_bypass).\n\nReasonable? We could actually knock up a fix for mainline to do most of\nthis already.\n\nWill\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xsRQk31RZz9sPk\n\tfor ;\n\tWed, 13 Sep 2017 13:06:54 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751439AbdIMDGg (ORCPT\n\t);\n\tTue, 12 Sep 2017 23:06:36 -0400","from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:47448 \"EHLO\n\tfoss.arm.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751118AbdIMDGf (ORCPT );\n\tTue, 12 Sep 2017 23:06:35 -0400","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3D14B1596;\n\tTue, 12 Sep 2017 20:06:35 -0700 (PDT)","from edgewater-inn.cambridge.arm.com\n\t(usa-sjc-imap-foss1.foss.arm.com [10.72.51.249])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id\n\t0A3073F483; Tue, 12 Sep 2017 20:06:35 -0700 (PDT)","by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000)\n\tid 7AC791AE37A8; Wed, 13 Sep 2017 04:06:44 +0100 (BST)"],"Date":"Wed, 13 Sep 2017 04:06:44 +0100","From":"Will Deacon ","To":"Jean-Philippe Brucker ","Cc":"Yisheng Xie , joro@8bytes.org,\n\trobh+dt@kernel.org, mark.rutland@arm.com,\n\tlorenzo.pieralisi@arm.com, hanjun.guo@linaro.org,\n\tsudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org,\n\trobin.murphy@arm.com, robert.moore@intel.com, lv.zheng@intel.com,\n\tiommu@lists.linux-foundation.org, devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, devel@acpica.org,\n\tliubo95@huawei.com, chenjiankang1@huawei.com, xieyisheng@huawei.com","Subject":"Re: [RFC PATCH 6/6] iommu/arm-smmu-v3: Avoid ILLEGAL setting of\n\tSTE.S1STALLD and CD.S","Message-ID":"<20170913030643.GD12411@arm.com>","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>\n\t<1504167642-14922-7-git-send-email-xieyisheng1@huawei.com>\n\t<738977bb-4cd7-7d86-0ea0-0c88b6af721c@arm.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<738977bb-4cd7-7d86-0ea0-0c88b6af721c@arm.com>","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1767757,"web_url":"http://patchwork.ozlabs.org/comment/1767757/","msgid":"<2f952821-afc3-46dd-17eb-40e8626bd6e5@huawei.com>","list_archive_url":null,"date":"2017-09-13T10:11:13","subject":"Re: [RFC PATCH 6/6] iommu/arm-smmu-v3: Avoid ILLEGAL setting of\n\tSTE.S1STALLD and CD.S","submitter":{"id":72263,"url":"http://patchwork.ozlabs.org/api/people/72263/","name":"Yisheng Xie","email":"xieyisheng1@huawei.com"},"content":"Hi Will,\n\nOn 2017/9/13 11:06, Will Deacon wrote:\n> On Tue, Sep 05, 2017 at 01:54:19PM +0100, Jean-Philippe Brucker wrote:\n>> On 31/08/17 09:20, Yisheng Xie wrote:\n>>> It is ILLEGAL to set STE.S1STALLD if STALL_MODEL is not 0b00, which\n>>> means we should not disable stall mode if stall/terminate mode is not\n>>> configuable.\n>>>\n>>> Meanwhile, it is also ILLEGAL when STALL_MODEL==0b10 && CD.S==0 which\n>>> means if stall mode is force we should always set CD.S.\n>>>\n>>> This patch add ARM_SMMU_FEAT_TERMINATE feature bit for smmu, and use\n>>> TERMINATE feature checking to ensue above ILLEGAL cases from happening.\n>>>\n>>> Signed-off-by: Yisheng Xie \n>>> ---\n>>> drivers/iommu/arm-smmu-v3.c | 22 ++++++++++++++++------\n>>> 1 file changed, 16 insertions(+), 6 deletions(-)\n>>>\n>>> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c\n>>> index dbda2eb..0745522 100644\n>>> --- a/drivers/iommu/arm-smmu-v3.c\n>>> +++ b/drivers/iommu/arm-smmu-v3.c\n>>> @@ -55,6 +55,7 @@\n>>> #define IDR0_STALL_MODEL_SHIFT\t\t24\n>>> #define IDR0_STALL_MODEL_MASK\t\t0x3\n>>> #define IDR0_STALL_MODEL_STALL\t\t(0 << IDR0_STALL_MODEL_SHIFT)\n>>> +#define IDR0_STALL_MODEL_NS\t\t(1 << IDR0_STALL_MODEL_SHIFT)\n>>> #define IDR0_STALL_MODEL_FORCE\t\t(2 << IDR0_STALL_MODEL_SHIFT)\n>>> #define IDR0_TTENDIAN_SHIFT\t\t21\n>>> #define IDR0_TTENDIAN_MASK\t\t0x3\n>>> @@ -766,6 +767,7 @@ struct arm_smmu_device {\n>>> #define ARM_SMMU_FEAT_SVM\t\t(1 << 15)\n>>> #define ARM_SMMU_FEAT_HA\t\t(1 << 16)\n>>> #define ARM_SMMU_FEAT_HD\t\t(1 << 17)\n>>> +#define ARM_SMMU_FEAT_TERMINATE\t\t(1 << 18)\n>>\n>> I'd rather introduce something like \"ARM_SMMU_FEAT_STALL_FORCE\" instead.\n>> Terminate model has another meaning, and is defined by a different bit in\n>> IDR0.\n> \n> Yes. What we need to do is:\n> \n> - If STALL_MODEL is 0b00, then set S1STALLD\n\nYes, and within this case, we can only set the S1STALLD for masters which can\nnot stall in the future?\n\n> - If STALL_MODEL is 0b01, then we're ok (in future, avoiding trying to use\n> stalls, even for masters that claim to support it)\n> - If STALL_MODEL is 0b10, then force all PCI devices and any platform\n> devices that don't claim to support stalls into bypass (depending on\n> disable_bypass).\n> \n> Reasonable? We could actually knock up a fix for mainline to do most of\n> this already.\nThis sound reasonable to me. And I can be a volunteer to prepare this patch if\nJean-Philippe do not oppose :)\n\nThanks\nYisheng Xie\n\n> \n> Will\n> \n> .\n> \n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xscvp0kcZz9sBW\n\tfor ;\n\tWed, 13 Sep 2017 20:14:14 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751671AbdIMKN7 (ORCPT\n\t);\n\tWed, 13 Sep 2017 06:13:59 -0400","from szxga04-in.huawei.com ([45.249.212.190]:6467 \"EHLO\n\tszxga04-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751444AbdIMKN6 (ORCPT\n\t); Wed, 13 Sep 2017 06:13:58 -0400","from 172.30.72.59 (EHLO DGGEMS414-HUB.china.huawei.com)\n\t([172.30.72.59])\n\tby dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DHD39825; Wed, 13 Sep 2017 18:11:27 +0800 (CST)","from [127.0.0.1] (10.177.29.40) by DGGEMS414-HUB.china.huawei.com\n\t(10.3.19.214) with Microsoft SMTP Server id 14.3.301.0;\n\tWed, 13 Sep 2017 18:11:18 +0800"],"From":"Yisheng Xie ","Subject":"Re: [RFC PATCH 6/6] iommu/arm-smmu-v3: Avoid ILLEGAL setting of\n\tSTE.S1STALLD and CD.S","To":"Will Deacon ,\n\tJean-Philippe Brucker ","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>\n\t<1504167642-14922-7-git-send-email-xieyisheng1@huawei.com>\n\t<738977bb-4cd7-7d86-0ea0-0c88b6af721c@arm.com>\n\t<20170913030643.GD12411@arm.com>","CC":", , ,\n\t, ,\n\t, , ,\n\t, ,\n\t, ,\n\t, ,\n\t,\n\t, ,\n\t, ,\n\t","Message-ID":"<2f952821-afc3-46dd-17eb-40e8626bd6e5@huawei.com>","Date":"Wed, 13 Sep 2017 18:11:13 +0800","User-Agent":"Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101\n\tThunderbird/45.1.0","MIME-Version":"1.0","In-Reply-To":"<20170913030643.GD12411@arm.com>","Content-Type":"text/plain; charset=\"windows-1252\"","Content-Transfer-Encoding":"7bit","X-Originating-IP":"[10.177.29.40]","X-CFilter-Loop":"Reflected","X-Mirapoint-Virus-RAPID-Raw":"score=unknown(0),\n\trefid=str=0001.0A090202.59B90450.002D, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32","X-Mirapoint-Loop-Id":"eaac97f5f94b6b047243d4909bd1c3ff","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1767977,"web_url":"http://patchwork.ozlabs.org/comment/1767977/","msgid":"","list_archive_url":null,"date":"2017-09-13T15:47:27","subject":"Re: [RFC PATCH 6/6] iommu/arm-smmu-v3: Avoid ILLEGAL setting of\n\tSTE.S1STALLD and CD.S","submitter":{"id":68357,"url":"http://patchwork.ozlabs.org/api/people/68357/","name":"Jean-Philippe Brucker","email":"Jean-Philippe.Brucker@arm.com"},"content":"On 13/09/17 11:11, Yisheng Xie wrote:\n> Hi Will,\n> \n> On 2017/9/13 11:06, Will Deacon wrote:\n>> On Tue, Sep 05, 2017 at 01:54:19PM +0100, Jean-Philippe Brucker wrote:\n>>> On 31/08/17 09:20, Yisheng Xie wrote:\n>>>> It is ILLEGAL to set STE.S1STALLD if STALL_MODEL is not 0b00, which\n>>>> means we should not disable stall mode if stall/terminate mode is not\n>>>> configuable.\n>>>>\n>>>> Meanwhile, it is also ILLEGAL when STALL_MODEL==0b10 && CD.S==0 which\n>>>> means if stall mode is force we should always set CD.S.\n>>>>\n>>>> This patch add ARM_SMMU_FEAT_TERMINATE feature bit for smmu, and use\n>>>> TERMINATE feature checking to ensue above ILLEGAL cases from happening.\n>>>>\n>>>> Signed-off-by: Yisheng Xie \n>>>> ---\n>>>>  drivers/iommu/arm-smmu-v3.c | 22 ++++++++++++++++------\n>>>>  1 file changed, 16 insertions(+), 6 deletions(-)\n>>>>\n>>>> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c\n>>>> index dbda2eb..0745522 100644\n>>>> --- a/drivers/iommu/arm-smmu-v3.c\n>>>> +++ b/drivers/iommu/arm-smmu-v3.c\n>>>> @@ -55,6 +55,7 @@\n>>>>  #define IDR0_STALL_MODEL_SHIFT             24\n>>>>  #define IDR0_STALL_MODEL_MASK              0x3\n>>>>  #define IDR0_STALL_MODEL_STALL             (0 << IDR0_STALL_MODEL_SHIFT)\n>>>> +#define IDR0_STALL_MODEL_NS                (1 << IDR0_STALL_MODEL_SHIFT)\n>>>>  #define IDR0_STALL_MODEL_FORCE             (2 << IDR0_STALL_MODEL_SHIFT)\n>>>>  #define IDR0_TTENDIAN_SHIFT                21\n>>>>  #define IDR0_TTENDIAN_MASK         0x3\n>>>> @@ -766,6 +767,7 @@ struct arm_smmu_device {\n>>>>  #define ARM_SMMU_FEAT_SVM          (1 << 15)\n>>>>  #define ARM_SMMU_FEAT_HA           (1 << 16)\n>>>>  #define ARM_SMMU_FEAT_HD           (1 << 17)\n>>>> +#define ARM_SMMU_FEAT_TERMINATE            (1 << 18)\n>>>\n>>> I'd rather introduce something like \"ARM_SMMU_FEAT_STALL_FORCE\" instead.\n>>> Terminate model has another meaning, and is defined by a different bit in\n>>> IDR0.\n>> \n>> Yes. What we need to do is:\n>> \n>> - If STALL_MODEL is 0b00, then set S1STALLD\n> \n> Yes, and within this case, we can only set the S1STALLD for masters which can\n> not stall in the future?\n> \n>> - If STALL_MODEL is 0b01, then we're ok (in future, avoiding trying to use\n>>   stalls, even for masters that claim to support it)\n>> - If STALL_MODEL is 0b10, then force all PCI devices and any platform\n>>   devices that don't claim to support stalls into bypass (depending on\n>>   disable_bypass).\n>> \n>> Reasonable? We could actually knock up a fix for mainline to do most of\n>> this already.\n> This sound reasonable to me. And I can be a volunteer to prepare this patch if\n> Jean-Philippe do not oppose :)\n\nSure go ahead, I'll rebase the platform SVM work on top of it.\n\nThanks,\nJean\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xsmJF1Svbz9sPk\n\tfor ;\n\tThu, 14 Sep 2017 01:47:25 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751866AbdIMPrH (ORCPT\n\t);\n\tWed, 13 Sep 2017 11:47:07 -0400","from foss.arm.com ([217.140.101.70]:53002 \"EHLO foss.arm.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751860AbdIMPrD (ORCPT );\n\tWed, 13 Sep 2017 11:47:03 -0400","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 166351596;\n\tWed, 13 Sep 2017 08:47:03 -0700 (PDT)","from [172.20.189.210] (usa-sjc-mx-foss1.foss.arm.com\n\t[217.140.101.70])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\t8CF3D3F578; Wed, 13 Sep 2017 08:47:02 -0700 (PDT)"],"Subject":"Re: [RFC PATCH 6/6] iommu/arm-smmu-v3: Avoid ILLEGAL setting of\n\tSTE.S1STALLD and CD.S","To":"Yisheng Xie , Will Deacon ","Cc":"\"joro@8bytes.org\" ,\n\t\"robh+dt@kernel.org\" ,\n\tMark Rutland ,\n\tLorenzo Pieralisi ,\n\t\"hanjun.guo@linaro.org\" ,\n\tSudeep Holla ,\n\t\"rjw@rjwysocki.net\" ,\n\t\"lenb@kernel.org\" ,\n\tRobin Murphy , \n\t\"robert.moore@intel.com\" ,\n\t\"lv.zheng@intel.com\" ,\n\t\"iommu@lists.linux-foundation.org\" ,\n\t\"devicetree@vger.kernel.org\" ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\t\"linux-acpi@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"devel@acpica.org\" ,\n\t\"liubo95@huawei.com\" ,\n\t\"chenjiankang1@huawei.com\" ","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>\n\t<1504167642-14922-7-git-send-email-xieyisheng1@huawei.com>\n\t<738977bb-4cd7-7d86-0ea0-0c88b6af721c@arm.com>\n\t<20170913030643.GD12411@arm.com>\n\t<2f952821-afc3-46dd-17eb-40e8626bd6e5@huawei.com>","From":"Jean-Philippe Brucker ","Message-ID":"","Date":"Wed, 13 Sep 2017 16:47:27 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<2f952821-afc3-46dd-17eb-40e8626bd6e5@huawei.com>","Content-Type":"text/plain; charset=windows-1252","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1768037,"web_url":"http://patchwork.ozlabs.org/comment/1768037/","msgid":"<20170913171159.GB14955@arm.com>","list_archive_url":null,"date":"2017-09-13T17:11:59","subject":"Re: [RFC PATCH 6/6] iommu/arm-smmu-v3: Avoid ILLEGAL setting of\n\tSTE.S1STALLD and CD.S","submitter":{"id":7916,"url":"http://patchwork.ozlabs.org/api/people/7916/","name":"Will Deacon","email":"will.deacon@arm.com"},"content":"On Wed, Sep 13, 2017 at 06:11:13PM +0800, Yisheng Xie wrote:\n> On 2017/9/13 11:06, Will Deacon wrote:\n> > On Tue, Sep 05, 2017 at 01:54:19PM +0100, Jean-Philippe Brucker wrote:\n> >> On 31/08/17 09:20, Yisheng Xie wrote:\n> >>> It is ILLEGAL to set STE.S1STALLD if STALL_MODEL is not 0b00, which\n> >>> means we should not disable stall mode if stall/terminate mode is not\n> >>> configuable.\n> >>>\n> >>> Meanwhile, it is also ILLEGAL when STALL_MODEL==0b10 && CD.S==0 which\n> >>> means if stall mode is force we should always set CD.S.\n> >>>\n> >>> This patch add ARM_SMMU_FEAT_TERMINATE feature bit for smmu, and use\n> >>> TERMINATE feature checking to ensue above ILLEGAL cases from happening.\n> >>>\n> >>> Signed-off-by: Yisheng Xie \n> >>> ---\n> >>> drivers/iommu/arm-smmu-v3.c | 22 ++++++++++++++++------\n> >>> 1 file changed, 16 insertions(+), 6 deletions(-)\n> >>>\n> >>> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c\n> >>> index dbda2eb..0745522 100644\n> >>> --- a/drivers/iommu/arm-smmu-v3.c\n> >>> +++ b/drivers/iommu/arm-smmu-v3.c\n> >>> @@ -55,6 +55,7 @@\n> >>> #define IDR0_STALL_MODEL_SHIFT\t\t24\n> >>> #define IDR0_STALL_MODEL_MASK\t\t0x3\n> >>> #define IDR0_STALL_MODEL_STALL\t\t(0 << IDR0_STALL_MODEL_SHIFT)\n> >>> +#define IDR0_STALL_MODEL_NS\t\t(1 << IDR0_STALL_MODEL_SHIFT)\n> >>> #define IDR0_STALL_MODEL_FORCE\t\t(2 << IDR0_STALL_MODEL_SHIFT)\n> >>> #define IDR0_TTENDIAN_SHIFT\t\t21\n> >>> #define IDR0_TTENDIAN_MASK\t\t0x3\n> >>> @@ -766,6 +767,7 @@ struct arm_smmu_device {\n> >>> #define ARM_SMMU_FEAT_SVM\t\t(1 << 15)\n> >>> #define ARM_SMMU_FEAT_HA\t\t(1 << 16)\n> >>> #define ARM_SMMU_FEAT_HD\t\t(1 << 17)\n> >>> +#define ARM_SMMU_FEAT_TERMINATE\t\t(1 << 18)\n> >>\n> >> I'd rather introduce something like \"ARM_SMMU_FEAT_STALL_FORCE\" instead.\n> >> Terminate model has another meaning, and is defined by a different bit in\n> >> IDR0.\n> > \n> > Yes. What we need to do is:\n> > \n> > - If STALL_MODEL is 0b00, then set S1STALLD\n> \n> Yes, and within this case, we can only set the S1STALLD for masters which can\n> not stall in the future?\n\nYeah, something like that. I'd probably predicate it on having afault\nhandler registered too.\n\nWill\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xsp9y4W2rz9sPm\n\tfor ;\n\tThu, 14 Sep 2017 03:12:06 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751317AbdIMRLw (ORCPT\n\t);\n\tWed, 13 Sep 2017 13:11:52 -0400","from foss.arm.com ([217.140.101.70]:54512 \"EHLO foss.arm.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751054AbdIMRLu (ORCPT );\n\tWed, 13 Sep 2017 13:11:50 -0400","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 17B131435;\n\tWed, 13 Sep 2017 10:11:50 -0700 (PDT)","from edgewater-inn.cambridge.arm.com\n\t(usa-sjc-imap-foss1.foss.arm.com [10.72.51.249])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id\n\tD90C13F483; Wed, 13 Sep 2017 10:11:49 -0700 (PDT)","by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000)\n\tid 871231AE0DCE; Wed, 13 Sep 2017 18:11:59 +0100 (BST)"],"Date":"Wed, 13 Sep 2017 18:11:59 +0100","From":"Will Deacon ","To":"Yisheng Xie ","Cc":"Jean-Philippe Brucker ,\n\tjoro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com,\n\tlorenzo.pieralisi@arm.com, hanjun.guo@linaro.org,\n\tsudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org,\n\trobin.murphy@arm.com, robert.moore@intel.com, lv.zheng@intel.com,\n\tiommu@lists.linux-foundation.org, devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, devel@acpica.org,\n\tliubo95@huawei.com, chenjiankang1@huawei.com","Subject":"Re: [RFC PATCH 6/6] iommu/arm-smmu-v3: Avoid ILLEGAL setting of\n\tSTE.S1STALLD and CD.S","Message-ID":"<20170913171159.GB14955@arm.com>","References":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>\n\t<1504167642-14922-7-git-send-email-xieyisheng1@huawei.com>\n\t<738977bb-4cd7-7d86-0ea0-0c88b6af721c@arm.com>\n\t<20170913030643.GD12411@arm.com>\n\t<2f952821-afc3-46dd-17eb-40e8626bd6e5@huawei.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<2f952821-afc3-46dd-17eb-40e8626bd6e5@huawei.com>","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]