[{"id":1760244,"web_url":"http://patchwork.ozlabs.org/comment/1760244/","msgid":"<20170830084012.19d91759@w520.home>","list_archive_url":null,"date":"2017-08-30T14:40:12","subject":"Re: [PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root\n\tports","submitter":{"id":4123,"url":"http://patchwork.ozlabs.org/api/people/4123/","name":"Alex Williamson","email":"alex.williamson@redhat.com"},"content":"On Wed, 30 Aug 2017 16:24:54 +0200\nJan Glauber wrote:\n\n> Root ports of cn8xxx do not function after a slot reset when used with\n> some e1000e and LSI HBA devices. Add a quirk to prevent slot reset on\n> these root ports.\n> \n> Signed-off-by: Jan Glauber \n> ---\n> drivers/pci/quirks.c | 16 ++++++++++++++++\n> 1 file changed, 16 insertions(+)\n> \n> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\n> index 85191b8..6679971 100644\n> --- a/drivers/pci/quirks.c\n> +++ b/drivers/pci/quirks.c\n> @@ -845,6 +845,22 @@ static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)\n> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);\n> #endif\n> \n> +/*\n> + * Root port on some Cavium CN8xxx chips do not successfully complete\n> + * a bus reset when used with certain types of child devices. Config\n> + * space access to the child may quit responding. Flag all devices under\n> + * the secondary bus as non-resettable.\n> + */\n> +static void quirk_CN8xxx_secondary_bus(struct pci_dev *dev)\n> +{\n> +\tstruct pci_dev *pdev;\n> +\n> +\tdev_warn(&dev->dev, \"Cavium CN8xxx quirk detected; reset for devices on secondary bus disabled\\n\");\n> +\tlist_for_each_entry(pdev, &dev->subordinate->devices, bus_list)\n> +\t\tpdev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;\n> +}\n> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_CN8xxx_secondary_bus);\n> +\n> /*\n> * Some settings of MMRBC can lead to data corruption so block changes.\n> * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide\n\n\nThis doesn't seem reliable, doesn't the user just need to remove and\nreprobe the slot and the device would re-appear without this flag set?\nThanks,\n\nAlex","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1760790,"web_url":"http://patchwork.ozlabs.org/comment/1760790/","msgid":"<20170831094052.GA15906@hc>","list_archive_url":null,"date":"2017-08-31T09:40:52","subject":"Re: [PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root\n\tports","submitter":{"id":68474,"url":"http://patchwork.ozlabs.org/api/people/68474/","name":"Jan Glauber","email":"jan.glauber@caviumnetworks.com"},"content":"On Wed, Aug 30, 2017 at 08:40:12AM -0600, Alex Williamson wrote:\n> On Wed, 30 Aug 2017 16:24:54 +0200\n> Jan Glauber wrote:\n> \n> > Root ports of cn8xxx do not function after a slot reset when used with\n> > some e1000e and LSI HBA devices. Add a quirk to prevent slot reset on\n> > these root ports.\n> > \n> > Signed-off-by: Jan Glauber \n> > ---\n> > drivers/pci/quirks.c | 16 ++++++++++++++++\n> > 1 file changed, 16 insertions(+)\n> > \n> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\n> > index 85191b8..6679971 100644\n> > --- a/drivers/pci/quirks.c\n> > +++ b/drivers/pci/quirks.c\n> > @@ -845,6 +845,22 @@ static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)\n> > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);\n> > #endif\n> > \n> > +/*\n> > + * Root port on some Cavium CN8xxx chips do not successfully complete\n> > + * a bus reset when used with certain types of child devices. Config\n> > + * space access to the child may quit responding. Flag all devices under\n> > + * the secondary bus as non-resettable.\n> > + */\n> > +static void quirk_CN8xxx_secondary_bus(struct pci_dev *dev)\n> > +{\n> > +\tstruct pci_dev *pdev;\n> > +\n> > +\tdev_warn(&dev->dev, \"Cavium CN8xxx quirk detected; reset for devices on secondary bus disabled\\n\");\n> > +\tlist_for_each_entry(pdev, &dev->subordinate->devices, bus_list)\n> > +\t\tpdev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;\n> > +}\n> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_CN8xxx_secondary_bus);\n> > +\n> > /*\n> > * Some settings of MMRBC can lead to data corruption so block changes.\n> > * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide\n> \n> \n> This doesn't seem reliable, doesn't the user just need to remove and\n> reprobe the slot and the device would re-appear without this flag set?\n\nNo, I tried before to disable the slot with \"echo 0 > /sys/bus/pci/slots/3/power\"\nbut that does not work as it is not supported.\n\nI'm not familiar with the quirk types, would another one be better\nsuited here (even if we don't have the problem you descibed)?\n\nthanks,\nJan\n\n\n> Thanks,\n> \n> Alex","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1761142,"web_url":"http://patchwork.ozlabs.org/comment/1761142/","msgid":"<20170831100130.5c8a922e@w520.home>","list_archive_url":null,"date":"2017-08-31T16:01:30","subject":"Re: [PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root\n\tports","submitter":{"id":4123,"url":"http://patchwork.ozlabs.org/api/people/4123/","name":"Alex Williamson","email":"alex.williamson@redhat.com"},"content":"On Thu, 31 Aug 2017 11:40:52 +0200\nJan Glauber wrote:\n\n> On Wed, Aug 30, 2017 at 08:40:12AM -0600, Alex Williamson wrote:\n> > On Wed, 30 Aug 2017 16:24:54 +0200\n> > Jan Glauber wrote:\n> > \n> > > Root ports of cn8xxx do not function after a slot reset when used with\n> > > some e1000e and LSI HBA devices. Add a quirk to prevent slot reset on\n> > > these root ports.\n> > > \n> > > Signed-off-by: Jan Glauber \n> > > ---\n> > > drivers/pci/quirks.c | 16 ++++++++++++++++\n> > > 1 file changed, 16 insertions(+)\n> > > \n> > > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\n> > > index 85191b8..6679971 100644\n> > > --- a/drivers/pci/quirks.c\n> > > +++ b/drivers/pci/quirks.c\n> > > @@ -845,6 +845,22 @@ static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)\n> > > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);\n> > > #endif\n> > > \n> > > +/*\n> > > + * Root port on some Cavium CN8xxx chips do not successfully complete\n> > > + * a bus reset when used with certain types of child devices. Config\n> > > + * space access to the child may quit responding. Flag all devices under\n> > > + * the secondary bus as non-resettable.\n> > > + */\n> > > +static void quirk_CN8xxx_secondary_bus(struct pci_dev *dev)\n> > > +{\n> > > +\tstruct pci_dev *pdev;\n> > > +\n> > > +\tdev_warn(&dev->dev, \"Cavium CN8xxx quirk detected; reset for devices on secondary bus disabled\\n\");\n> > > +\tlist_for_each_entry(pdev, &dev->subordinate->devices, bus_list)\n> > > +\t\tpdev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;\n> > > +}\n> > > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_CN8xxx_secondary_bus);\n> > > +\n> > > /*\n> > > * Some settings of MMRBC can lead to data corruption so block changes.\n> > > * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide \n> > \n> > \n> > This doesn't seem reliable, doesn't the user just need to remove and\n> > reprobe the slot and the device would re-appear without this flag set? \n> \n> No, I tried before to disable the slot with \"echo 0 > /sys/bus/pci/slots/3/power\"\n> but that does not work as it is not supported.\n> \n> I'm not familiar with the quirk types, would another one be better\n> suited here (even if we don't have the problem you descibed)?\n\nThe scenario I'm mentioning is to \"echo 1 > /sys/bus/pci/devices//remove\", then \"echo >\n/sys/bus/pci/rescan\". This would break the ordering implicit in using\na fixup defined for the root port. It seems like it'd make a lot more\nsense to add a test on the parent bridge more similar to how the bus\nreset works. It's not the subordinate devices imposing the\nno-bus-reset flag, it's the bridge device and the objects and code\nshould support and reflect that. Thanks,\n\nAlex","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"AdhbZRQ3\"; dkim-atps=neutral","ext-mx10.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx10.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=alex.williamson@redhat.com"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjnF32nbFz9sD9\n\tfor ;\n\tFri, 1 Sep 2017 02:01:59 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dnRum-0002sQ-6q; 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bh=6CGfNrd29Xq/IZtaJTJHXsbBcuepKd8ks69vs8v2F98=;\n\tb=AdhbZRQ3pb3vyY\n\tdnpOVCADOqaoIjchnuZCALGtwgY8JooLsces8kxhHaSA3Nn5EVN0vyziy6/Bbnf6YEx0JSX8FpKEp\n\tRkV8l442z4PFB3Av3aTiSI9fCHC3keWeaoP8wqhODzLBfyZLKPpopmpclrEeWPg8706eW19DI8fRh\n\takhDOZi3p1OPvApYh1X+2kXmt+NFzBdMtLXUVdcwZJ+UO76mLBBMt4aBp2N3aQBL4eVO5Xfhz/wZl\n\tN0IyP5FKdtjqeX7huq3wXX4ROySShXcZtXIlXrCZrAYPapmj7kIaduydPeXlWizTIzrGeGg3jGguB\n\tHgmL9aRYaYKOmYM4SJfQ==;","DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 87C3961490","Date":"Thu, 31 Aug 2017 10:01:30 -0600","From":"Alex Williamson ","To":"Jan Glauber ","Subject":"Re: [PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root\n\tports","Message-ID":"<20170831100130.5c8a922e@w520.home>","In-Reply-To":"<20170831094052.GA15906@hc>","References":"<20170830142454.10971-1-jglauber@cavium.com>\n\t<20170830142454.10971-4-jglauber@cavium.com>\n\t<20170830084012.19d91759@w520.home> <20170831094052.GA15906@hc>","MIME-Version":"1.0","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.15","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.39]); 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1764568,"web_url":"http://patchwork.ozlabs.org/comment/1764568/","msgid":"<20170907074904.GB13490@hc>","list_archive_url":null,"date":"2017-09-07T07:49:04","subject":"Re: [PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root\n\tports","submitter":{"id":68474,"url":"http://patchwork.ozlabs.org/api/people/68474/","name":"Jan Glauber","email":"jan.glauber@caviumnetworks.com"},"content":"On Thu, Sep 07, 2017 at 09:40:11AM +0200, Jan Glauber wrote:\n> So what if we add an additional check like:\n> \n> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c\n> index fdf65a6..389db4b 100644\n> --- a/drivers/pci/pci.c\n> +++ b/drivers/pci/pci.c\n> @@ -4389,6 +4389,9 @@ static bool pci_slot_resetable(struct pci_slot *slot)\n> {\n> struct pci_dev *dev;\n> \n> + if (slot->bus->self & PCI_DEV_FLAGS_NO_BUS_RESET)\n> + return false;\n> +\n> list_for_each_entry(dev, &slot->bus->devices, bus_list) {\n> if (!dev->slot || dev->slot != slot)\n> continue;\n\nObviously I meant:\nif (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)\n\n--Jan","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=aQRaFwI1AFTTsNksqDvBKw8GmFBjc2G3Xu9QvN73nj4=;\n\tb=j0dZVV+5CxffXdD4pz9yraLZ4f+rc9vzxgKlL6s/e77Wpg1BWkAbQwK8TwY43p9Mg3RrIyuZ5i0FMUC2iLemg1C1GVAf0dw7PjCupwL397TO46s/TZD7OT5siDMRDz9op432FrG/f6g6Avyl1+5BuEkKGM7txTAwUmWchP5E9eY="],"Date":"Thu, 7 Sep 2017 09:49:04 +0200","From":"Jan Glauber ","To":"Alex Williamson ","Subject":"Re: [PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root\n\tports","Message-ID":"<20170907074904.GB13490@hc>","References":"<20170830142454.10971-1-jglauber@cavium.com>\n\t<20170830142454.10971-4-jglauber@cavium.com>\n\t<20170830084012.19d91759@w520.home> <20170831094052.GA15906@hc>\n\t<20170831100130.5c8a922e@w520.home> <20170907074011.GA13490@hc>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<20170907074011.GA13490@hc>","User-Agent":"Mutt/1.5.21 (2010-09-15)","X-Originating-IP":"[46.223.66.108]","X-ClientProxiedBy":"VI1PR0101CA0064.eurprd01.prod.exchangelabs.com\n\t(10.169.128.160) To CY1PR07MB2585.namprd07.prod.outlook.com\n\t(10.167.16.135)","X-MS-PublicTrafficType":"Email","X-MS-Office365-Filtering-Correlation-Id":"c4f00eb1-4fbc-4a80-16e8-08d4f5c4f1c1","X-Microsoft-Antispam":"UriScan:; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1764837,"web_url":"http://patchwork.ozlabs.org/comment/1764837/","msgid":"<20170907105237.3f025280@w520.home>","list_archive_url":null,"date":"2017-09-07T16:52:37","subject":"Re: [PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root\n\tports","submitter":{"id":4123,"url":"http://patchwork.ozlabs.org/api/people/4123/","name":"Alex Williamson","email":"alex.williamson@redhat.com"},"content":"On Thu, 7 Sep 2017 09:49:04 +0200\nJan Glauber wrote:\n\n> On Thu, Sep 07, 2017 at 09:40:11AM +0200, Jan Glauber wrote:\n> > So what if we add an additional check like:\n> > \n> > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c\n> > index fdf65a6..389db4b 100644\n> > --- a/drivers/pci/pci.c\n> > +++ b/drivers/pci/pci.c\n> > @@ -4389,6 +4389,9 @@ static bool pci_slot_resetable(struct pci_slot *slot)\n> > {\n> > struct pci_dev *dev;\n> > \n> > + if (slot->bus->self & PCI_DEV_FLAGS_NO_BUS_RESET)\n> > + return false;\n> > +\n> > list_for_each_entry(dev, &slot->bus->devices, bus_list) {\n> > if (!dev->slot || dev->slot != slot)\n> > continue; \n> \n> Obviously I meant:\n> if (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)\n\nMuch better, perhaps even incorporate the bus->self check for good\nmeasure... is it possible to have a slot on a root bus? Taking\ndifferent approaches for bus vs slot reset should have been a giant red\nflag that something is wrong. Thanks,\n\nAlex","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"Q6vZsAuh\"; dkim-atps=neutral","ext-mx05.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx05.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=alex.williamson@redhat.com"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xp6361Np0z9s8J\n\tfor ;\n\tFri, 8 Sep 2017 02:53:22 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dq03K-0000f4-P1; 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