[{"id":1766812,"web_url":"http://patchwork.ozlabs.org/comment/1766812/","msgid":"<45f67de0-ba85-74b8-0dea-5b8e8a337dbe@codeaurora.org>","list_archive_url":null,"date":"2017-09-12T09:27:09","subject":"Re: [PATCH v1 0/5] mmc: sdhci-msm: Corrections to implementation of\n\tpower irq","submitter":{"id":72258,"url":"http://patchwork.ozlabs.org/api/people/72258/","name":"Vijay Viswanath","email":"vviswana@codeaurora.org"},"content":"Hi Adrian, Ulf,\n\nI have addressed the comments on previous patch series. Can you please \ntell how I should proceed from here?\n\nThanks,\nVijay\n\nOn 8/30/2017 6:21 PM, Vijay Viswanath wrote:\n> Register writes which change voltage of IO lines or turn the IO bus on/off\n> require sdhc controller to be ready before progressing further. Once a\n> register write which affects IO lines is done, the driver should wait for\n> power irq from controller. Once the irq comes, the driver should acknowledge\n> the irq by writing to power control register. If the acknowledgement is not\n> given to controller, the controller may not complete the corresponding\n> register write action and this can mess up the controller if drivers proceeds\n> without power irq completing.\n> \n> Changes since RFC:\n> \twait_for_completion_timeout replaced with wait_event_timeout when\n> \twaiting for power irq.\n> \tRemoved the spinlock within power irq handler and API which waits\n> \tfor power irq.\n> \tAdded comments to sdhci msm register write functions, warning that they\n> \tcan sleep.\n> \tSdhci msm register write functions will do a memory barrier before\n> \twriting to the register if the particular register can trigger\n> \tpower irq.\n> \tInstead of enabling SDHCI IO ACCESSORS config in arm64/defconfig, it\n> \twill be selected in mmc/host/Kconfig if the platform is MMC_SDHCI_MSM.\n> \n> \n> Sahitya Tummala (2):\n> mmc: sdhci-msm: Fix HW issue with power IRQ handling during reset\n> mmc: sdhci-msm: Add support to wait for power irq\n> \n> Subhash Jadavani (1):\n> mmc: sdhci-msm: fix issue with power irq\n> \n> Vijay Viswanath (2):\n> mmc: sdhci-msm: Add ops to do sdhc register write\n> mmc: Kconfig: Enable CONFIG_MMC_SDHCI_IO_ACCESSORS\n> \n> drivers/mmc/host/Kconfig | 1 +\n> drivers/mmc/host/sdhci-msm.c | 253 ++++++++++++++++++++++++++++++++++++++++++-\n> 2 files changed, 249 insertions(+), 5 deletions(-)\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1766871,"web_url":"http://patchwork.ozlabs.org/comment/1766871/","msgid":"<53f7f52f-0c83-3e5e-d658-f9e1acd393e0@intel.com>","list_archive_url":null,"date":"2017-09-12T10:41:05","subject":"Re: [PATCH v1 0/5] mmc: sdhci-msm: Corrections to implementation of\n\tpower irq","submitter":{"id":11091,"url":"http://patchwork.ozlabs.org/api/people/11091/","name":"Adrian Hunter","email":"adrian.hunter@intel.com"},"content":"On 12/09/17 12:27, Vijay Viswanath wrote:\n> I have addressed the comments on previous patch series. Can you please tell\n> how I should proceed from here?\n\nI will look at it soon.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"JJL18/T7\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs1jY1bfQz9s7M\n\tfor ;\n\tTue, 12 Sep 2017 20:48:17 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1drijm-0003YW-AQ; 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i=\"5.42,382,1500966000\"; d=\"scan'208\";\n\ta=\"1171420654\"","Subject":"Re: [PATCH v1 0/5] mmc: sdhci-msm: Corrections to implementation of\n\tpower irq","To":"Vijay Viswanath , ulf.hansson@linaro.org,\n\twill.deacon@arm.com","References":"<1504097509-58983-1-git-send-email-vviswana@codeaurora.org>\n\t<45f67de0-ba85-74b8-0dea-5b8e8a337dbe@codeaurora.org>","From":"Adrian Hunter ","Organization":"Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, \n\tBusiness Identity Code: 0357606 - 4, Domiciled in Helsinki","Message-ID":"<53f7f52f-0c83-3e5e-d658-f9e1acd393e0@intel.com>","Date":"Tue, 12 Sep 2017 13:41:05 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<45f67de0-ba85-74b8-0dea-5b8e8a337dbe@codeaurora.org>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170912_034810_275201_96317B3F ","X-CRM114-Status":"UNSURE ( 7.93 )","X-CRM114-Notice":"Please train this message.","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [192.55.52.88 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3)\n\t[192.55.52.88 listed in wl.mailspike.net]\n\t-0.0 RCVD_IN_MSPIKE_WL Mailspike good senders","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"riteshh@codeaurora.org, linux-arm-msm@vger.kernel.org,\n\tlinux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tstummala@codeaurora.org, subhashj@codeaurora.org,\n\tlinux-arm-kernel@lists.infradead.org, asutoshd@codeaurora.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1768354,"web_url":"http://patchwork.ozlabs.org/comment/1768354/","msgid":"<1ff495dd-cb66-f49b-ed23-6994e5ccdc0f@intel.com>","list_archive_url":null,"date":"2017-09-14T06:20:30","subject":"Re: [PATCH v1 1/5] mmc: sdhci-msm: fix issue with power irq","submitter":{"id":11091,"url":"http://patchwork.ozlabs.org/api/people/11091/","name":"Adrian Hunter","email":"adrian.hunter@intel.com"},"content":"On 30/08/17 15:51, Vijay Viswanath wrote:\n> From: Subhash Jadavani \n> \n> SDCC controller reset (SW_RST) during probe may trigger power irq if\n> previous status of PWRCTL was either BUS_ON or IO_HIGH_V. So before we\n> enable the power irq interrupt in GIC (by registering the interrupt\n> handler), we need to ensure that any pending power irq interrupt status\n> is acknowledged otherwise power irq interrupt handler would be fired\n> prematurely.\n> \n> Signed-off-by: Subhash Jadavani \n> Signed-off-by: Vijay Viswanath \n\nAcked-by: Adrian Hunter \n\n> ---\n> drivers/mmc/host/sdhci-msm.c | 18 ++++++++++++++++++\n> 1 file changed, 18 insertions(+)\n> \n> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c\n> index 9d601dc..d636251 100644\n> --- a/drivers/mmc/host/sdhci-msm.c\n> +++ b/drivers/mmc/host/sdhci-msm.c\n> @@ -1250,6 +1250,21 @@ static int sdhci_msm_probe(struct platform_device *pdev)\n> \t\t\t CORE_VENDOR_SPEC_CAPABILITIES0);\n> \t}\n> \n> +\t/*\n> +\t * Power on reset state may trigger power irq if previous status of\n> +\t * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq\n> +\t * interrupt in GIC, any pending power irq interrupt should be\n> +\t * acknowledged. Otherwise power irq interrupt handler would be\n> +\t * fired prematurely.\n> +\t */\n> +\tsdhci_msm_voltage_switch(host);\n> +\n> +\t/*\n> +\t * Ensure that above writes are propogated before interrupt enablement\n> +\t * in GIC.\n> +\t */\n> +\tmb();\n> +\n> \t/* Setup IRQ for handling power/voltage tasks with PMIC */\n> \tmsm_host->pwr_irq = platform_get_irq_byname(pdev, \"pwr_irq\");\n> \tif (msm_host->pwr_irq < 0) {\n> @@ -1259,6 +1274,9 @@ static int sdhci_msm_probe(struct platform_device *pdev)\n> \t\tgoto clk_disable;\n> \t}\n> \n> +\t/* Enable pwr irq interrupts */\n> +\twritel_relaxed(INT_MASK, msm_host->core_mem + CORE_PWRCTL_MASK);\n> +\n> \tret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,\n> \t\t\t\t\tsdhci_msm_pwr_irq, IRQF_ONESHOT,\n> \t\t\t\t\tdev_name(&pdev->dev), host);\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<1504097509-58983-2-git-send-email-vviswana@codeaurora.org>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170913_232735_440715_D296CBC1 ","X-CRM114-Status":"GOOD ( 12.85 )","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [134.134.136.20 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3)\n\t[134.134.136.20 listed in wl.mailspike.net]\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.0 RCVD_IN_MSPIKE_WL Mailspike good senders","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"riteshh@codeaurora.org, linux-arm-msm@vger.kernel.org,\n\tlinux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tstummala@codeaurora.org, subhashj@codeaurora.org,\n\tlinux-arm-kernel@lists.infradead.org, asutoshd@codeaurora.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1768355,"web_url":"http://patchwork.ozlabs.org/comment/1768355/","msgid":"<0c3e68f5-8945-9401-1078-bdee725c3c67@intel.com>","list_archive_url":null,"date":"2017-09-14T06:20:38","subject":"Re: [PATCH v1 2/5] mmc: sdhci-msm: Fix HW issue with power IRQ\n\thandling during reset","submitter":{"id":11091,"url":"http://patchwork.ozlabs.org/api/people/11091/","name":"Adrian Hunter","email":"adrian.hunter@intel.com"},"content":"On 30/08/17 15:51, Vijay Viswanath wrote:\n> From: Sahitya Tummala \n> \n> There is a rare scenario in HW, where the first clear pulse could\n> be lost when the actual reset and clear/read of status register\n> are happening at the same time. Fix this by retrying upto 10 times\n> to ensure the status register gets cleared. Otherwise, this will\n> lead to a spurious power IRQ which results in system instability.\n> \n> Signed-off-by: Sahitya Tummala \n> Signed-off-by: Vijay Viswanath \n\nAcked-by: Adrian Hunter \n\n> ---\n> drivers/mmc/host/sdhci-msm.c | 46 ++++++++++++++++++++++++++++++++++++++++----\n> 1 file changed, 42 insertions(+), 4 deletions(-)\n> \n> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c\n> index d636251..42a65ab 100644\n> --- a/drivers/mmc/host/sdhci-msm.c\n> +++ b/drivers/mmc/host/sdhci-msm.c\n> @@ -995,17 +995,52 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,\n> \t\tsdhci_msm_hs400(host, &mmc->ios);\n> }\n> \n> -static void sdhci_msm_voltage_switch(struct sdhci_host *host)\n> +static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)\n> +{\n> +\tstruct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);\n> +\tstruct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);\n> +\n> +\tpr_err(\"%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\\n\",\n> +\t\t\tmmc_hostname(host->mmc),\n> +\t\t\treadl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS),\n> +\t\t\treadl_relaxed(msm_host->core_mem + CORE_PWRCTL_MASK),\n> +\t\t\treadl_relaxed(msm_host->core_mem + CORE_PWRCTL_CTL));\n> +}\n> +\n> +static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)\n> {\n> \tstruct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);\n> \tstruct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);\n> \tu32 irq_status, irq_ack = 0;\n> +\tint retry = 10;\n> \n> \tirq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS);\n> \tirq_status &= INT_MASK;\n> \n> \twritel_relaxed(irq_status, msm_host->core_mem + CORE_PWRCTL_CLEAR);\n> \n> +\t/*\n> +\t * There is a rare HW scenario where the first clear pulse could be\n> +\t * lost when actual reset and clear/read of status register is\n> +\t * happening at a time. Hence, retry for at least 10 times to make\n> +\t * sure status register is cleared. Otherwise, this will result in\n> +\t * a spurious power IRQ resulting in system instability.\n> +\t */\n> +\twhile (irq_status & readl_relaxed(msm_host->core_mem +\n> +\t\t\t\tCORE_PWRCTL_STATUS)) {\n> +\t\tif (retry == 0) {\n> +\t\t\tpr_err(\"%s: Timedout clearing (0x%x) pwrctl status register\\n\",\n> +\t\t\t\t\tmmc_hostname(host->mmc), irq_status);\n> +\t\t\tsdhci_msm_dump_pwr_ctrl_regs(host);\n> +\t\t\tWARN_ON(1);\n> +\t\t\tbreak;\n> +\t\t}\n> +\t\twritel_relaxed(irq_status,\n> +\t\t\t\tmsm_host->core_mem + CORE_PWRCTL_CLEAR);\n> +\t\tretry--;\n> +\t\tudelay(10);\n> +\t}\n> +\n> \tif (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF))\n> \t\tirq_ack |= CORE_PWRCTL_BUS_SUCCESS;\n> \tif (irq_status & (CORE_PWRCTL_IO_LOW | CORE_PWRCTL_IO_HIGH))\n> @@ -1017,13 +1052,17 @@ static void sdhci_msm_voltage_switch(struct sdhci_host *host)\n> \t * switches are handled by the sdhci core, so just report success.\n> \t */\n> \twritel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL);\n> +\n> +\tpr_debug(\"%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\\n\",\n> +\t\tmmc_hostname(msm_host->mmc), __func__, irq, irq_status,\n> +\t\tirq_ack);\n> }\n> \n> static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)\n> {\n> \tstruct sdhci_host *host = (struct sdhci_host *)data;\n> \n> -\tsdhci_msm_voltage_switch(host);\n> +\tsdhci_msm_handle_pwr_irq(host, irq);\n> \n> \treturn IRQ_HANDLED;\n> }\n> @@ -1106,7 +1145,6 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)\n> \t.get_max_clock = sdhci_msm_get_max_clock,\n> \t.set_bus_width = sdhci_set_bus_width,\n> \t.set_uhs_signaling = sdhci_msm_set_uhs_signaling,\n> -\t.voltage_switch = sdhci_msm_voltage_switch,\n> };\n> \n> static const struct sdhci_pltfm_data sdhci_msm_pdata = {\n> @@ -1257,7 +1295,7 @@ static int sdhci_msm_probe(struct platform_device *pdev)\n> \t * acknowledged. Otherwise power irq interrupt handler would be\n> \t * fired prematurely.\n> \t */\n> -\tsdhci_msm_voltage_switch(host);\n> +\tsdhci_msm_handle_pwr_irq(host, 0);\n> \n> \t/*\n> \t * Ensure that above writes are propogated before interrupt enablement\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"Tt3jE5Hx\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xt7rM3cQwz9t1G\n\tfor ;\n\tThu, 14 Sep 2017 16:28:03 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dsNd2-0007Zu-9v; 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d=\"scan'208\";a=\"900119311\"","Subject":"Re: [PATCH v1 2/5] mmc: sdhci-msm: Fix HW issue with power IRQ\n\thandling during reset","To":"Vijay Viswanath , ulf.hansson@linaro.org,\n\twill.deacon@arm.com","References":"<1504097509-58983-1-git-send-email-vviswana@codeaurora.org>\n\t<1504097509-58983-3-git-send-email-vviswana@codeaurora.org>","From":"Adrian Hunter ","Organization":"Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, \n\tBusiness Identity Code: 0357606 - 4, Domiciled in Helsinki","Message-ID":"<0c3e68f5-8945-9401-1078-bdee725c3c67@intel.com>","Date":"Thu, 14 Sep 2017 09:20:38 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<1504097509-58983-3-git-send-email-vviswana@codeaurora.org>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170913_232741_021398_646525AF ","X-CRM114-Status":"GOOD ( 19.59 )","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [134.134.136.31 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"riteshh@codeaurora.org, linux-arm-msm@vger.kernel.org,\n\tlinux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tstummala@codeaurora.org, subhashj@codeaurora.org,\n\tlinux-arm-kernel@lists.infradead.org, asutoshd@codeaurora.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1768360,"web_url":"http://patchwork.ozlabs.org/comment/1768360/","msgid":"","list_archive_url":null,"date":"2017-09-14T06:34:23","subject":"Re: [PATCH v1 3/5] mmc: sdhci-msm: Add support to wait for power irq","submitter":{"id":11091,"url":"http://patchwork.ozlabs.org/api/people/11091/","name":"Adrian Hunter","email":"adrian.hunter@intel.com"},"content":"On 30/08/17 15:51, Vijay Viswanath wrote:\n> From: Sahitya Tummala \n> \n> Add support API which will check if power irq is expected to be\n> generated and wait for the power irq to come and complete if the irq is\n> expected.\n> \n> Signed-off-by: Sahitya Tummala \n> Signed-off-by: Vijay Viswanath \n\nOne comment below.\n\n> ---\n> drivers/mmc/host/sdhci-msm.c | 124 ++++++++++++++++++++++++++++++++++++++++++-\n> 1 file changed, 122 insertions(+), 2 deletions(-)\n> \n> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c\n> index 42a65ab..e3e385e 100644\n> --- a/drivers/mmc/host/sdhci-msm.c\n> +++ b/drivers/mmc/host/sdhci-msm.c\n> @@ -123,6 +123,10 @@\n> #define CMUX_SHIFT_PHASE_MASK\t(7 << CMUX_SHIFT_PHASE_SHIFT)\n> \n> #define MSM_MMC_AUTOSUSPEND_DELAY_MS\t50\n> +\n> +/* Timeout value to avoid infinite waiting for pwr_irq */\n> +#define MSM_PWR_IRQ_TIMEOUT_MS 5000\n> +\n> struct sdhci_msm_host {\n> \tstruct platform_device *pdev;\n> \tvoid __iomem *core_mem;\t/* MSM SDCC mapped address */\n> @@ -138,6 +142,12 @@ struct sdhci_msm_host {\n> \tbool calibration_done;\n> \tu8 saved_tuning_phase;\n> \tbool use_cdclp533;\n> +\tu32 curr_pwr_state;\n> +\tu32 curr_io_level;\n> +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS\n> +\twait_queue_head_t pwr_irq_wait;\n> +\tbool pwr_irq_flag;\n> +#endif\n> };\n> \n> static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,\n> @@ -995,6 +1005,87 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,\n> \t\tsdhci_msm_hs400(host, &mmc->ios);\n> }\n> \n> +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS\n> +static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)\n> +{\n> +\tinit_waitqueue_head(&msm_host->pwr_irq_wait);\n> +}\n> +\n> +static inline void sdhci_msm_complete_pwr_irq_wait(\n> +\t\tstruct sdhci_msm_host *msm_host)\n> +{\n> +\twake_up(&msm_host->pwr_irq_wait);\n> +}\n> +\n> +/*\n> + * sdhci_msm_check_power_status API should be called when registers writes\n> + * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.\n> + * To what state the register writes will change the IO lines should be passed\n> + * as the argument req_type. This API will check whether the IO line's state\n> + * is already the expected state and will wait for power irq only if\n> + * power irq is expected to be trigerred based on the current IO line state\n> + * and expected IO line state.\n> + */\n> +static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)\n> +{\n> +\tstruct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);\n> +\tstruct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);\n> +\tbool done = false;\n> +\n> +\tpr_debug(\"%s: %s: request %d curr_pwr_state %x curr_io_level %x\\n\",\n> +\t\t\tmmc_hostname(host->mmc), __func__, req_type,\n> +\t\t\tmsm_host->curr_pwr_state, msm_host->curr_io_level);\n> +\n> +\t/*\n> +\t * The IRQ for request type IO High/LOW will be generated when -\n> +\t * there is a state change in 1.8V enable bit (bit 3) of\n> +\t * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0\n> +\t * which indicates 3.3V IO voltage. So, when MMC core layer tries\n> +\t * to set it to 3.3V before card detection happens, the\n> +\t * IRQ doesn't get triggered as there is no state change in this bit.\n> +\t * The driver already handles this case by changing the IO voltage\n> +\t * level to high as part of controller power up sequence. Hence, check\n> +\t * for host->pwr to handle a case where IO voltage high request is\n> +\t * issued even before controller power up.\n> +\t */\n> +\tif ((req_type & REQ_IO_HIGH) && !host->pwr) {\n> +\t\tpr_debug(\"%s: do not wait for power IRQ that never comes, req_type: %d\\n\",\n> +\t\t\t\tmmc_hostname(host->mmc), req_type);\n> +\t\treturn;\n> +\t}\n> +\tif ((req_type & msm_host->curr_pwr_state) ||\n> +\t\t\t(req_type & msm_host->curr_io_level))\n> +\t\tdone = true;\n> +\t/*\n> +\t * This is needed here to hanlde a case where IRQ gets\n> +\t * triggered even before this function is called so that\n> +\t * x->done counter of completion gets reset. Otherwise,\n> +\t * next call to wait_for_completion returns immediately\n> +\t * without actually waiting for the IRQ to be handled.\n> +\t */\n\nThis isn't true anymore. If there is always an interrupt following the\nregister write, then you can always call wait_event_timeout() because\nif the interrupt has already happened msm_host->pwr_irq_flag will already be\ntrue.\n\nHowever if the interrupt only happens if the pwr_state of io_level changes,\nthen you do need to check those, to avoid waiting for an interrupt that is\nnot coming.\n\n> +\tif (!done) {\n> +\t\tif (!wait_event_timeout(msm_host->pwr_irq_wait,\n> +\t\t\t\tmsm_host->pwr_irq_flag,\n> +\t\t\t\tmsecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))\n> +\t\t\t__WARN_printf(\"%s: pwr_irq for req: (%d) timed out\\n\",\n> +\t\t\t\t\tmmc_hostname(host->mmc), req_type);\n> +\t}\n> +\tmsm_host->pwr_irq_flag = 0;\n> +\tpr_debug(\"%s: %s: request %d done\\n\", mmc_hostname(host->mmc),\n> +\t\t\t__func__, req_type);\n> +}\n> +#else\n> +static inline void sdhci_msm_init_pwr_irq_completion(\n> +\t\tstruct sdhci_msm_host *msm_host)\n> +{\n> +}\n> +\n> +static inline void sdhci_msm_complete_pwr_irq_completion(\n> +\t\tstruct sdhci_msm_host *msm_host)\n> +{\n> +}\n> +#endif\n> +\n> static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)\n> {\n> \tstruct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);\n> @@ -1013,6 +1104,8 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)\n> \tstruct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);\n> \tu32 irq_status, irq_ack = 0;\n> \tint retry = 10;\n> +\tint pwr_state = 0, io_level = 0;\n> +\n> \n> \tirq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS);\n> \tirq_status &= INT_MASK;\n> @@ -1041,10 +1134,26 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)\n> \t\tudelay(10);\n> \t}\n> \n> -\tif (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF))\n> +\t/* Handle BUS ON/OFF*/\n> +\tif (irq_status & CORE_PWRCTL_BUS_ON) {\n> +\t\tpwr_state = REQ_BUS_ON;\n> +\t\tio_level = REQ_IO_HIGH;\n> \t\tirq_ack |= CORE_PWRCTL_BUS_SUCCESS;\n> -\tif (irq_status & (CORE_PWRCTL_IO_LOW | CORE_PWRCTL_IO_HIGH))\n> +\t}\n> +\tif (irq_status & CORE_PWRCTL_BUS_OFF) {\n> +\t\tpwr_state = REQ_BUS_OFF;\n> +\t\tio_level = REQ_IO_LOW;\n> +\t\tirq_ack |= CORE_PWRCTL_BUS_SUCCESS;\n> +\t}\n> +\t/* Handle IO LOW/HIGH */\n> +\tif (irq_status & CORE_PWRCTL_IO_LOW) {\n> +\t\tio_level = REQ_IO_LOW;\n> +\t\tirq_ack |= CORE_PWRCTL_IO_SUCCESS;\n> +\t}\n> +\tif (irq_status & CORE_PWRCTL_IO_HIGH) {\n> +\t\tio_level = REQ_IO_HIGH;\n> \t\tirq_ack |= CORE_PWRCTL_IO_SUCCESS;\n> +\t}\n> \n> \t/*\n> \t * The driver has to acknowledge the interrupt, switch voltages and\n> @@ -1053,6 +1162,11 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)\n> \t */\n> \twritel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL);\n> \n> +\tif (pwr_state)\n> +\t\tmsm_host->curr_pwr_state = pwr_state;\n> +\tif (io_level)\n> +\t\tmsm_host->curr_io_level = io_level;\n> +\n> \tpr_debug(\"%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\\n\",\n> \t\tmmc_hostname(msm_host->mmc), __func__, irq, irq_status,\n> \t\tirq_ack);\n> @@ -1061,8 +1175,13 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)\n> static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)\n> {\n> \tstruct sdhci_host *host = (struct sdhci_host *)data;\n> +\tstruct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);\n> +\tstruct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);\n> \n> \tsdhci_msm_handle_pwr_irq(host, irq);\n> +\tmsm_host->pwr_irq_flag = 1;\n> +\tsdhci_msm_complete_pwr_irq_wait(msm_host);\n> +\n> \n> \treturn IRQ_HANDLED;\n> }\n> @@ -1312,6 +1431,7 @@ static int sdhci_msm_probe(struct platform_device *pdev)\n> \t\tgoto clk_disable;\n> \t}\n> \n> +\tsdhci_msm_init_pwr_irq_wait(msm_host);\n> \t/* Enable pwr irq interrupts */\n> \twritel_relaxed(INT_MASK, msm_host->core_mem + CORE_PWRCTL_MASK);\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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13 Sep 2017 23:41:00 -0700"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:\n\tMessage-ID:From:References:To:Subject:Reply-To:Content-ID:Content-Description\n\t:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=c2B6gcaR71A7zglWMYjYyzDvlLpqjHNOL6DbYenxtj8=;\n\tb=FzNt9Y9BYEJgYK\n\tDw0RXKN7vikvQpXIsUg6Fijk8kQkASHbpoV2VpUyuUcpcwdmqD3dk8YyTZd+evseXH7P99eElv9XD\n\tAdEx3X07fMok+VUKRNbvt6HKlNrkgM2vPl7Zais7ugLk6rpXa3URtnhK3qCYCTShm+gm/b3usg9PA\n\tzP5UmhZyUKx5114omR31Lf6xRSnfkbTSLbQ21STajt1DI7/1r0tsTA7hEodP0X24hXULk6TFxjJrf\n\tzdPTb2gbpzWg3yhVNeWoSmo1NWK17jObn02gdEy6VS6HCU7ztAXYZe2wvTBFO0bdKNGETnFTV6Cjm\n\tgQn4wDits8eP+Yb95shw==;","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,391,1500966000\"; d=\"scan'208\";a=\"900122809\"","Subject":"Re: [PATCH v1 3/5] mmc: sdhci-msm: Add support to wait for power irq","To":"Vijay Viswanath , ulf.hansson@linaro.org,\n\twill.deacon@arm.com","References":"<1504097509-58983-1-git-send-email-vviswana@codeaurora.org>\n\t<1504097509-58983-4-git-send-email-vviswana@codeaurora.org>","From":"Adrian Hunter ","Organization":"Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, \n\tBusiness Identity Code: 0357606 - 4, Domiciled in Helsinki","Message-ID":"","Date":"Thu, 14 Sep 2017 09:34:23 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<1504097509-58983-4-git-send-email-vviswana@codeaurora.org>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170913_234123_906044_8EBCDCE1 ","X-CRM114-Status":"GOOD ( 25.97 )","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [134.134.136.20 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3)\n\t[134.134.136.20 listed in wl.mailspike.net]\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.0 RCVD_IN_MSPIKE_WL Mailspike good senders","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"riteshh@codeaurora.org, linux-arm-msm@vger.kernel.org,\n\tlinux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tstummala@codeaurora.org, subhashj@codeaurora.org,\n\tlinux-arm-kernel@lists.infradead.org, asutoshd@codeaurora.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1768362,"web_url":"http://patchwork.ozlabs.org/comment/1768362/","msgid":"<3cfed059-0146-2eb4-35cb-d74cd96455bb@intel.com>","list_archive_url":null,"date":"2017-09-14T06:34:36","subject":"Re: [PATCH v1 4/5] mmc: sdhci-msm: Add ops to do sdhc register write","submitter":{"id":11091,"url":"http://patchwork.ozlabs.org/api/people/11091/","name":"Adrian Hunter","email":"adrian.hunter@intel.com"},"content":"On 30/08/17 15:51, Vijay Viswanath wrote:\n> Register writes which change voltage of IO lines or turn the IO bus\n> on/off require controller to be ready before progressing further. When\n> the controller is ready, it will generate a power irq which needs to be\n> handled. The thread which initiated the register write should wait for\n> power irq to complete. This will be done through the new sdhc msm write\n> APIs which will check whether the particular write can trigger a power\n> irq and wait for it with a timeout if it is expected.\n> The SDHC core power control IRQ gets triggered when -\n> * There is a state change in power control bit (bit 0)\n> of SDHCI_POWER_CONTROL register.\n> * There is a state change in 1.8V enable bit (bit 3) of\n> SDHCI_HOST_CONTROL2 register.\n> * Bit 1 of SDHCI_SOFTWARE_RESET is set.\n> \n> Signed-off-by: Vijay Viswanath \n\nAcked-by: Adrian Hunter \n\n> ---\n> drivers/mmc/host/sdhci-msm.c | 69 +++++++++++++++++++++++++++++++++++++++++++-\n> 1 file changed, 68 insertions(+), 1 deletion(-)\n> \n> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c\n> index e3e385e..a4a78b5 100644\n> --- a/drivers/mmc/host/sdhci-msm.c\n> +++ b/drivers/mmc/host/sdhci-msm.c\n> @@ -1070,7 +1070,6 @@ static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)\n> \t\t\t__WARN_printf(\"%s: pwr_irq for req: (%d) timed out\\n\",\n> \t\t\t\t\tmmc_hostname(host->mmc), req_type);\n> \t}\n> -\tmsm_host->pwr_irq_flag = 0;\n> \tpr_debug(\"%s: %s: request %d done\\n\", mmc_hostname(host->mmc),\n> \t\t\t__func__, req_type);\n> }\n> @@ -1250,6 +1249,70 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)\n> \t__sdhci_msm_set_clock(host, clock);\n> }\n> \n> +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS\n> +/*\n> + * Platform specific register write functions. This is so that, if any\n> + * register write needs to be followed up by platform specific actions,\n> + * they can be added here. These functions can go to sleep when writes\n> + * to certain registers are done.\n> + * These functions are relying on sdhci_set_ios not using spinlock.\n> + */\n> +static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)\n> +{\n> +\tstruct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);\n> +\tstruct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);\n> +\tu32 req_type = 0;\n> +\n> +\tswitch (reg) {\n> +\tcase SDHCI_HOST_CONTROL2:\n> +\t\treq_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW :\n> +\t\t\tREQ_IO_HIGH;\n> +\t\tbreak;\n> +\tcase SDHCI_SOFTWARE_RESET:\n> +\t\tif (host->pwr && (val & SDHCI_RESET_ALL))\n> +\t\t\treq_type = REQ_BUS_OFF;\n> +\t\tbreak;\n> +\tcase SDHCI_POWER_CONTROL:\n> +\t\treq_type = !val ? REQ_BUS_OFF : REQ_BUS_ON;\n> +\t\tbreak;\n> +\t}\n> +\n> +\tif (req_type) {\n> +\t\tmsm_host->pwr_irq_flag = 0;\n> +\t\t/*\n> +\t\t * Since this register write may trigger a power irq, ensure\n> +\t\t * all previous register writes are complete by this point.\n> +\t\t */\n> +\t\tmb();\n> +\t}\n> +\treturn req_type;\n> +}\n> +\n> +/* This function may sleep*/\n> +static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)\n> +{\n> +\tu32 req_type = 0;\n> +\n> +\treq_type = __sdhci_msm_check_write(host, val, reg);\n> +\twritew_relaxed(val, host->ioaddr + reg);\n> +\n> +\tif (req_type)\n> +\t\tsdhci_msm_check_power_status(host, req_type);\n> +}\n> +\n> +/* This function may sleep*/\n> +static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)\n> +{\n> +\tu32 req_type = 0;\n> +\n> +\treq_type = __sdhci_msm_check_write(host, val, reg);\n> +\n> +\twriteb_relaxed(val, host->ioaddr + reg);\n> +\n> +\tif (req_type)\n> +\t\tsdhci_msm_check_power_status(host, req_type);\n> +}\n> +#endif\n> static const struct of_device_id sdhci_msm_dt_match[] = {\n> \t{ .compatible = \"qcom,sdhci-msm-v4\" },\n> \t{},\n> @@ -1264,6 +1327,10 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)\n> \t.get_max_clock = sdhci_msm_get_max_clock,\n> \t.set_bus_width = sdhci_set_bus_width,\n> \t.set_uhs_signaling = sdhci_msm_set_uhs_signaling,\n> +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS\n> +\t.write_w = sdhci_msm_writew,\n> +\t.write_b = sdhci_msm_writeb,\n> +#endif\n> };\n> \n> static const struct sdhci_pltfm_data sdhci_msm_pdata = {\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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13 Sep 2017 23:41:13 -0700"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:\n\tMessage-ID:From:References:To:Subject:Reply-To:Content-ID:Content-Description\n\t:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=W9vsR2AC2uyQfHHG17SAuNE2iWMgqO7fWBKk45WHMWw=;\n\tb=VVV6j0JCpZh0LI\n\tgqwBvjeWiw4eJrYabTLL52iV0AzjYZuIqVT55Kpcd5Qih/k4GW15uRV3uMv+scwCsEcL+BhHLNnmr\n\t26yBmtNuE5ngbs2XHWgjPkJIeUoKuoHS02/nNMJB4EDkkZDHFFgNEgNEh3bjLFBijohXqgjZYQUgu\n\tU6jHQs0ushAKCoNofK4Jue+gAV3ffoGt0jxJyjfNbnVyJ5w6kQoKimd1xmgX6dXHNp2QMRILd4k9P\n\twkX3TAbVQPvOToSK4r38WN+MU3JpRd2dkCjyyNUOv3ZBn1FbeWvy/57jLj/itlqKeuyVEORkQ18tI\n\t/PXSUMHpDSZQwbRBzs5Q==;","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,391,1500966000\"; d=\"scan'208\";a=\"900122882\"","Subject":"Re: [PATCH v1 4/5] mmc: sdhci-msm: Add ops to do sdhc register write","To":"Vijay Viswanath , ulf.hansson@linaro.org,\n\twill.deacon@arm.com","References":"<1504097509-58983-1-git-send-email-vviswana@codeaurora.org>\n\t<1504097509-58983-5-git-send-email-vviswana@codeaurora.org>","From":"Adrian Hunter ","Organization":"Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, \n\tBusiness Identity Code: 0357606 - 4, Domiciled in Helsinki","Message-ID":"<3cfed059-0146-2eb4-35cb-d74cd96455bb@intel.com>","Date":"Thu, 14 Sep 2017 09:34:36 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<1504097509-58983-5-git-send-email-vviswana@codeaurora.org>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170913_234138_843717_93352BBC ","X-CRM114-Status":"GOOD ( 21.10 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [134.134.136.24 listed in list.dnswl.org]\n\t-0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3)\n\t[134.134.136.24 listed in wl.mailspike.net]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.0 RCVD_IN_MSPIKE_WL Mailspike good senders","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"riteshh@codeaurora.org, linux-arm-msm@vger.kernel.org,\n\tlinux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tstummala@codeaurora.org, subhashj@codeaurora.org,\n\tlinux-arm-kernel@lists.infradead.org, asutoshd@codeaurora.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1768369,"web_url":"http://patchwork.ozlabs.org/comment/1768369/","msgid":"","list_archive_url":null,"date":"2017-09-14T06:34:51","subject":"Re: [PATCH v1 5/5] mmc: Kconfig: Enable\n\tCONFIG_MMC_SDHCI_IO_ACCESSORS","submitter":{"id":11091,"url":"http://patchwork.ozlabs.org/api/people/11091/","name":"Adrian Hunter","email":"adrian.hunter@intel.com"},"content":"On 30/08/17 15:51, Vijay Viswanath wrote:\n> Enable CONFIG_MMC_SDHCI_IO_ACCESSORS so that SDHC controller specific\n> register read and write APIs, if registered, can be used.\n\nMissing signed-off\n\nWhy don't you put this patch earlier in the patch set and then you don't\nneed all the ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS ?\n\n> ---\n> drivers/mmc/host/Kconfig | 1 +\n> 1 file changed, 1 insertion(+)\n> \n> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig\n> index 2db84dd..64a9298 100644\n> --- a/drivers/mmc/host/Kconfig\n> +++ b/drivers/mmc/host/Kconfig\n> @@ -420,6 +420,7 @@ config MMC_SDHCI_MSM\n> \ttristate \"Qualcomm SDHCI Controller Support\"\n> \tdepends on ARCH_QCOM || (ARM && COMPILE_TEST)\n> \tdepends on MMC_SDHCI_PLTFM\n> +\tselect CONFIG_MMC_SDHCI_IO_ACCESSORS\n\nCONFIG_MMC_SDHCI_IO_ACCESSORS -> MMC_SDHCI_IO_ACCESSORS\n\n> \thelp\n> \t This selects the Secure Digital Host Controller Interface (SDHCI)\n> \t support present in Qualcomm SOCs. The controller supports\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"soNkM5v/\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xt8R311Lbz9sPk\n\tfor ;\n\tThu, 14 Sep 2017 16:54:39 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dsO2l-0004Ad-Tp; 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d=\"scan'208\";a=\"900122951\"","Subject":"Re: [PATCH v1 5/5] mmc: Kconfig: Enable\n\tCONFIG_MMC_SDHCI_IO_ACCESSORS","To":"Vijay Viswanath , ulf.hansson@linaro.org,\n\twill.deacon@arm.com","References":"<1504097509-58983-1-git-send-email-vviswana@codeaurora.org>\n\t<1504097509-58983-6-git-send-email-vviswana@codeaurora.org>","From":"Adrian Hunter ","Organization":"Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, \n\tBusiness Identity Code: 0357606 - 4, Domiciled in Helsinki","Message-ID":"","Date":"Thu, 14 Sep 2017 09:34:51 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<1504097509-58983-6-git-send-email-vviswana@codeaurora.org>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170913_234201_458451_DE92C631 ","X-CRM114-Status":"GOOD ( 11.17 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [192.55.52.115 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"riteshh@codeaurora.org, linux-arm-msm@vger.kernel.org,\n\tlinux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tstummala@codeaurora.org, subhashj@codeaurora.org,\n\tlinux-arm-kernel@lists.infradead.org, asutoshd@codeaurora.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1770642,"web_url":"http://patchwork.ozlabs.org/comment/1770642/","msgid":"","list_archive_url":null,"date":"2017-09-19T04:03:21","subject":"Re: [PATCH v1 5/5] mmc: Kconfig: Enable\n\tCONFIG_MMC_SDHCI_IO_ACCESSORS","submitter":{"id":72258,"url":"http://patchwork.ozlabs.org/api/people/72258/","name":"Vijay Viswanath","email":"vviswana@codeaurora.org"},"content":"On 9/14/2017 12:04 PM, Adrian Hunter wrote:\n> On 30/08/17 15:51, Vijay Viswanath wrote:\n>> Enable CONFIG_MMC_SDHCI_IO_ACCESSORS so that SDHC controller specific\n>> register read and write APIs, if registered, can be used.\n> \n> Missing signed-off\n> \n> Why don't you put this patch earlier in the patch set and then you don't\n> need all the ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS ?\n> \n\nThis will involve merging the current patches 3 & 4 into one (Some \nfunctions defined under ifdef in patch 3 are used only in patch 4). Will \nthat be fine ?\n\n>> ---\n>> drivers/mmc/host/Kconfig | 1 +\n>> 1 file changed, 1 insertion(+)\n>>\n>> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig\n>> index 2db84dd..64a9298 100644\n>> --- a/drivers/mmc/host/Kconfig\n>> +++ b/drivers/mmc/host/Kconfig\n>> @@ -420,6 +420,7 @@ config MMC_SDHCI_MSM\n>> \ttristate \"Qualcomm SDHCI Controller Support\"\n>> \tdepends on ARCH_QCOM || (ARM && COMPILE_TEST)\n>> \tdepends on MMC_SDHCI_PLTFM\n>> +\tselect CONFIG_MMC_SDHCI_IO_ACCESSORS\n> \n> CONFIG_MMC_SDHCI_IO_ACCESSORS -> MMC_SDHCI_IO_ACCESSORS\n> \n>> \thelp\n>> \t This selects the Secure Digital Host Controller Interface (SDHCI)\n>> \t support present in Qualcomm SOCs. The controller supports\n>>\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"RXYhmEoH\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"PLUlxajl\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"PLUlxajl\"; \n\tdkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none) header.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=vviswana@codeaurora.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xx8tW52xBz9ryr\n\tfor ;\n\tTue, 19 Sep 2017 14:25:23 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1duA61-00049D-Qq; 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WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170918_210349_464970_10BCF22A ","X-CRM114-Status":"GOOD ( 12.02 )","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.3 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [198.145.29.96 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"riteshh@codeaurora.org, linux-arm-msm@vger.kernel.org,\n\tlinux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tstummala@codeaurora.org, subhashj@codeaurora.org,\n\tlinux-arm-kernel@lists.infradead.org, asutoshd@codeaurora.org","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1770669,"web_url":"http://patchwork.ozlabs.org/comment/1770669/","msgid":"<33605097-6881-50a3-4526-a2ac6448a60d@intel.com>","list_archive_url":null,"date":"2017-09-19T05:44:26","subject":"Re: [PATCH v1 5/5] mmc: Kconfig: Enable\n\tCONFIG_MMC_SDHCI_IO_ACCESSORS","submitter":{"id":11091,"url":"http://patchwork.ozlabs.org/api/people/11091/","name":"Adrian Hunter","email":"adrian.hunter@intel.com"},"content":"On 19/09/17 07:03, Vijay Viswanath wrote:\n> \n> \n> On 9/14/2017 12:04 PM, Adrian Hunter wrote:\n>> On 30/08/17 15:51, Vijay Viswanath wrote:\n>>> Enable CONFIG_MMC_SDHCI_IO_ACCESSORS so that SDHC controller specific\n>>> register read and write APIs, if registered, can be used.\n>>\n>> Missing signed-off\n>>\n>> Why don't you put this patch earlier in the patch set and then you don't\n>> need all the ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS ?\n>>\n> \n> This will involve merging the current patches 3 & 4 into one (Some functions\n> defined under ifdef in patch 3 are used only in patch 4). Will that be fine ?\n\nSure\n\n> \n>>> ---\n>>> drivers/mmc/host/Kconfig | 1 +\n>>> 1 file changed, 1 insertion(+)\n>>>\n>>> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig\n>>> index 2db84dd..64a9298 100644\n>>> --- a/drivers/mmc/host/Kconfig\n>>> +++ b/drivers/mmc/host/Kconfig\n>>> @@ -420,6 +420,7 @@ config MMC_SDHCI_MSM\n>>> tristate \"Qualcomm SDHCI Controller Support\"\n>>> depends on ARCH_QCOM || (ARM && COMPILE_TEST)\n>>> depends on MMC_SDHCI_PLTFM\n>>> + select CONFIG_MMC_SDHCI_IO_ACCESSORS\n>>\n>> CONFIG_MMC_SDHCI_IO_ACCESSORS -> MMC_SDHCI_IO_ACCESSORS\n>>\n>>> help\n>>> This selects the Secure Digital Host Controller Interface (SDHCI)\n>>> support present in Qualcomm SOCs. The controller supports\n>>>\n>>\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"a/7fr/QO\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxBp44Zvmz9ryQ\n\tfor ;\n\tTue, 19 Sep 2017 15:51:40 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1duBRX-0007FL-DS; Tue, 19 Sep 2017 05:51:35 +0000","from mga03.intel.com ([134.134.136.65])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1duBRU-00078p-14 for linux-arm-kernel@lists.infradead.org;\n\tTue, 19 Sep 2017 05:51:33 +0000","from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t18 Sep 2017 22:51:10 -0700","from ahunter-desktop.fi.intel.com (HELO [10.237.72.168])\n\t([10.237.72.168])\n\tby orsmga002.jf.intel.com with ESMTP; 18 Sep 2017 22:51:05 -0700"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:\n\tMessage-ID:From:References:To:Subject:Reply-To:Content-ID:Content-Description\n\t:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=qwgT7GjBsF85phwypCd5mnUUuN+Eju34Qk4uB5B328k=;\n\tb=a/7fr/QOrU9xsY\n\tXGkSvlOSFprKCUwRoc/3zQCJOrDumaOCc0VSVAzFoFxm16+vHVqlqfHxLRmKyZ7FOh+M1vALHG0H7\n\tYosWetbxufbBbG8I7gCsU90UhPhXEkTm/gMhnnXG3d1nYH+bF6qOMy9OI2clk2I0FL9y0GlDBesST\n\tY3TarDVrBKiCnup+4rEIPbavcGLn6FkAkLQcbyw78Qch/nJB8h9XKcXyKLZ0Us/GIISJEogIlS1cg\n\tfFkttmwG+MNIe9ryEnKA5OIg8h06cOG+F6ZJZXFX2K4ZQv4Qep9rUmBT/jK3cY2hyfDCQGz57/rxl\n\t1QYfyrS61J3PNdvkcUpQ==;","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,416,1500966000\"; d=\"scan'208\";a=\"136893529\"","Subject":"Re: [PATCH v1 5/5] mmc: Kconfig: Enable\n\tCONFIG_MMC_SDHCI_IO_ACCESSORS","To":"Vijay Viswanath , ulf.hansson@linaro.org,\n\twill.deacon@arm.com","References":"<1504097509-58983-1-git-send-email-vviswana@codeaurora.org>\n\t<1504097509-58983-6-git-send-email-vviswana@codeaurora.org>\n\t\n\t","From":"Adrian Hunter ","Organization":"Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, \n\tBusiness Identity Code: 0357606 - 4, Domiciled in Helsinki","Message-ID":"<33605097-6881-50a3-4526-a2ac6448a60d@intel.com>","Date":"Tue, 19 Sep 2017 08:44:26 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170918_225132_173964_828E186E ","X-CRM114-Status":"GOOD ( 11.95 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [134.134.136.65 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"riteshh@codeaurora.org, linux-arm-msm@vger.kernel.org,\n\tlinux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tstummala@codeaurora.org, subhashj@codeaurora.org,\n\tlinux-arm-kernel@lists.infradead.org, asutoshd@codeaurora.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}}]