[{"id":1759823,"web_url":"http://patchwork.ozlabs.org/comment/1759823/","msgid":"","list_archive_url":null,"date":"2017-08-30T02:54:03","subject":"Re: [RFC PATCH v9 5/7] perf: cavium: Support memory controller PMU\n\tcounters","submitter":{"id":71656,"url":"http://patchwork.ozlabs.org/api/people/71656/","name":"Shaokun Zhang","email":"zhangshaokun@hisilicon.com"},"content":"Hi Jan,\n\nSome trivial things i noticed, please consider if you are glad.\n\nThanks,\nShaokun\n\nOn 2017/8/29 21:12, Jan Glauber wrote:\n> Add support for the PMU counters on Cavium SOC memory controllers.\n> \n> This patch also adds generic functions to allow supporting more\n> devices with PMU counters.\n> \n> Properties of the LMC PMU counters:\n> - not stoppable\n> - fixed purpose\n> - read-only\n> - one PCI device per memory controller\n> \n> Signed-off-by: Jan Glauber \n> ---\n> drivers/perf/Kconfig | 8 +\n> drivers/perf/Makefile | 1 +\n> drivers/perf/cavium_pmu.c | 445 ++++++++++++++++++++++++++++++++++++++++\n> drivers/soc/cavium/cavium_lmc.c | 4 +\n> include/linux/cpuhotplug.h | 1 +\n> include/linux/soc/cavium/lmc.h | 3 +\n> 6 files changed, 462 insertions(+)\n> create mode 100644 drivers/perf/cavium_pmu.c\n> \n> diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig\n> index e5197ff..a787562 100644\n> --- a/drivers/perf/Kconfig\n> +++ b/drivers/perf/Kconfig\n> @@ -43,4 +43,12 @@ config XGENE_PMU\n> help\n> Say y if you want to use APM X-Gene SoC performance monitors.\n> \n> +config CAVIUM_PMU_LMC\n> +\ttristate \"Cavium SOC memory controller PMU\"\n> +\tdepends on ARCH_THUNDER && m\n> +\tselect CAVIUM_LMC\n> +\thelp\n> +\t Provides PMU counters for the memory controller on\n> +\t Cavium ThunderX or OcteonTX SOCs.\n> +\n> endmenu\n> diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile\n> index 6420bd4..077a15d 100644\n> --- a/drivers/perf/Makefile\n> +++ b/drivers/perf/Makefile\n> @@ -3,3 +3,4 @@ obj-$(CONFIG_ARM_PMU_ACPI) += arm_pmu_acpi.o\n> obj-$(CONFIG_QCOM_L2_PMU)\t+= qcom_l2_pmu.o\n> obj-$(CONFIG_QCOM_L3_PMU) += qcom_l3_pmu.o\n> obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o\n> +obj-$(CONFIG_CAVIUM_PMU_LMC) += cavium_pmu.o\n\nKeep in alphabetic order?\n\n> diff --git a/drivers/perf/cavium_pmu.c b/drivers/perf/cavium_pmu.c\n> new file mode 100644\n> index 0000000..bcdedaa\n> --- /dev/null\n> +++ b/drivers/perf/cavium_pmu.c\n> @@ -0,0 +1,445 @@\n> +/*\n> + * Cavium ARM SOC \"uncore\" PMU counters\n> + *\n> + * This file is subject to the terms and conditions of the GNU General Public\n> + * License. See the file \"COPYING\" in the main directory of this archive\n> + * for more details.\n> + *\n> + * Copyright Cavium, Inc. 2017\n> + * Author(s): Jan Glauber \n> + *\n> + */\n> +#include \n> +#include \n> +#include \n> +#include \n\nKeep the include header files in alphabetic order too?\n\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +enum cvm_pmu_type {\n> +\tCVM_PMU_LMC,\n> +};\n> +\n> +/* maximum number of parallel hardware counters for all pmu types */\n> +#define CVM_PMU_MAX_COUNTERS 64\n> +\n> +/* generic struct to cover the different pmu types */\n> +struct cvm_pmu_dev {\n> +\tstruct pmu pmu;\n> +\tconst char *pmu_name;\n\nIt seems that pmu_name is redundant since struct pmu has a name field,\nMark has mentioned it in HiSilicon uncore PMU driver, Link:\nhttps://patchwork.kernel.org/patch/9861821/\n\n> +\tbool (*event_valid)(u64);\n> +\tvoid __iomem *map;\n> +\tstruct pci_dev *pdev;\n> +\tint num_counters;\n> +\tstruct perf_event *events[CVM_PMU_MAX_COUNTERS];\n> +\tstruct list_head entry;\n> +\tstruct hlist_node cpuhp_node;\n> +\tcpumask_t active_mask;\n> +};\n> +\n> +static struct list_head cvm_pmu_lmcs;\n> +static struct list_head cvm_pmu_tlks;\n> +\n> +/*\n> + * Common Cavium PMU stuff\n> + *\n> + * Shared properties of the different PMU types:\n> + * - all counters are 64 bit long\n> + * - there are no overflow interrupts\n> + * - all devices with PMU counters appear as PCI devices\n> + *\n> + * Counter control, access and device association depends on the\n> + * PMU type.\n> + */\n> +\n> +#define to_pmu_dev(x) container_of((x), struct cvm_pmu_dev, pmu)\n> +\n> +static int cvm_pmu_event_init(struct perf_event *event)\n> +{\n> +\tstruct hw_perf_event *hwc = &event->hw;\n> +\tstruct cvm_pmu_dev *pmu_dev;\n> +\tstruct perf_event *sibling;\n> +\n> +\tif (event->attr.type != event->pmu->type)\n> +\t\treturn -ENOENT;\n> +\n> +\t/* we do not support sampling */\n> +\tif (is_sampling_event(event))\n> +\t\treturn -EINVAL;\n> +\n> +\t/* PMU counters do not support any these bits */\n> +\tif (event->attr.exclude_user\t||\n> +\t event->attr.exclude_kernel\t||\n> +\t event->attr.exclude_host\t||\n> +\t event->attr.exclude_guest\t||\n> +\t event->attr.exclude_hv\t||\n> +\t event->attr.exclude_idle)\n> +\t\treturn -EINVAL;\n> +\n> +\tpmu_dev = to_pmu_dev(event->pmu);\n> +\tif (!pmu_dev->event_valid(event->attr.config))\n> +\t\treturn -EINVAL;\n> +\n> +\t/*\n> +\t * Forbid groups containing mixed PMUs, software events are acceptable.\n> +\t */\n> +\tif (event->group_leader->pmu != event->pmu &&\n> +\t !is_software_event(event->group_leader))\n> +\t\treturn -EINVAL;\n> +\n> +\tlist_for_each_entry(sibling, &event->group_leader->sibling_list,\n> +\t\t\t group_entry)\n> +\t\tif (sibling->pmu != event->pmu &&\n> +\t\t !is_software_event(sibling))\n> +\t\t\treturn -EINVAL;\n> +\n> +\thwc->config = event->attr.config;\n> +\thwc->idx = -1;\n\nBlank line?\n\n> +\treturn 0;\n> +}\n> +\n> +static void cvm_pmu_read(struct perf_event *event)\n> +{\n> +\tstruct cvm_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);\n> +\tstruct hw_perf_event *hwc = &event->hw;\n> +\tu64 prev, delta, new;\n> +\n> +again:\n> +\tprev = local64_read(&hwc->prev_count);\n> +\tnew = readq(hwc->event_base + pmu_dev->map);\n> +\n> +\tif (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)\n> +\t\tgoto again;\n> +\n> +\tdelta = new - prev;\n> +\tlocal64_add(delta, &event->count);\n> +}\n> +\n> +static void cvm_pmu_start(struct perf_event *event, int flags)\n> +{\n> +\tstruct cvm_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);\n> +\tstruct hw_perf_event *hwc = &event->hw;\n> +\tu64 new;\n> +\n> +\tif (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))\n> +\t\treturn;\n> +\n> +\tWARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));\n> +\thwc->state = 0;\n> +\n> +\t/* update prev_count always in order support unstoppable counters */\n> +\tnew = readq(hwc->event_base + pmu_dev->map);\n> +\tlocal64_set(&hwc->prev_count, new);\n> +\n> +\tperf_event_update_userpage(event);\n> +}\n> +\n> +static void cvm_pmu_stop(struct perf_event *event, int flags)\n> +{\n> +\tstruct hw_perf_event *hwc = &event->hw;\n> +\n> +\tWARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);\n> +\thwc->state |= PERF_HES_STOPPED;\n> +\n> +\tif ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {\n> +\t\tcvm_pmu_read(event);\n> +\t\thwc->state |= PERF_HES_UPTODATE;\n> +\t}\n> +}\n> +\n> +static int cvm_pmu_add(struct perf_event *event, int flags, u64 config_base,\n> +\t\t u64 event_base)\n> +{\n> +\tstruct cvm_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);\n> +\tstruct hw_perf_event *hwc = &event->hw;\n> +\n> +\tif (!cmpxchg(&pmu_dev->events[hwc->config], NULL, event))\n> +\t\thwc->idx = hwc->config;\n> +\n> +\tif (hwc->idx == -1)\n> +\t\treturn -EBUSY;\n> +\n> +\thwc->config_base = config_base;\n> +\thwc->event_base = event_base;\n> +\thwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;\n> +\n> +\tif (flags & PERF_EF_START)\n> +\t\tpmu_dev->pmu.start(event, PERF_EF_RELOAD);\n> +\n> +\treturn 0;\n> +}\n> +\n> +static void cvm_pmu_del(struct perf_event *event, int flags)\n> +{\n> +\tstruct cvm_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);\n> +\tstruct hw_perf_event *hwc = &event->hw;\n> +\tint i;\n> +\n> +\tevent->pmu->stop(event, PERF_EF_UPDATE);\n> +\n> +\t/*\n> +\t * For programmable counters we need to check where we installed it.\n> +\t * To keep this function generic always test the more complicated\n> +\t * case (free running counters won't need the loop).\n> +\t */\n> +\tfor (i = 0; i < pmu_dev->num_counters; i++)\n> +\t\tif (cmpxchg(&pmu_dev->events[i], event, NULL) == event)\n> +\t\t\tbreak;\n> +\n> +\tperf_event_update_userpage(event);\n> +\thwc->idx = -1;\n> +}\n> +\n> +static ssize_t cvm_pmu_event_sysfs_show(struct device *dev,\n> +\t\t\t\t\tstruct device_attribute *attr,\n> +\t\t\t\t\tchar *page)\n> +{\n> +\tstruct perf_pmu_events_attr *pmu_attr =\n> +\t\tcontainer_of(attr, struct perf_pmu_events_attr, attr);\n> +\n> +\tif (pmu_attr->event_str)\n> +\t\treturn sprintf(page, \"%s\", pmu_attr->event_str);\n> +\n> +\treturn 0;\n> +}\n> +\n> +/*\n> + * The pmu events are independent from CPUs. Provide a cpumask\n> + * nevertheless to prevent perf from adding the event per-cpu and just\n> + * set the mask to one online CPU. Use the same cpumask for all \"uncore\"\n> + * devices.\n> + *\n> + * There is a performance penalty for accessing a device from a CPU on\n> + * another socket, but we do not care.\n> + */\n> +static int cvm_pmu_offline_cpu(unsigned int old_cpu, struct hlist_node *node)\n> +{\n> +\tstruct cvm_pmu_dev *pmu_dev;\n> +\tint new_cpu;\n\nunsigned int?\n\n> +\n> +\tpmu_dev = hlist_entry_safe(node, struct cvm_pmu_dev, cpuhp_node);\n> +\tif (!cpumask_test_and_clear_cpu(old_cpu, &pmu_dev->active_mask))\n> +\t\treturn 0;\n> +\n> +\tnew_cpu = cpumask_any_but(cpu_online_mask, old_cpu);\n> +\tif (new_cpu >= nr_cpu_ids)\n> +\t\treturn 0;\n> +\n> +\tperf_pmu_migrate_context(&pmu_dev->pmu, old_cpu, new_cpu);\n> +\tcpumask_set_cpu(new_cpu, &pmu_dev->active_mask);\n> +\n> +\treturn 0;\n> +}\n> +\n> +static ssize_t cvm_pmu_attr_show_cpumask(struct device *dev,\n> +\t\t\t\t\t struct device_attribute *attr,\n> +\t\t\t\t\t char *buf)\n> +{\n> +\tstruct pmu *pmu = dev_get_drvdata(dev);\n> +\tstruct cvm_pmu_dev *pmu_dev = container_of(pmu, struct cvm_pmu_dev, pmu);\n> +\n> +\treturn cpumap_print_to_pagebuf(true, buf, &pmu_dev->active_mask);\n> +}\n> +\n> +static DEVICE_ATTR(cpumask, S_IRUGO, cvm_pmu_attr_show_cpumask, NULL);\n> +\n> +static struct attribute *cvm_pmu_attrs[] = {\n> +\t&dev_attr_cpumask.attr,\n> +\tNULL,\n> +};\n> +\n> +static struct attribute_group cvm_pmu_attr_group = {\n> +\t.attrs = cvm_pmu_attrs,\n> +};\n> +\n> +/*\n> + * LMC (memory controller) counters:\n> + * - not stoppable, always on, read-only\n> + * - one PCI device per memory controller\n> + */\n> +#define LMC_CONFIG_OFFSET\t\t0x188\n> +#define LMC_CONFIG_RESET_BIT\t\tBIT(17)\n> +\n> +/* LMC events */\n> +#define LMC_EVENT_IFB_CNT\t\t0x1d0\n> +#define LMC_EVENT_OPS_CNT\t\t0x1d8\n> +#define LMC_EVENT_DCLK_CNT\t\t0x1e0\n> +#define LMC_EVENT_BANK_CONFLICT1\t0x360\n> +#define LMC_EVENT_BANK_CONFLICT2\t0x368\n> +\n> +#define CVM_PMU_LMC_EVENT_ATTR(_name, _id)\t\t\t\t\t\t\\\n> +\t&((struct perf_pmu_events_attr[]) {\t\t\t\t\t\t\\\n> +\t\t{\t\t\t\t\t\t\t\t\t\\\n> +\t\t\t__ATTR(_name, S_IRUGO, cvm_pmu_event_sysfs_show, NULL),\t\t\\\n> +\t\t\t_id,\t\t\t\t\t\t\t\t\\\n> +\t\t\t\"lmc_event=\" __stringify(_id),\t\t\t\t\t\\\n> +\t\t}\t\t\t\t\t\t\t\t\t\\\n> +\t})[0].attr.attr\n> +\n> +/* map counter numbers to register offsets */\n> +static int lmc_events[] = {\n\nAdd const?\n\n> +\tLMC_EVENT_IFB_CNT,\n> +\tLMC_EVENT_OPS_CNT,\n> +\tLMC_EVENT_DCLK_CNT,\n> +\tLMC_EVENT_BANK_CONFLICT1,\n> +\tLMC_EVENT_BANK_CONFLICT2,\n> +};\n> +\n> +static int cvm_pmu_lmc_add(struct perf_event *event, int flags)\n> +{\n> +\tstruct hw_perf_event *hwc = &event->hw;\n> +\n> +\treturn cvm_pmu_add(event, flags, LMC_CONFIG_OFFSET,\n> +\t\t\t lmc_events[hwc->config]);\n> +}\n> +\n> +PMU_FORMAT_ATTR(lmc_event, \"config:0-2\");\n> +\n> +static struct attribute *cvm_pmu_lmc_format_attr[] = {\n> +\t&format_attr_lmc_event.attr,\n> +\tNULL,\n> +};\n> +\n> +static struct attribute_group cvm_pmu_lmc_format_group = {\n> +\t.name = \"format\",\n> +\t.attrs = cvm_pmu_lmc_format_attr,\n> +};\n> +\n> +static struct attribute *cvm_pmu_lmc_events_attr[] = {\n> +\tCVM_PMU_LMC_EVENT_ATTR(ifb_cnt,\t\t0),\n> +\tCVM_PMU_LMC_EVENT_ATTR(ops_cnt,\t\t1),\n> +\tCVM_PMU_LMC_EVENT_ATTR(dclk_cnt,\t2),\n> +\tCVM_PMU_LMC_EVENT_ATTR(bank_conflict1,\t3),\n> +\tCVM_PMU_LMC_EVENT_ATTR(bank_conflict2,\t4),\n> +\tNULL,\n> +};\n> +\n> +static struct attribute_group cvm_pmu_lmc_events_group = {\n> +\t.name = \"events\",\n> +\t.attrs = cvm_pmu_lmc_events_attr,\n> +};\n> +\n> +static const struct attribute_group *cvm_pmu_lmc_attr_groups[] = {\n> +\t&cvm_pmu_attr_group,\n> +\t&cvm_pmu_lmc_format_group,\n> +\t&cvm_pmu_lmc_events_group,\n> +\tNULL,\n> +};\n> +\n> +static bool cvm_pmu_lmc_event_valid(u64 config)\n> +{\n> +\treturn (config < ARRAY_SIZE(lmc_events));\n> +}\n> +\n> +int cvm_lmc_pmu_probe(struct pci_dev *pdev, const struct pci_device_id *ent)\n> +{\n> +\tstruct cvm_pmu_dev *next, *lmc;\n> +\tint nr = 0, ret = -ENOMEM;\n> +\n> +\tlmc = kzalloc(sizeof(*lmc), GFP_KERNEL);\n\nHow about use devm_kzalloc?\n\n> +\tif (!lmc)\n> +\t\treturn -ENOMEM;\n> +\n> +\tlmc->map = ioremap(pci_resource_start(pdev, 0),\n> +\t\t\t pci_resource_len(pdev, 0));\n> +\tif (!lmc->map)\n> +\t\tgoto fail_ioremap;\n> +\n> +\tlist_for_each_entry(next, &cvm_pmu_lmcs, entry)\n> +\t\tnr++;\n> +\tlmc->pmu_name = kasprintf(GFP_KERNEL, \"lmc%d\", nr);\n\nUse devm_kasprintf, simplify fail handle and memory free?\n\n> +\tif (!lmc->pmu_name)\n> +\t\tgoto fail_kasprintf;\n> +\n> +\tlmc->pdev = pdev;\n> +\tlmc->num_counters = ARRAY_SIZE(lmc_events);\n> +\tlmc->pmu = (struct pmu) {\n> +\t\t.task_ctx_nr = perf_invalid_context,\n> +\t\t.event_init\t= cvm_pmu_event_init,\n> +\t\t.add\t\t= cvm_pmu_lmc_add,\n> +\t\t.del\t\t= cvm_pmu_del,\n> +\t\t.start\t\t= cvm_pmu_start,\n> +\t\t.stop\t\t= cvm_pmu_stop,\n> +\t\t.read\t\t= cvm_pmu_read,\n> +\t\t.attr_groups\t= cvm_pmu_lmc_attr_groups,\n> +\t};\n> +\n> +\tcpuhp_state_add_instance_nocalls(CPUHP_AP_PERF_ARM_CVM_ONLINE,\n> +\t\t\t\t\t &lmc->cpuhp_node);\n> +\n> +\t/*\n> +\t * perf PMU is CPU dependent so pick a random CPU and migrate away\n> +\t * if it goes offline.\n> +\t */\n> +\tcpumask_set_cpu(smp_processor_id(), &lmc->active_mask);\n> +\n> +\tlist_add(&lmc->entry, &cvm_pmu_lmcs);\n> +\tlmc->event_valid = cvm_pmu_lmc_event_valid;\n> +\n> +\tret = perf_pmu_register(&lmc->pmu, lmc->pmu_name, -1);\n> +\tif (ret)\n> +\t\tgoto fail_pmu;\n> +\n> +\tdev_info(&pdev->dev, \"Enabled %s PMU with %d counters\\n\",\n> +\t\t lmc->pmu_name, lmc->num_counters);\n\nBlank line?\n\n> +\treturn 0;\n> +\n> +fail_pmu:\n> +\tkfree(lmc->pmu_name);\n> +\tcpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_CVM_ONLINE,\n> +\t\t\t\t &lmc->cpuhp_node);\n> +fail_kasprintf:\n> +\tiounmap(lmc->map);\n> +fail_ioremap:\n> +\tkfree(lmc);\n> +\treturn ret;\n> +}\n> +EXPORT_SYMBOL_GPL(cvm_lmc_pmu_probe);\n> +\n> +void cvm_lmc_pmu_remove(struct pci_dev *pdev)\n> +{\n> +\tstruct list_head *l, *tmp;\n> +\tstruct cvm_pmu_dev *lmc;\n> +\n> +\tlist_for_each_safe(l, tmp, &cvm_pmu_lmcs) {\n> +\t\tlmc = list_entry(l, struct cvm_pmu_dev, entry);\n> +\t\tif (pdev != lmc->pdev)\n> +\t\t\tcontinue;\n> +\n> +\t\tperf_pmu_unregister(&lmc->pmu);\n> +\t\tiounmap(lmc->map);\n> +\t\tcpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_CVM_ONLINE,\n> +\t\t\t\t\t &lmc->cpuhp_node);\n> +\t\tlist_del(&lmc->entry);\n> +\t\tkfree(lmc->pmu_name);\n> +\t\tkfree(lmc);\n> +\t}\n> +}\n> +EXPORT_SYMBOL_GPL(cvm_lmc_pmu_remove);\n> +\n> +static int __init cvm_pmu_init(void)\n> +{\n> +\tINIT_LIST_HEAD(&cvm_pmu_lmcs);\n> +\tINIT_LIST_HEAD(&cvm_pmu_tlks);\n> +\n> +\treturn cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_CVM_ONLINE,\n> +\t\t\t\t \"perf/arm/cvm:online\", NULL,\n> +\t\t\t\t cvm_pmu_offline_cpu);\n> +}\n> +\n> +static void __exit cvm_pmu_exit(void)\n> +{\n> +\tcpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CVM_ONLINE);\n> +}\n> +\n> +module_init(cvm_pmu_init);\n> +module_exit(cvm_pmu_exit);\n> +\n> +MODULE_LICENSE(\"GPL v2\");\n> +MODULE_AUTHOR(\"Cavium, Inc.\");\n> +MODULE_DESCRIPTION(\"PMU Driver for Cavium ThunderX SOC\");\n> diff --git a/drivers/soc/cavium/cavium_lmc.c b/drivers/soc/cavium/cavium_lmc.c\n> index 87248e8..d21d59c 100644\n> --- a/drivers/soc/cavium/cavium_lmc.c\n> +++ b/drivers/soc/cavium/cavium_lmc.c\n> @@ -17,6 +17,8 @@\n> static int cvm_lmc_probe(struct pci_dev *pdev,\n> \t\t\t const struct pci_device_id *ent)\n> {\n> +\tif (IS_ENABLED(CONFIG_CAVIUM_PMU_LMC))\n> +\t\tcvm_lmc_pmu_probe(pdev, ent);\n> \tif (IS_ENABLED(CONFIG_EDAC_THUNDERX))\n> \t\tthunderx_edac_lmc_probe(pdev, ent);\n> \treturn 0;\n> @@ -24,6 +26,8 @@ static int cvm_lmc_probe(struct pci_dev *pdev,\n> \n> static void cvm_lmc_remove(struct pci_dev *pdev)\n> {\n> +\tif (IS_ENABLED(CONFIG_CAVIUM_PMU_LMC))\n> +\t\tcvm_lmc_pmu_remove(pdev);\n> \tif (IS_ENABLED(CONFIG_EDAC_THUNDERX))\n> \t\tthunderx_edac_lmc_remove(pdev);\n> }\n> diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h\n> index 82b30e6..ca84ac8 100644\n> --- a/include/linux/cpuhotplug.h\n> +++ b/include/linux/cpuhotplug.h\n> @@ -139,6 +139,7 @@ enum cpuhp_state {\n> \tCPUHP_AP_PERF_ARM_QCOM_L3_ONLINE,\n> \tCPUHP_AP_WORKQUEUE_ONLINE,\n> \tCPUHP_AP_RCUTREE_ONLINE,\n> +\tCPUHP_AP_PERF_ARM_CVM_ONLINE,\n\nAlphabetic order?\n\n> \tCPUHP_AP_ONLINE_DYN,\n> \tCPUHP_AP_ONLINE_DYN_END\t\t= CPUHP_AP_ONLINE_DYN + 30,\n> \tCPUHP_AP_X86_HPET_ONLINE,\n> diff --git a/include/linux/soc/cavium/lmc.h b/include/linux/soc/cavium/lmc.h\n> index 336f467..e5ad650 100644\n> --- a/include/linux/soc/cavium/lmc.h\n> +++ b/include/linux/soc/cavium/lmc.h\n> @@ -3,6 +3,9 @@\n> \n> #include \n> \n> +int cvm_lmc_pmu_probe(struct pci_dev *pdev, const struct pci_device_id *ent);\n> +void cvm_lmc_pmu_remove(struct pci_dev *pdev);\n> +\n> int thunderx_edac_lmc_probe(struct pci_dev *pdev, const struct pci_device_id *ent);\n> void thunderx_edac_lmc_remove(struct pci_dev *pdev);\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"h1ikJM7R\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhqqs4FKLz9sNc\n\tfor ;\n\tWed, 30 Aug 2017 12:55:21 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat 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h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:\n\tMessage-ID:From:References:To:Subject:Reply-To:Content-ID:Content-Description\n\t:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=+N8tfvzOA2E/fXhGzEEkVfkPbaPdJPsKTaZ16K98AkU=;\n\tb=h1ikJM7RGYEbkR\n\thrUxvemm2mMQrIP57npbTg8nxA93geEHorCgaoSSOAfC6sjN//R20Ssg56/ubIgAOTSAW57sQKcJ7\n\tb3DGt4TIeMCISVhfCkFV/4cHYj0dx0KTFtJiGpfj/L8mikWK6OrORKhCCJ7BJjHHy1NmgQZJOFZnu\n\tLHWG8UC0YDM+Yo04h7O7v+A43qJnssAZuP97Fc9+g4W70dmT2cUp+0MmrQzehHWlCt+Vm8ZmEF1iV\n\tsDmgAqtrmRaAlEFz4DkqwFemzFP1/EUjluUCbSrjpJNjVij2SXoeZHPQ0m/I7u8QxJe1fq6rdRAPa\n\tJQF0K4vArYHcfnYS7PsQ==;","Subject":"Re: [RFC PATCH v9 5/7] perf: cavium: Support memory controller PMU\n\tcounters","To":"Jan Glauber , Mark Rutland , \n\tWill Deacon ","References":"<20170829131238.4988-1-jglauber@cavium.com>\n\t<20170829131238.4988-6-jglauber@cavium.com>","From":"Zhangshaokun ","Message-ID":"","Date":"Wed, 30 Aug 2017 10:54:03 +0800","User-Agent":"Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101\n\tThunderbird/45.1.1","MIME-Version":"1.0","In-Reply-To":"<20170829131238.4988-6-jglauber@cavium.com>","X-Originating-IP":"[10.74.221.148]","X-CFilter-Loop":"Reflected","X-Mirapoint-Virus-RAPID-Raw":"score=unknown(0),\n\trefid=str=0001.0A020204.59A628D3.00AE, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32","X-Mirapoint-Loop-Id":"82afcfaa51375daa7330d49dea65d1ff","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170829_195450_388636_F86DD51E ","X-CRM114-Status":"GOOD ( 29.80 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Suzuki K Poulose , Borislav Petkov ,\n\tlinux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tDavid Daney ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1760012,"web_url":"http://patchwork.ozlabs.org/comment/1760012/","msgid":"<09997d9f-0003-0eb0-63d1-9b31e26e2229@arm.com>","list_archive_url":null,"date":"2017-08-30T10:03:00","subject":"Re: [RFC PATCH v9 5/7] perf: cavium: Support memory controller PMU\n\tcounters","submitter":{"id":65822,"url":"http://patchwork.ozlabs.org/api/people/65822/","name":"Suzuki K Poulose","email":"suzuki.poulose@arm.com"},"content":"On 29/08/17 14:12, Jan Glauber wrote:\n> Add support for the PMU counters on Cavium SOC memory controllers.\n>\n> This patch also adds generic functions to allow supporting more\n> devices with PMU counters.\n>\n> Properties of the LMC PMU counters:\n> - not stoppable\n> - fixed purpose\n> - read-only\n> - one PCI device per memory controller\n>\n> Signed-off-by: Jan Glauber \n\nJan,\n\nSome minor comments below.\n\n> +static void cvm_pmu_del(struct perf_event *event, int flags)\n> +{\n> +\tstruct cvm_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);\n> +\tstruct hw_perf_event *hwc = &event->hw;\n> +\tint i;\n> +\n> +\tevent->pmu->stop(event, PERF_EF_UPDATE);\n> +\n> +\t/*\n> +\t * For programmable counters we need to check where we installed it.\n> +\t * To keep this function generic always test the more complicated\n> +\t * case (free running counters won't need the loop).\n> +\t */\n> +\tfor (i = 0; i < pmu_dev->num_counters; i++)\n> +\t\tif (cmpxchg(&pmu_dev->events[i], event, NULL) == event)\n> +\t\t\tbreak;\n\nDoes this mean, it is the only way to map any given event (for programmable counters)\nto a hardware counter ? What do we store in hwc->idx ? We have 2 additional\nstruct hw_perf_event_extra fields. We should be able to use one field to map it\nback to the counter, isn't it ?\n\n> +\n> +\tperf_event_update_userpage(event);\n> +\thwc->idx = -1;\n> +}\n> +\n\n...\n\n> +/* LMC events */\n> +#define LMC_EVENT_IFB_CNT\t\t0x1d0\n> +#define LMC_EVENT_OPS_CNT\t\t0x1d8\n> +#define LMC_EVENT_DCLK_CNT\t\t0x1e0\n> +#define LMC_EVENT_BANK_CONFLICT1\t0x360\n> +#define LMC_EVENT_BANK_CONFLICT2\t0x368\n> +\n> +#define CVM_PMU_LMC_EVENT_ATTR(_name, _id)\t\t\t\t\t\t\\\n> +\t&((struct perf_pmu_events_attr[]) {\t\t\t\t\t\t\\\n> +\t\t{\t\t\t\t\t\t\t\t\t\\\n> +\t\t\t__ATTR(_name, S_IRUGO, cvm_pmu_event_sysfs_show, NULL),\t\t\\\n> +\t\t\t_id,\t\t\t\t\t\t\t\t\\\n> +\t\t\t\"lmc_event=\" __stringify(_id),\t\t\t\t\t\\\n> +\t\t}\t\t\t\t\t\t\t\t\t\\\n> +\t})[0].attr.attr\n> +\n> +/* map counter numbers to register offsets */\n> +static int lmc_events[] = {\n> +\tLMC_EVENT_IFB_CNT,\n> +\tLMC_EVENT_OPS_CNT,\n> +\tLMC_EVENT_DCLK_CNT,\n> +\tLMC_EVENT_BANK_CONFLICT1,\n> +\tLMC_EVENT_BANK_CONFLICT2,\n> +};\n> +\n> +static int cvm_pmu_lmc_add(struct perf_event *event, int flags)\n> +{\n> +\tstruct hw_perf_event *hwc = &event->hw;\n> +\n> +\treturn cvm_pmu_add(event, flags, LMC_CONFIG_OFFSET,\n> +\t\t\t lmc_events[hwc->config]);\n> +}\n> +\n\nIs there any reason why we can't use the LMC event code directly\nhere, avoiding the mapping altogether ?\n\n> +PMU_FORMAT_ATTR(lmc_event, \"config:0-2\");\n> +\n> +static struct attribute *cvm_pmu_lmc_format_attr[] = {\n> +\t&format_attr_lmc_event.attr,\n> +\tNULL,\n> +};\n> +\n> +static struct attribute_group cvm_pmu_lmc_format_group = {\n> +\t.name = \"format\",\n> +\t.attrs = cvm_pmu_lmc_format_attr,\n> +};\n> +\n> +static struct attribute *cvm_pmu_lmc_events_attr[] = {\n> +\tCVM_PMU_LMC_EVENT_ATTR(ifb_cnt,\t\t0),\n> +\tCVM_PMU_LMC_EVENT_ATTR(ops_cnt,\t\t1),\n> +\tCVM_PMU_LMC_EVENT_ATTR(dclk_cnt,\t2),\n> +\tCVM_PMU_LMC_EVENT_ATTR(bank_conflict1,\t3),\n> +\tCVM_PMU_LMC_EVENT_ATTR(bank_conflict2,\t4),\n> +\tNULL,\n> +};\n> +\n> +static struct attribute_group cvm_pmu_lmc_events_group = {\n> +\t.name = \"events\",\n> +\t.attrs = cvm_pmu_lmc_events_attr,\n> +};\n> +\n> +static const struct attribute_group *cvm_pmu_lmc_attr_groups[] = {\n> +\t&cvm_pmu_attr_group,\n> +\t&cvm_pmu_lmc_format_group,\n> +\t&cvm_pmu_lmc_events_group,\n> +\tNULL,\n> +};\n> +\n> +static bool cvm_pmu_lmc_event_valid(u64 config)\n> +{\n> +\treturn (config < ARRAY_SIZE(lmc_events));\n> +}\n> +\n> +int cvm_lmc_pmu_probe(struct pci_dev *pdev, const struct pci_device_id *ent)\n> +{\n> +\tstruct cvm_pmu_dev *next, *lmc;\n> +\tint nr = 0, ret = -ENOMEM;\n> +\n> +\tlmc = kzalloc(sizeof(*lmc), GFP_KERNEL);\n> +\tif (!lmc)\n> +\t\treturn -ENOMEM;\n\nAs Shaokun mentioned already, we could use devm_kzalloc() to avoid having to\ncleanup the memory explicitly upon error and during module unload.\n\n> +\n> +\tlmc->map = ioremap(pci_resource_start(pdev, 0),\n> +\t\t\t pci_resource_len(pdev, 0));\n\nUse devm_ioremap here. See below.\n\n> +\tif (!lmc->map)\n> +\t\tgoto fail_ioremap;\n> +\n> +\tlist_for_each_entry(next, &cvm_pmu_lmcs, entry)\n> +\t\tnr++;\n> +\tlmc->pmu_name = kasprintf(GFP_KERNEL, \"lmc%d\", nr);\n\nAgain, you could remove the field and use devm_kasprintf() into a local\nvariable for using it with pmu_register. It would be automatically free'd\nupon error or device removal.\n\n> +\tif (!lmc->pmu_name)\n> +\t\tgoto fail_kasprintf;\n> +\n> +\tlmc->pdev = pdev;\n> +\tlmc->num_counters = ARRAY_SIZE(lmc_events);\n> +\tlmc->pmu = (struct pmu) {\n> +\t\t.task_ctx_nr = perf_invalid_context,\n> +\t\t.event_init\t= cvm_pmu_event_init,\n> +\t\t.add\t\t= cvm_pmu_lmc_add,\n> +\t\t.del\t\t= cvm_pmu_del,\n> +\t\t.start\t\t= cvm_pmu_start,\n> +\t\t.stop\t\t= cvm_pmu_stop,\n> +\t\t.read\t\t= cvm_pmu_read,\n> +\t\t.attr_groups\t= cvm_pmu_lmc_attr_groups,\n> +\t};\n> +\n> +\tcpuhp_state_add_instance_nocalls(CPUHP_AP_PERF_ARM_CVM_ONLINE,\n> +\t\t\t\t\t &lmc->cpuhp_node);\n> +\n> +\t/*\n> +\t * perf PMU is CPU dependent so pick a random CPU and migrate away\n> +\t * if it goes offline.\n> +\t */\n> +\tcpumask_set_cpu(smp_processor_id(), &lmc->active_mask);\n> +\n> +\tlist_add(&lmc->entry, &cvm_pmu_lmcs);\n> +\tlmc->event_valid = cvm_pmu_lmc_event_valid;\n> +\n> +\tret = perf_pmu_register(&lmc->pmu, lmc->pmu_name, -1);\n> +\tif (ret)\n> +\t\tgoto fail_pmu;\n> +\n> +\tdev_info(&pdev->dev, \"Enabled %s PMU with %d counters\\n\",\n> +\t\t lmc->pmu_name, lmc->num_counters);\n> +\treturn 0;\n> +\n> +fail_pmu:\n> +\tkfree(lmc->pmu_name);\n> +\tcpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_CVM_ONLINE,\n> +\t\t\t\t &lmc->cpuhp_node);\n> +fail_kasprintf:\n> +\tiounmap(lmc->map);\n> +fail_ioremap:\n> +\tkfree(lmc);\n\nAs mentioned above, if you switch to devm_* versions, you could get rid of this\nkfrees and iounmap.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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Wed, 30 Aug 2017 03:03:02 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type:\n\tContent-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive:\n\tList-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From:\n\tReferences:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;\n\tbh=Z1kG13ULAJxPzjSkLYVzZx9eg1pe/Ed/ilT9dc4eWrI=;\n\tb=SGyve8Ba38spfAyTNyI8i9YNP\n\tvZWlyzz+5x0z1u8QIK7vO1f3NPLNQqUwQJloN4HUl1YvuUoyeZ+kgkipbRPehqysgEq1XtmxxSDik\n\tMqDiEUvIYvgMU0zd6yPxNYnCOon6kTFsCESgooHIScmlSQtC3jwbknIC4XP+phSHmN/OJ0H5bisJe\n\t8YVdnnHMSYa2Nxgf0eOQJS6c6rCVcQDdVHzWfWmDk9K5tgTcN+c+nILy8TiHPufMU1YYQxmG0/10M\n\tCkfyWXry58d/Q5N3l51a27fO9zgi2J5znHXcEzZmbIfBS+4fuMPH5QHP+Csko/6AU7J+l+ICea5bN\n\t1T3feVmeg==;","Subject":"Re: [RFC PATCH v9 5/7] perf: cavium: Support memory controller PMU\n\tcounters","To":"Jan Glauber , Mark Rutland , \n\tWill Deacon ","References":"<20170829131238.4988-1-jglauber@cavium.com>\n\t<20170829131238.4988-6-jglauber@cavium.com>","From":"Suzuki K Poulose ","Message-ID":"<09997d9f-0003-0eb0-63d1-9b31e26e2229@arm.com>","Date":"Wed, 30 Aug 2017 11:03:00 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.8.0","MIME-Version":"1.0","In-Reply-To":"<20170829131238.4988-6-jglauber@cavium.com>","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170830_030324_277482_B7E850B4 ","X-CRM114-Status":"GOOD ( 22.65 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Borislav Petkov , linux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tDavid Daney ","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1760382,"web_url":"http://patchwork.ozlabs.org/comment/1760382/","msgid":"<20170830175406.ygmathi3b5orzyqy@pd.tnic>","list_archive_url":null,"date":"2017-08-30T17:54:06","subject":"Re: [RFC PATCH v9 1/7] edac: thunderx: Remove suspend/resume support","submitter":{"id":4449,"url":"http://patchwork.ozlabs.org/api/people/4449/","name":"Borislav Petkov","email":"bp@alien8.de"},"content":"On Tue, Aug 29, 2017 at 03:12:32PM +0200, Jan Glauber wrote:\n> The memory controller on ThunderX/OcteonTX systems does not\n> support power management. Therefore remove the suspend/resume\n> callbacks.\n> \n> Signed-off-by: Jan Glauber \n> ---\n> drivers/edac/thunderx_edac.c | 21 ---------------------\n> 1 file changed, 21 deletions(-)\n\nJust when I thought I'd pick that one up now because it is removing\nstuff:\n\ndrivers/edac/thunderx_edac.c:817:14: error: ‘thunderx_lmc_suspend’ undeclared here (not in a function)\n .suspend = thunderx_lmc_suspend,\n ^~~~~~~~~~~~~~~~~~~~\ndrivers/edac/thunderx_edac.c:818:14: error: ‘thunderx_lmc_resume’ undeclared here (not in a function)\n .resume = thunderx_lmc_resume,\n ^~~~~~~~~~~~~~~~~~~\nscripts/Makefile.build:308: recipe for target 'drivers/edac/thunderx_edac.o' failed\nmake[1]: *** [drivers/edac/thunderx_edac.o] Error 1\nmake[1]: *** Waiting for unfinished jobs....\nMakefile:1682: recipe for target 'drivers/edac/' failed\nmake: *** [drivers/edac/] Error 2\n\nPlease make sure you build and test every patch before submitting.\nYou're lucky I can at least build arm64 on my x86 workstation. :-)\n\nThx.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"VEZVOx5e\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjCnl58sNz9s8w\n\tfor ;\n\tThu, 31 Aug 2017 03:54:51 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dn7CR-0002Ci-MP; Wed, 30 Aug 2017 17:54:47 +0000","from mail.skyhub.de ([2a01:4f8:190:11c2::b:1457])\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dn7CM-0002At-Se for linux-arm-kernel@lists.infradead.org;\n\tWed, 30 Aug 2017 17:54:45 +0000","from mail.skyhub.de ([127.0.0.1])\n\tby localhost (blast.alien8.de [127.0.0.1]) (amavisd-new, port 10026)\n\twith ESMTP id LP9di6bw7SXW; Wed, 30 Aug 2017 19:54:17 +0200 (CEST)","from pd.tnic (p2003008C2F67CD00240DF70709634A95.dip0.t-ipconnect.de\n\t[IPv6:2003:8c:2f67:cd00:240d:f707:963:4a95])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id\n\t6BEAA1EC03E1; Wed, 30 Aug 2017 19:54:17 +0200 (CEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=8CWyT4ld9Jrg8Zjv79KXwJiwPUkRGIq8HP3sXZRecyk=;\n\tb=VEZVOx5eNAQcsz\n\tKhX6XtDYFVqr1I4o706oJkXB+0x5azNkcIIR+FKmXlqCMn5vGKVzZGuUSCIzNCAzn5jRd7e9gT8jA\n\tcFagsbBR49e/1Pr3RzU4VJOapa4DeqJwEGuTlT03+s34CVFTN4yoV16CXvOBR8K+yzfNNb0tuO7JJ\n\tTrYa2+Y+jJz90mwSOLJPK4irYh2Ly9d0AkE2lA1pxZGIiyKoZScK4638ujPMpOCxPd21yWtKxjpim\n\ttEm6T523dZyE9lL6uB4WHd7SrUbWgccEh2GetZrIsMEElWZOzBTydGgub+FCxQiPZRJ7ey/UuFRHD\n\tLasAGdTCmuZtYaBOHInA==;","X-Virus-Scanned":"Nedap ESD1 at mail.skyhub.de","Date":"Wed, 30 Aug 2017 19:54:06 +0200","From":"Borislav Petkov ","To":"Jan Glauber ","Subject":"Re: [RFC PATCH v9 1/7] edac: thunderx: Remove suspend/resume support","Message-ID":"<20170830175406.ygmathi3b5orzyqy@pd.tnic>","References":"<20170829131238.4988-1-jglauber@cavium.com>\n\t<20170829131238.4988-2-jglauber@cavium.com>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<20170829131238.4988-2-jglauber@cavium.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170830_105443_119977_6E289477 ","X-CRM114-Status":"UNSURE ( 9.58 )","X-CRM114-Notice":"Please train this message.","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Mark Rutland , David Daney ,\n\tSuzuki K Poulose ,\n\tWill Deacon , \n\tlinux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1760793,"web_url":"http://patchwork.ozlabs.org/comment/1760793/","msgid":"<20170831084606.GA14296@hc>","list_archive_url":null,"date":"2017-08-31T08:46:06","subject":"Re: [RFC PATCH v9 1/7] edac: thunderx: Remove suspend/resume support","submitter":{"id":68474,"url":"http://patchwork.ozlabs.org/api/people/68474/","name":"Jan Glauber","email":"jan.glauber@caviumnetworks.com"},"content":"On Wed, Aug 30, 2017 at 07:54:06PM +0200, Borislav Petkov wrote:\n> On Tue, Aug 29, 2017 at 03:12:32PM +0200, Jan Glauber wrote:\n> > The memory controller on ThunderX/OcteonTX systems does not\n> > support power management. Therefore remove the suspend/resume\n> > callbacks.\n> > \n> > Signed-off-by: Jan Glauber \n> > ---\n> > drivers/edac/thunderx_edac.c | 21 ---------------------\n> > 1 file changed, 21 deletions(-)\n> \n> Just when I thought I'd pick that one up now because it is removing\n> stuff:\n> \n> drivers/edac/thunderx_edac.c:817:14: error: ‘thunderx_lmc_suspend’ undeclared here (not in a function)\n> .suspend = thunderx_lmc_suspend,\n> ^~~~~~~~~~~~~~~~~~~~\n> drivers/edac/thunderx_edac.c:818:14: error: ‘thunderx_lmc_resume’ undeclared here (not in a function)\n> .resume = thunderx_lmc_resume,\n> ^~~~~~~~~~~~~~~~~~~\n> scripts/Makefile.build:308: recipe for target 'drivers/edac/thunderx_edac.o' failed\n> make[1]: *** [drivers/edac/thunderx_edac.o] Error 1\n> make[1]: *** Waiting for unfinished jobs....\n> Makefile:1682: recipe for target 'drivers/edac/' failed\n> make: *** [drivers/edac/] Error 2\n\nArgh... forgot to build test the single patches. \n\n> Please make sure you build and test every patch before submitting.\n> You're lucky I can at least build arm64 on my x86 workstation. :-)\n\nSorry for that. The whole series builds because I removed the suspend/resume\ncallbacks during the move to the soc driver.\n\n--Jan\n\n> Thx.\n> \n> -- \n> Regards/Gruss,\n> Boris.\n> \n> Good mailing practices for 400: avoid top-posting and trim the reply.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"hSuEmkWf\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=infradead.org header.i=@infradead.org\n\theader.b=\"hqdqsm2U\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=CAVIUMNETWORKS.onmicrosoft.com\n\theader.i=@CAVIUMNETWORKS.onmicrosoft.com header.b=\"M5GMKnvn\"; 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a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=5WsYQMpos9FscEzTrbrq11Wb/ToZOxRujAEx5+w91FA=;\n\tb=M5GMKnvniSSgWDhxAinAbAajv9JJsmnYP2vG8jt3Uhjz1GScflBpCySwMa3AjRaHWXzjX6PCIzrc0aeOf7nAki/a6AmsIn2IKsfp/pL5LDNlzWYJak0a9v9gQRkPD9eSP1Oc1fdL9rIdxMeP0/XaPLTLKoX6StTUGeiIY+2W0uQ="],"Date":"Thu, 31 Aug 2017 10:46:06 +0200","From":"Jan Glauber ","To":"Borislav Petkov ","Subject":"Re: [RFC PATCH v9 1/7] edac: thunderx: Remove suspend/resume support","Message-ID":"<20170831084606.GA14296@hc>","References":"<20170829131238.4988-1-jglauber@cavium.com>\n\t<20170829131238.4988-2-jglauber@cavium.com>\n\t<20170830175406.ygmathi3b5orzyqy@pd.tnic>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<20170830175406.ygmathi3b5orzyqy@pd.tnic>","User-Agent":"Mutt/1.5.21 (2010-09-15)","X-Originating-IP":"[46.223.64.100]","X-ClientProxiedBy":"AM3PR04CA0136.eurprd04.prod.outlook.com\n\t(2603:10a6:207::20)\n\tTo SN2PR07MB2592.namprd07.prod.outlook.com\n\t(2603:10b6:804:7::22)","X-MS-PublicTrafficType":"Email","X-MS-Office365-Filtering-Correlation-Id":"a60879e2-ac7f-498c-85ae-08d4f04cbfa1","X-Microsoft-Antispam":"UriScan:; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1760799,"web_url":"http://patchwork.ozlabs.org/comment/1760799/","msgid":"<20170831095746.GB15906@hc>","list_archive_url":null,"date":"2017-08-31T09:57:46","subject":"Re: [RFC PATCH v9 5/7] perf: cavium: Support memory controller PMU\n\tcounters","submitter":{"id":68474,"url":"http://patchwork.ozlabs.org/api/people/68474/","name":"Jan Glauber","email":"jan.glauber@caviumnetworks.com"},"content":"On Wed, Aug 30, 2017 at 10:54:03AM +0800, Zhangshaokun wrote:\n> Hi Jan,\n> \n> Some trivial things i noticed, please consider if you are glad.\n> \n> Thanks,\n> Shaokun\n\nHi Shaokun, thanks for the review.\n\n> On 2017/8/29 21:12, Jan Glauber wrote:\n> > Add support for the PMU counters on Cavium SOC memory controllers.\n> > \n> > This patch also adds generic functions to allow supporting more\n> > devices with PMU counters.\n> > \n> > Properties of the LMC PMU counters:\n> > - not stoppable\n> > - fixed purpose\n> > - read-only\n> > - one PCI device per memory controller\n> > \n> > Signed-off-by: Jan Glauber \n> > ---\n> > drivers/perf/Kconfig | 8 +\n> > drivers/perf/Makefile | 1 +\n> > drivers/perf/cavium_pmu.c | 445 ++++++++++++++++++++++++++++++++++++++++\n> > drivers/soc/cavium/cavium_lmc.c | 4 +\n> > include/linux/cpuhotplug.h | 1 +\n> > include/linux/soc/cavium/lmc.h | 3 +\n> > 6 files changed, 462 insertions(+)\n> > create mode 100644 drivers/perf/cavium_pmu.c\n> > \n> > diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig\n> > index e5197ff..a787562 100644\n> > --- a/drivers/perf/Kconfig\n> > +++ b/drivers/perf/Kconfig\n> > @@ -43,4 +43,12 @@ config XGENE_PMU\n> > help\n> > Say y if you want to use APM X-Gene SoC performance monitors.\n> > \n> > +config CAVIUM_PMU_LMC\n> > +\ttristate \"Cavium SOC memory controller PMU\"\n> > +\tdepends on ARCH_THUNDER && m\n> > +\tselect CAVIUM_LMC\n> > +\thelp\n> > +\t Provides PMU counters for the memory controller on\n> > +\t Cavium ThunderX or OcteonTX SOCs.\n> > +\n> > endmenu\n> > diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile\n> > index 6420bd4..077a15d 100644\n> > --- a/drivers/perf/Makefile\n> > +++ b/drivers/perf/Makefile\n> > @@ -3,3 +3,4 @@ obj-$(CONFIG_ARM_PMU_ACPI) += arm_pmu_acpi.o\n> > obj-$(CONFIG_QCOM_L2_PMU)\t+= qcom_l2_pmu.o\n> > obj-$(CONFIG_QCOM_L3_PMU) += qcom_l3_pmu.o\n> > obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o\n> > +obj-$(CONFIG_CAVIUM_PMU_LMC) += cavium_pmu.o\n> \n> Keep in alphabetic order?\n> \n\nOK.\n\n> > diff --git a/drivers/perf/cavium_pmu.c b/drivers/perf/cavium_pmu.c\n> > new file mode 100644\n> > index 0000000..bcdedaa\n> > --- /dev/null\n> > +++ b/drivers/perf/cavium_pmu.c\n> > @@ -0,0 +1,445 @@\n> > +/*\n> > + * Cavium ARM SOC \"uncore\" PMU counters\n> > + *\n> > + * This file is subject to the terms and conditions of the GNU General Public\n> > + * License. See the file \"COPYING\" in the main directory of this archive\n> > + * for more details.\n> > + *\n> > + * Copyright Cavium, Inc. 2017\n> > + * Author(s): Jan Glauber \n> > + *\n> > + */\n> > +#include \n> > +#include \n> > +#include \n> > +#include \n> \n> Keep the include header files in alphabetic order too?\n> \n> > +#include \n> > +#include \n> > +#include \n> > +#include \n> > +#include \n> > +#include \n> > +#include \n> > +\n> > +enum cvm_pmu_type {\n> > +\tCVM_PMU_LMC,\n> > +};\n> > +\n> > +/* maximum number of parallel hardware counters for all pmu types */\n> > +#define CVM_PMU_MAX_COUNTERS 64\n> > +\n> > +/* generic struct to cover the different pmu types */\n> > +struct cvm_pmu_dev {\n> > +\tstruct pmu pmu;\n> > +\tconst char *pmu_name;\n> \n> It seems that pmu_name is redundant since struct pmu has a name field,\n> Mark has mentioned it in HiSilicon uncore PMU driver, Link:\n> https://patchwork.kernel.org/patch/9861821/\n\nI don't get it. perf_pmu_register() just copies the char* from the\nargument into pmu->name. Somewhere the string must be allocated.\nThat's why I have cvm_pmu_dev->pmu_name.\n\n> > +\tbool (*event_valid)(u64);\n> > +\tvoid __iomem *map;\n> > +\tstruct pci_dev *pdev;\n> > +\tint num_counters;\n> > +\tstruct perf_event *events[CVM_PMU_MAX_COUNTERS];\n> > +\tstruct list_head entry;\n> > +\tstruct hlist_node cpuhp_node;\n> > +\tcpumask_t active_mask;\n> > +};\n> > +\n> > +static struct list_head cvm_pmu_lmcs;\n> > +static struct list_head cvm_pmu_tlks;\n> > +\n> > +/*\n> > + * Common Cavium PMU stuff\n> > + *\n> > + * Shared properties of the different PMU types:\n> > + * - all counters are 64 bit long\n> > + * - there are no overflow interrupts\n> > + * - all devices with PMU counters appear as PCI devices\n> > + *\n> > + * Counter control, access and device association depends on the\n> > + * PMU type.\n> > + */\n> > +\n> > +#define to_pmu_dev(x) container_of((x), struct cvm_pmu_dev, pmu)\n> > +\n> > +static int cvm_pmu_event_init(struct perf_event *event)\n> > +{\n> > +\tstruct hw_perf_event *hwc = &event->hw;\n> > +\tstruct cvm_pmu_dev *pmu_dev;\n> > +\tstruct perf_event *sibling;\n> > +\n> > +\tif (event->attr.type != event->pmu->type)\n> > +\t\treturn -ENOENT;\n> > +\n> > +\t/* we do not support sampling */\n> > +\tif (is_sampling_event(event))\n> > +\t\treturn -EINVAL;\n> > +\n> > +\t/* PMU counters do not support any these bits */\n> > +\tif (event->attr.exclude_user\t||\n> > +\t event->attr.exclude_kernel\t||\n> > +\t event->attr.exclude_host\t||\n> > +\t event->attr.exclude_guest\t||\n> > +\t event->attr.exclude_hv\t||\n> > +\t event->attr.exclude_idle)\n> > +\t\treturn -EINVAL;\n> > +\n> > +\tpmu_dev = to_pmu_dev(event->pmu);\n> > +\tif (!pmu_dev->event_valid(event->attr.config))\n> > +\t\treturn -EINVAL;\n> > +\n> > +\t/*\n> > +\t * Forbid groups containing mixed PMUs, software events are acceptable.\n> > +\t */\n> > +\tif (event->group_leader->pmu != event->pmu &&\n> > +\t !is_software_event(event->group_leader))\n> > +\t\treturn -EINVAL;\n> > +\n> > +\tlist_for_each_entry(sibling, &event->group_leader->sibling_list,\n> > +\t\t\t group_entry)\n> > +\t\tif (sibling->pmu != event->pmu &&\n> > +\t\t !is_software_event(sibling))\n> > +\t\t\treturn -EINVAL;\n> > +\n> > +\thwc->config = event->attr.config;\n> > +\thwc->idx = -1;\n> \n> Blank line?\n\nOK.\n\n> > +\treturn 0;\n> > +}\n> > +\n> > +static void cvm_pmu_read(struct perf_event *event)\n> > +{\n> > +\tstruct cvm_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);\n> > +\tstruct hw_perf_event *hwc = &event->hw;\n> > +\tu64 prev, delta, new;\n> > +\n> > +again:\n> > +\tprev = local64_read(&hwc->prev_count);\n> > +\tnew = readq(hwc->event_base + pmu_dev->map);\n> > +\n> > +\tif (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)\n> > +\t\tgoto again;\n> > +\n> > +\tdelta = new - prev;\n> > +\tlocal64_add(delta, &event->count);\n> > +}\n> > +\n> > +static void cvm_pmu_start(struct perf_event *event, int flags)\n> > +{\n> > +\tstruct cvm_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);\n> > +\tstruct hw_perf_event *hwc = &event->hw;\n> > +\tu64 new;\n> > +\n> > +\tif (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))\n> > +\t\treturn;\n> > +\n> > +\tWARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));\n> > +\thwc->state = 0;\n> > +\n> > +\t/* update prev_count always in order support unstoppable counters */\n> > +\tnew = readq(hwc->event_base + pmu_dev->map);\n> > +\tlocal64_set(&hwc->prev_count, new);\n> > +\n> > +\tperf_event_update_userpage(event);\n> > +}\n> > +\n> > +static void cvm_pmu_stop(struct perf_event *event, int flags)\n> > +{\n> > +\tstruct hw_perf_event *hwc = &event->hw;\n> > +\n> > +\tWARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);\n> > +\thwc->state |= PERF_HES_STOPPED;\n> > +\n> > +\tif ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {\n> > +\t\tcvm_pmu_read(event);\n> > +\t\thwc->state |= PERF_HES_UPTODATE;\n> > +\t}\n> > +}\n> > +\n> > +static int cvm_pmu_add(struct perf_event *event, int flags, u64 config_base,\n> > +\t\t u64 event_base)\n> > +{\n> > +\tstruct cvm_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);\n> > +\tstruct hw_perf_event *hwc = &event->hw;\n> > +\n> > +\tif (!cmpxchg(&pmu_dev->events[hwc->config], NULL, event))\n> > +\t\thwc->idx = hwc->config;\n> > +\n> > +\tif (hwc->idx == -1)\n> > +\t\treturn -EBUSY;\n> > +\n> > +\thwc->config_base = config_base;\n> > +\thwc->event_base = event_base;\n> > +\thwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;\n> > +\n> > +\tif (flags & PERF_EF_START)\n> > +\t\tpmu_dev->pmu.start(event, PERF_EF_RELOAD);\n> > +\n> > +\treturn 0;\n> > +}\n> > +\n> > +static void cvm_pmu_del(struct perf_event *event, int flags)\n> > +{\n> > +\tstruct cvm_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);\n> > +\tstruct hw_perf_event *hwc = &event->hw;\n> > +\tint i;\n> > +\n> > +\tevent->pmu->stop(event, PERF_EF_UPDATE);\n> > +\n> > +\t/*\n> > +\t * For programmable counters we need to check where we installed it.\n> > +\t * To keep this function generic always test the more complicated\n> > +\t * case (free running counters won't need the loop).\n> > +\t */\n> > +\tfor (i = 0; i < pmu_dev->num_counters; i++)\n> > +\t\tif (cmpxchg(&pmu_dev->events[i], event, NULL) == event)\n> > +\t\t\tbreak;\n> > +\n> > +\tperf_event_update_userpage(event);\n> > +\thwc->idx = -1;\n> > +}\n> > +\n> > +static ssize_t cvm_pmu_event_sysfs_show(struct device *dev,\n> > +\t\t\t\t\tstruct device_attribute *attr,\n> > +\t\t\t\t\tchar *page)\n> > +{\n> > +\tstruct perf_pmu_events_attr *pmu_attr =\n> > +\t\tcontainer_of(attr, struct perf_pmu_events_attr, attr);\n> > +\n> > +\tif (pmu_attr->event_str)\n> > +\t\treturn sprintf(page, \"%s\", pmu_attr->event_str);\n> > +\n> > +\treturn 0;\n> > +}\n> > +\n> > +/*\n> > + * The pmu events are independent from CPUs. Provide a cpumask\n> > + * nevertheless to prevent perf from adding the event per-cpu and just\n> > + * set the mask to one online CPU. Use the same cpumask for all \"uncore\"\n> > + * devices.\n> > + *\n> > + * There is a performance penalty for accessing a device from a CPU on\n> > + * another socket, but we do not care.\n> > + */\n> > +static int cvm_pmu_offline_cpu(unsigned int old_cpu, struct hlist_node *node)\n> > +{\n> > +\tstruct cvm_pmu_dev *pmu_dev;\n> > +\tint new_cpu;\n> \n> unsigned int?\n\nI don't think we gonna overflow signed int soon, or? \n\n> > +\n> > +\tpmu_dev = hlist_entry_safe(node, struct cvm_pmu_dev, cpuhp_node);\n> > +\tif (!cpumask_test_and_clear_cpu(old_cpu, &pmu_dev->active_mask))\n> > +\t\treturn 0;\n> > +\n> > +\tnew_cpu = cpumask_any_but(cpu_online_mask, old_cpu);\n> > +\tif (new_cpu >= nr_cpu_ids)\n> > +\t\treturn 0;\n> > +\n> > +\tperf_pmu_migrate_context(&pmu_dev->pmu, old_cpu, new_cpu);\n> > +\tcpumask_set_cpu(new_cpu, &pmu_dev->active_mask);\n> > +\n> > +\treturn 0;\n> > +}\n> > +\n> > +static ssize_t cvm_pmu_attr_show_cpumask(struct device *dev,\n> > +\t\t\t\t\t struct device_attribute *attr,\n> > +\t\t\t\t\t char *buf)\n> > +{\n> > +\tstruct pmu *pmu = dev_get_drvdata(dev);\n> > +\tstruct cvm_pmu_dev *pmu_dev = container_of(pmu, struct cvm_pmu_dev, pmu);\n> > +\n> > +\treturn cpumap_print_to_pagebuf(true, buf, &pmu_dev->active_mask);\n> > +}\n> > +\n> > +static DEVICE_ATTR(cpumask, S_IRUGO, cvm_pmu_attr_show_cpumask, NULL);\n> > +\n> > +static struct attribute *cvm_pmu_attrs[] = {\n> > +\t&dev_attr_cpumask.attr,\n> > +\tNULL,\n> > +};\n> > +\n> > +static struct attribute_group cvm_pmu_attr_group = {\n> > +\t.attrs = cvm_pmu_attrs,\n> > +};\n> > +\n> > +/*\n> > + * LMC (memory controller) counters:\n> > + * - not stoppable, always on, read-only\n> > + * - one PCI device per memory controller\n> > + */\n> > +#define LMC_CONFIG_OFFSET\t\t0x188\n> > +#define LMC_CONFIG_RESET_BIT\t\tBIT(17)\n> > +\n> > +/* LMC events */\n> > +#define LMC_EVENT_IFB_CNT\t\t0x1d0\n> > +#define LMC_EVENT_OPS_CNT\t\t0x1d8\n> > +#define LMC_EVENT_DCLK_CNT\t\t0x1e0\n> > +#define LMC_EVENT_BANK_CONFLICT1\t0x360\n> > +#define LMC_EVENT_BANK_CONFLICT2\t0x368\n> > +\n> > +#define CVM_PMU_LMC_EVENT_ATTR(_name, _id)\t\t\t\t\t\t\\\n> > +\t&((struct perf_pmu_events_attr[]) {\t\t\t\t\t\t\\\n> > +\t\t{\t\t\t\t\t\t\t\t\t\\\n> > +\t\t\t__ATTR(_name, S_IRUGO, cvm_pmu_event_sysfs_show, NULL),\t\t\\\n> > +\t\t\t_id,\t\t\t\t\t\t\t\t\\\n> > +\t\t\t\"lmc_event=\" __stringify(_id),\t\t\t\t\t\\\n> > +\t\t}\t\t\t\t\t\t\t\t\t\\\n> > +\t})[0].attr.attr\n> > +\n> > +/* map counter numbers to register offsets */\n> > +static int lmc_events[] = {\n> \n> Add const?\n\nYes.\n\n> > +\tLMC_EVENT_IFB_CNT,\n> > +\tLMC_EVENT_OPS_CNT,\n> > +\tLMC_EVENT_DCLK_CNT,\n> > +\tLMC_EVENT_BANK_CONFLICT1,\n> > +\tLMC_EVENT_BANK_CONFLICT2,\n> > +};\n> > +\n> > +static int cvm_pmu_lmc_add(struct perf_event *event, int flags)\n> > +{\n> > +\tstruct hw_perf_event *hwc = &event->hw;\n> > +\n> > +\treturn cvm_pmu_add(event, flags, LMC_CONFIG_OFFSET,\n> > +\t\t\t lmc_events[hwc->config]);\n> > +}\n> > +\n> > +PMU_FORMAT_ATTR(lmc_event, \"config:0-2\");\n> > +\n> > +static struct attribute *cvm_pmu_lmc_format_attr[] = {\n> > +\t&format_attr_lmc_event.attr,\n> > +\tNULL,\n> > +};\n> > +\n> > +static struct attribute_group cvm_pmu_lmc_format_group = {\n> > +\t.name = \"format\",\n> > +\t.attrs = cvm_pmu_lmc_format_attr,\n> > +};\n> > +\n> > +static struct attribute *cvm_pmu_lmc_events_attr[] = {\n> > +\tCVM_PMU_LMC_EVENT_ATTR(ifb_cnt,\t\t0),\n> > +\tCVM_PMU_LMC_EVENT_ATTR(ops_cnt,\t\t1),\n> > +\tCVM_PMU_LMC_EVENT_ATTR(dclk_cnt,\t2),\n> > +\tCVM_PMU_LMC_EVENT_ATTR(bank_conflict1,\t3),\n> > +\tCVM_PMU_LMC_EVENT_ATTR(bank_conflict2,\t4),\n> > +\tNULL,\n> > +};\n> > +\n> > +static struct attribute_group cvm_pmu_lmc_events_group = {\n> > +\t.name = \"events\",\n> > +\t.attrs = cvm_pmu_lmc_events_attr,\n> > +};\n> > +\n> > +static const struct attribute_group *cvm_pmu_lmc_attr_groups[] = {\n> > +\t&cvm_pmu_attr_group,\n> > +\t&cvm_pmu_lmc_format_group,\n> > +\t&cvm_pmu_lmc_events_group,\n> > +\tNULL,\n> > +};\n> > +\n> > +static bool cvm_pmu_lmc_event_valid(u64 config)\n> > +{\n> > +\treturn (config < ARRAY_SIZE(lmc_events));\n> > +}\n> > +\n> > +int cvm_lmc_pmu_probe(struct pci_dev *pdev, const struct pci_device_id *ent)\n> > +{\n> > +\tstruct cvm_pmu_dev *next, *lmc;\n> > +\tint nr = 0, ret = -ENOMEM;\n> > +\n> > +\tlmc = kzalloc(sizeof(*lmc), GFP_KERNEL);\n> \n> How about use devm_kzalloc?\n\nI've not used devm_kzalloc before as I didn't have a traditional device\nprobe/remove with the previous versions. I'm not sure it would work now,\nbut I'll give it a try as devm_ is really great.\n\n> > +\tif (!lmc)\n> > +\t\treturn -ENOMEM;\n> > +\n> > +\tlmc->map = ioremap(pci_resource_start(pdev, 0),\n> > +\t\t\t pci_resource_len(pdev, 0));\n> > +\tif (!lmc->map)\n> > +\t\tgoto fail_ioremap;\n> > +\n> > +\tlist_for_each_entry(next, &cvm_pmu_lmcs, entry)\n> > +\t\tnr++;\n> > +\tlmc->pmu_name = kasprintf(GFP_KERNEL, \"lmc%d\", nr);\n> \n> Use devm_kasprintf, simplify fail handle and memory free?\n> \n> > +\tif (!lmc->pmu_name)\n> > +\t\tgoto fail_kasprintf;\n> > +\n> > +\tlmc->pdev = pdev;\n> > +\tlmc->num_counters = ARRAY_SIZE(lmc_events);\n> > +\tlmc->pmu = (struct pmu) {\n> > +\t\t.task_ctx_nr = perf_invalid_context,\n> > +\t\t.event_init\t= cvm_pmu_event_init,\n> > +\t\t.add\t\t= cvm_pmu_lmc_add,\n> > +\t\t.del\t\t= cvm_pmu_del,\n> > +\t\t.start\t\t= cvm_pmu_start,\n> > +\t\t.stop\t\t= cvm_pmu_stop,\n> > +\t\t.read\t\t= cvm_pmu_read,\n> > +\t\t.attr_groups\t= cvm_pmu_lmc_attr_groups,\n> > +\t};\n> > +\n> > +\tcpuhp_state_add_instance_nocalls(CPUHP_AP_PERF_ARM_CVM_ONLINE,\n> > +\t\t\t\t\t &lmc->cpuhp_node);\n> > +\n> > +\t/*\n> > +\t * perf PMU is CPU dependent so pick a random CPU and migrate away\n> > +\t * if it goes offline.\n> > +\t */\n> > +\tcpumask_set_cpu(smp_processor_id(), &lmc->active_mask);\n> > +\n> > +\tlist_add(&lmc->entry, &cvm_pmu_lmcs);\n> > +\tlmc->event_valid = cvm_pmu_lmc_event_valid;\n> > +\n> > +\tret = perf_pmu_register(&lmc->pmu, lmc->pmu_name, -1);\n> > +\tif (ret)\n> > +\t\tgoto fail_pmu;\n> > +\n> > +\tdev_info(&pdev->dev, \"Enabled %s PMU with %d counters\\n\",\n> > +\t\t lmc->pmu_name, lmc->num_counters);\n> \n> Blank line?\n\nOK\n\n> > +\treturn 0;\n> > +\n> > +fail_pmu:\n> > +\tkfree(lmc->pmu_name);\n> > +\tcpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_CVM_ONLINE,\n> > +\t\t\t\t &lmc->cpuhp_node);\n> > +fail_kasprintf:\n> > +\tiounmap(lmc->map);\n> > +fail_ioremap:\n> > +\tkfree(lmc);\n> > +\treturn ret;\n> > +}\n> > +EXPORT_SYMBOL_GPL(cvm_lmc_pmu_probe);\n> > +\n> > +void cvm_lmc_pmu_remove(struct pci_dev *pdev)\n> > +{\n> > +\tstruct list_head *l, *tmp;\n> > +\tstruct cvm_pmu_dev *lmc;\n> > +\n> > +\tlist_for_each_safe(l, tmp, &cvm_pmu_lmcs) {\n> > +\t\tlmc = list_entry(l, struct cvm_pmu_dev, entry);\n> > +\t\tif (pdev != lmc->pdev)\n> > +\t\t\tcontinue;\n> > +\n> > +\t\tperf_pmu_unregister(&lmc->pmu);\n> > +\t\tiounmap(lmc->map);\n> > +\t\tcpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_CVM_ONLINE,\n> > +\t\t\t\t\t &lmc->cpuhp_node);\n> > +\t\tlist_del(&lmc->entry);\n> > +\t\tkfree(lmc->pmu_name);\n> > +\t\tkfree(lmc);\n> > +\t}\n> > +}\n> > +EXPORT_SYMBOL_GPL(cvm_lmc_pmu_remove);\n> > +\n> > +static int __init cvm_pmu_init(void)\n> > +{\n> > +\tINIT_LIST_HEAD(&cvm_pmu_lmcs);\n> > +\tINIT_LIST_HEAD(&cvm_pmu_tlks);\n> > +\n> > +\treturn cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_CVM_ONLINE,\n> > +\t\t\t\t \"perf/arm/cvm:online\", NULL,\n> > +\t\t\t\t cvm_pmu_offline_cpu);\n> > +}\n> > +\n> > +static void __exit cvm_pmu_exit(void)\n> > +{\n> > +\tcpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CVM_ONLINE);\n> > +}\n> > +\n> > +module_init(cvm_pmu_init);\n> > +module_exit(cvm_pmu_exit);\n> > +\n> > +MODULE_LICENSE(\"GPL v2\");\n> > +MODULE_AUTHOR(\"Cavium, Inc.\");\n> > +MODULE_DESCRIPTION(\"PMU Driver for Cavium ThunderX SOC\");\n> > diff --git a/drivers/soc/cavium/cavium_lmc.c b/drivers/soc/cavium/cavium_lmc.c\n> > index 87248e8..d21d59c 100644\n> > --- a/drivers/soc/cavium/cavium_lmc.c\n> > +++ b/drivers/soc/cavium/cavium_lmc.c\n> > @@ -17,6 +17,8 @@\n> > static int cvm_lmc_probe(struct pci_dev *pdev,\n> > \t\t\t const struct pci_device_id *ent)\n> > {\n> > +\tif (IS_ENABLED(CONFIG_CAVIUM_PMU_LMC))\n> > +\t\tcvm_lmc_pmu_probe(pdev, ent);\n> > \tif (IS_ENABLED(CONFIG_EDAC_THUNDERX))\n> > \t\tthunderx_edac_lmc_probe(pdev, ent);\n> > \treturn 0;\n> > @@ -24,6 +26,8 @@ static int cvm_lmc_probe(struct pci_dev *pdev,\n> > \n> > static void cvm_lmc_remove(struct pci_dev *pdev)\n> > {\n> > +\tif (IS_ENABLED(CONFIG_CAVIUM_PMU_LMC))\n> > +\t\tcvm_lmc_pmu_remove(pdev);\n> > \tif (IS_ENABLED(CONFIG_EDAC_THUNDERX))\n> > \t\tthunderx_edac_lmc_remove(pdev);\n> > }\n> > diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h\n> > index 82b30e6..ca84ac8 100644\n> > --- a/include/linux/cpuhotplug.h\n> > +++ b/include/linux/cpuhotplug.h\n> > @@ -139,6 +139,7 @@ enum cpuhp_state {\n> > \tCPUHP_AP_PERF_ARM_QCOM_L3_ONLINE,\n> > \tCPUHP_AP_WORKQUEUE_ONLINE,\n> > \tCPUHP_AP_RCUTREE_ONLINE,\n> > +\tCPUHP_AP_PERF_ARM_CVM_ONLINE,\n> \n> Alphabetic order?\n\nThese don't look alphabetically ordered to me.\n\nthanks, Jan\n\n> \n> > \tCPUHP_AP_ONLINE_DYN,\n> > \tCPUHP_AP_ONLINE_DYN_END\t\t= CPUHP_AP_ONLINE_DYN + 30,\n> > \tCPUHP_AP_X86_HPET_ONLINE,\n> > diff --git a/include/linux/soc/cavium/lmc.h b/include/linux/soc/cavium/lmc.h\n> > index 336f467..e5ad650 100644\n> > --- a/include/linux/soc/cavium/lmc.h\n> > +++ b/include/linux/soc/cavium/lmc.h\n> > @@ -3,6 +3,9 @@\n> > \n> > #include \n> > \n> > +int cvm_lmc_pmu_probe(struct pci_dev *pdev, const struct pci_device_id *ent);\n> > +void cvm_lmc_pmu_remove(struct pci_dev *pdev);\n> > +\n> > int thunderx_edac_lmc_probe(struct pci_dev *pdev, const struct pci_device_id *ent);\n> > void thunderx_edac_lmc_remove(struct pci_dev *pdev);\n> > \n> >","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"RQmqQJGh\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) 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PMU\n\tcounters","Message-ID":"<20170831095746.GB15906@hc>","References":"<20170829131238.4988-1-jglauber@cavium.com>\n\t<20170829131238.4988-6-jglauber@cavium.com>\n\t","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"","User-Agent":"Mutt/1.5.21 (2010-09-15)","X-Originating-IP":"[88.67.130.225]","X-ClientProxiedBy":"HE1PR0202CA0004.eurprd02.prod.outlook.com (10.168.182.14)\n\tTo CO2PR07MB2583.namprd07.prod.outlook.com (10.166.201.22)","X-MS-PublicTrafficType":"Email","X-MS-Office365-Filtering-Correlation-Id":"e8440762-8a13-442a-51f7-08d4f056c46c","X-Microsoft-Antispam":"UriScan:; BCL:0; PCL:0;\n\tRULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(2017030254152)(300000503095)(300135400095)(2017052603199)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);\n\tSRVR:CO2PR07MB2583; ","X-Microsoft-Exchange-Diagnostics":["1; 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","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1760818,"web_url":"http://patchwork.ozlabs.org/comment/1760818/","msgid":"<20170831103119.GC15031@leverpostej>","list_archive_url":null,"date":"2017-08-31T10:31:20","subject":"Re: [RFC PATCH v9 5/7] perf: cavium: Support memory controller PMU\n\tcounters","submitter":{"id":8806,"url":"http://patchwork.ozlabs.org/api/people/8806/","name":"Mark Rutland","email":"mark.rutland@arm.com"},"content":"On Thu, Aug 31, 2017 at 11:57:46AM +0200, Jan Glauber wrote:\n> On Wed, Aug 30, 2017 at 10:54:03AM +0800, Zhangshaokun wrote:\n> > On 2017/8/29 21:12, Jan Glauber wrote:\n> > > Add support for the PMU counters on Cavium SOC memory controllers.\n> > > \n> > > This patch also adds generic functions to allow supporting more\n> > > devices with PMU counters.\n\n> > > +/* generic struct to cover the different pmu types */\n> > > +struct cvm_pmu_dev {\n> > > +\tstruct pmu pmu;\n> > > +\tconst char *pmu_name;\n> > \n> > It seems that pmu_name is redundant since struct pmu has a name field,\n> > Mark has mentioned it in HiSilicon uncore PMU driver, Link:\n> > https://patchwork.kernel.org/patch/9861821/\n> \n> I don't get it. perf_pmu_register() just copies the char* from the\n> argument into pmu->name. Somewhere the string must be allocated.\n> That's why I have cvm_pmu_dev->pmu_name.\n\nI'm not sure I follow. cvm_pmu_dev->pmu_name is just a char *, so what\ndoes that have to do with allocation?\n\n... unless you mean you want to allocate this in some variant-specific\ncode prior to passing it to code which calls perf_pmu_register(), and\nyou just need a place to stash it in the mean time?\n\n> > > diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h\n> > > index 82b30e6..ca84ac8 100644\n> > > --- a/include/linux/cpuhotplug.h\n> > > +++ b/include/linux/cpuhotplug.h\n> > > @@ -139,6 +139,7 @@ enum cpuhp_state {\n> > > \tCPUHP_AP_PERF_ARM_QCOM_L3_ONLINE,\n> > > \tCPUHP_AP_WORKQUEUE_ONLINE,\n> > > \tCPUHP_AP_RCUTREE_ONLINE,\n> > > +\tCPUHP_AP_PERF_ARM_CVM_ONLINE,\n> > \n> > Alphabetic order?\n> \n> These don't look alphabetically ordered to me.\n\nSure, the full list is ordered by dependency.\n\nHowever, we've generally kept the uncore PMUs together, and within the\ngroup of system PMU CPUHP_AP_PERF_ARM_* callbacks, we've retained\nalphabetical order.\n\nDoes this PMU need workqueues and RCU up before its HP callback is\ninvoked? Or can this be moved into the group of CPUHP_AP_PERF_ARM_*\nabove CPUHP_AP_WORKQUEUE_ONLINE and CPUHP_AP_RCUTREE_ONLINE? i.e.\nbetween CPUHP_AP_PERF_ARM_CCN_ONLINE and CPUHP_AP_PERF_ARM_L2X0_ONLINE.\n\nTHanks,\nMark.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"nQ9DNYo5\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjdxY45Bjz9sPt\n\tfor ;\n\tThu, 31 Aug 2017 20:33:05 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dnMmU-0002IL-EA; Thu, 31 Aug 2017 10:33:02 +0000","from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]\n\thelo=foss.arm.com)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dnMmQ-0002Gp-0i for linux-arm-kernel@lists.infradead.org;\n\tThu, 31 Aug 2017 10:32:59 +0000","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 66B1280D;\n\tThu, 31 Aug 2017 03:32:37 -0700 (PDT)","from leverpostej (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\tC5BCE3F58F; Thu, 31 Aug 2017 03:32:35 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=vSISGL1enbdOiVkLsbWGqC0ilekkcQSi2WjPUJwXvLA=;\n\tb=nQ9DNYo51NHIvi\n\t7NK8lNr7S5++DZEAPP4PJhudMMd0emFpJI4PLYJslE7NJs4kWHqm08A3gWcfS0F5L3HcmiuRaR0G3\n\tKtTz4PRbZ3lVJZFylwJ+91Y1N1R19DOHXH1xKFkUygiNMRwLkbPFgotRRQYzE1pmS7ZH6MWVZ2ZJZ\n\tABiK3ldvZj+yvWWIVzdp/vZKIpogCISpEeXfCkt+dWqE7X3bQ135Y12+w+xUwYPsdg6YpubA7tswV\n\tsGwqLhJ+gfRcdeYEKY963g5XMaXIZD7RJSCGHjC/O+sXz9dYRbFyMcIvzVECTDhvqi53KtI1W0Dow\n\tw0dNvQLtjot1ozxIuW+Q==;","Date":"Thu, 31 Aug 2017 11:31:20 +0100","From":"Mark Rutland ","To":"Jan Glauber ","Subject":"Re: [RFC PATCH v9 5/7] perf: cavium: Support memory controller PMU\n\tcounters","Message-ID":"<20170831103119.GC15031@leverpostej>","References":"<20170829131238.4988-1-jglauber@cavium.com>\n\t<20170829131238.4988-6-jglauber@cavium.com>\n\t\n\t<20170831095746.GB15906@hc>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<20170831095746.GB15906@hc>","User-Agent":"Mutt/1.5.21 (2010-09-15)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170831_033258_076176_0A55CD9B ","X-CRM114-Status":"GOOD ( 19.80 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Suzuki K Poulose ,\n\tDavid Daney , Will Deacon , \n\tlinux-kernel@vger.kernel.org, Zhangshaokun , \n\tBorislav Petkov , linux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1760836,"web_url":"http://patchwork.ozlabs.org/comment/1760836/","msgid":"<20170831111359.GC15906@hc>","list_archive_url":null,"date":"2017-08-31T11:13:59","subject":"Re: [RFC PATCH v9 5/7] perf: cavium: Support memory controller PMU\n\tcounters","submitter":{"id":68474,"url":"http://patchwork.ozlabs.org/api/people/68474/","name":"Jan Glauber","email":"jan.glauber@caviumnetworks.com"},"content":"On Thu, Aug 31, 2017 at 11:31:20AM +0100, Mark Rutland wrote:\n> On Thu, Aug 31, 2017 at 11:57:46AM +0200, Jan Glauber wrote:\n> > On Wed, Aug 30, 2017 at 10:54:03AM +0800, Zhangshaokun wrote:\n> > > On 2017/8/29 21:12, Jan Glauber wrote:\n> > > > Add support for the PMU counters on Cavium SOC memory controllers.\n> > > > \n> > > > This patch also adds generic functions to allow supporting more\n> > > > devices with PMU counters.\n> \n> > > > +/* generic struct to cover the different pmu types */\n> > > > +struct cvm_pmu_dev {\n> > > > +\tstruct pmu pmu;\n> > > > +\tconst char *pmu_name;\n> > > \n> > > It seems that pmu_name is redundant since struct pmu has a name field,\n> > > Mark has mentioned it in HiSilicon uncore PMU driver, Link:\n> > > https://patchwork.kernel.org/patch/9861821/\n> > \n> > I don't get it. perf_pmu_register() just copies the char* from the\n> > argument into pmu->name. Somewhere the string must be allocated.\n> > That's why I have cvm_pmu_dev->pmu_name.\n> \n> I'm not sure I follow. cvm_pmu_dev->pmu_name is just a char *, so what\n> does that have to do with allocation?\n\nAs you pointed out here:\nhttps://lkml.org/lkml/2017/6/2/530\nperf_pmu_register does not copy the string, so _somewhere_ the name must\nbe allocated and freed afterwards. Are you suggesting to use pmu.name\ndirectly to allocate the name there and pass\nperf_register_pmu(..., tlk->pmu.name, ...)?\n\n--Jan\n\n> ... unless you mean you want to allocate this in some variant-specific\n> code prior to passing it to code which calls perf_pmu_register(), and\n> you just need a place to stash it in the mean time?\n\n\n\n[...]\n\n> THanks,\n> Mark.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"J+93Qo77\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=CAVIUMNETWORKS.onmicrosoft.com\n\theader.i=@CAVIUMNETWORKS.onmicrosoft.com header.b=\"eUAh85tU\"; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1760837,"web_url":"http://patchwork.ozlabs.org/comment/1760837/","msgid":"<20170831111827.GD15906@hc>","list_archive_url":null,"date":"2017-08-31T11:18:27","subject":"Re: [RFC PATCH v9 5/7] perf: cavium: Support memory controller PMU\n\tcounters","submitter":{"id":68474,"url":"http://patchwork.ozlabs.org/api/people/68474/","name":"Jan Glauber","email":"jan.glauber@caviumnetworks.com"},"content":"On Thu, Aug 31, 2017 at 11:31:20AM +0100, Mark Rutland wrote:\n> On Thu, Aug 31, 2017 at 11:57:46AM +0200, Jan Glauber wrote:\n> > On Wed, Aug 30, 2017 at 10:54:03AM +0800, Zhangshaokun wrote:\n> > > On 2017/8/29 21:12, Jan Glauber wrote:\n\n[...]\n\n> > > > diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h\n> > > > index 82b30e6..ca84ac8 100644\n> > > > --- a/include/linux/cpuhotplug.h\n> > > > +++ b/include/linux/cpuhotplug.h\n> > > > @@ -139,6 +139,7 @@ enum cpuhp_state {\n> > > > \tCPUHP_AP_PERF_ARM_QCOM_L3_ONLINE,\n> > > > \tCPUHP_AP_WORKQUEUE_ONLINE,\n> > > > \tCPUHP_AP_RCUTREE_ONLINE,\n> > > > +\tCPUHP_AP_PERF_ARM_CVM_ONLINE,\n> > > \n> > > Alphabetic order?\n> > \n> > These don't look alphabetically ordered to me.\n> \n> Sure, the full list is ordered by dependency.\n> \n> However, we've generally kept the uncore PMUs together, and within the\n> group of system PMU CPUHP_AP_PERF_ARM_* callbacks, we've retained\n> alphabetical order.\n> \n> Does this PMU need workqueues and RCU up before its HP callback is\n> invoked? Or can this be moved into the group of CPUHP_AP_PERF_ARM_*\n> above CPUHP_AP_WORKQUEUE_ONLINE and CPUHP_AP_RCUTREE_ONLINE? i.e.\n> between CPUHP_AP_PERF_ARM_CCN_ONLINE and CPUHP_AP_PERF_ARM_L2X0_ONLINE.\n\nI think I can move it inside the CPUHP_AP_PERF_ARM_* group.\n\n--Jan\n\n> THanks,\n> Mark.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"Uqr4L3gq\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=CAVIUMNETWORKS.onmicrosoft.com\n\theader.i=@CAVIUMNETWORKS.onmicrosoft.com header.b=\"CQa5GB/1\"; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1760846,"web_url":"http://patchwork.ozlabs.org/comment/1760846/","msgid":"<20170831113508.GE15906@hc>","list_archive_url":null,"date":"2017-08-31T11:35:08","subject":"Re: [RFC PATCH v9 5/7] perf: cavium: Support memory controller PMU\n\tcounters","submitter":{"id":68474,"url":"http://patchwork.ozlabs.org/api/people/68474/","name":"Jan Glauber","email":"jan.glauber@caviumnetworks.com"},"content":"On Wed, Aug 30, 2017 at 11:03:00AM +0100, Suzuki K Poulose wrote:\n> On 29/08/17 14:12, Jan Glauber wrote:\n> >Add support for the PMU counters on Cavium SOC memory controllers.\n> >\n> >This patch also adds generic functions to allow supporting more\n> >devices with PMU counters.\n> >\n> >Properties of the LMC PMU counters:\n> >- not stoppable\n> >- fixed purpose\n> >- read-only\n> >- one PCI device per memory controller\n> >\n> >Signed-off-by: Jan Glauber \n> \n> Jan,\n> \n> Some minor comments below.\n> \n> >+static void cvm_pmu_del(struct perf_event *event, int flags)\n> >+{\n> >+\tstruct cvm_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);\n> >+\tstruct hw_perf_event *hwc = &event->hw;\n> >+\tint i;\n> >+\n> >+\tevent->pmu->stop(event, PERF_EF_UPDATE);\n> >+\n> >+\t/*\n> >+\t * For programmable counters we need to check where we installed it.\n> >+\t * To keep this function generic always test the more complicated\n> >+\t * case (free running counters won't need the loop).\n> >+\t */\n> >+\tfor (i = 0; i < pmu_dev->num_counters; i++)\n> >+\t\tif (cmpxchg(&pmu_dev->events[i], event, NULL) == event)\n> >+\t\t\tbreak;\n> \n> Does this mean, it is the only way to map any given event (for programmable counters)\n> to a hardware counter ? What do we store in hwc->idx ? We have 2 additional\n> struct hw_perf_event_extra fields. We should be able to use one field to map it\n> back to the counter, isn't it ?\n\nHmm, I might be able to use hwc-idx directly instead of the loop, will\ncheck that.\n\n> >+\n> >+\tperf_event_update_userpage(event);\n> >+\thwc->idx = -1;\n> >+}\n> >+\n> \n> ...\n> \n> >+/* LMC events */\n> >+#define LMC_EVENT_IFB_CNT\t\t0x1d0\n> >+#define LMC_EVENT_OPS_CNT\t\t0x1d8\n> >+#define LMC_EVENT_DCLK_CNT\t\t0x1e0\n> >+#define LMC_EVENT_BANK_CONFLICT1\t0x360\n> >+#define LMC_EVENT_BANK_CONFLICT2\t0x368\n> >+\n> >+#define CVM_PMU_LMC_EVENT_ATTR(_name, _id)\t\t\t\t\t\t\\\n> >+\t&((struct perf_pmu_events_attr[]) {\t\t\t\t\t\t\\\n> >+\t\t{\t\t\t\t\t\t\t\t\t\\\n> >+\t\t\t__ATTR(_name, S_IRUGO, cvm_pmu_event_sysfs_show, NULL),\t\t\\\n> >+\t\t\t_id,\t\t\t\t\t\t\t\t\\\n> >+\t\t\t\"lmc_event=\" __stringify(_id),\t\t\t\t\t\\\n> >+\t\t}\t\t\t\t\t\t\t\t\t\\\n> >+\t})[0].attr.attr\n> >+\n> >+/* map counter numbers to register offsets */\n> >+static int lmc_events[] = {\n> >+\tLMC_EVENT_IFB_CNT,\n> >+\tLMC_EVENT_OPS_CNT,\n> >+\tLMC_EVENT_DCLK_CNT,\n> >+\tLMC_EVENT_BANK_CONFLICT1,\n> >+\tLMC_EVENT_BANK_CONFLICT2,\n> >+};\n> >+\n> >+static int cvm_pmu_lmc_add(struct perf_event *event, int flags)\n> >+{\n> >+\tstruct hw_perf_event *hwc = &event->hw;\n> >+\n> >+\treturn cvm_pmu_add(event, flags, LMC_CONFIG_OFFSET,\n> >+\t\t\t lmc_events[hwc->config]);\n> >+}\n> >+\n> \n> Is there any reason why we can't use the LMC event code directly\n> here, avoiding the mapping altogether ?\n\nI wanted to avoid exposing the raw numbers (0x1d0 - 0x368) here.\n\nthanks,\nJan\n\n> >+PMU_FORMAT_ATTR(lmc_event, \"config:0-2\");\n> >+\n> >+static struct attribute *cvm_pmu_lmc_format_attr[] = {\n> >+\t&format_attr_lmc_event.attr,\n> >+\tNULL,\n> >+};\n> >+\n> >+static struct attribute_group cvm_pmu_lmc_format_group = {\n> >+\t.name = \"format\",\n> >+\t.attrs = cvm_pmu_lmc_format_attr,\n> >+};\n> >+\n> >+static struct attribute *cvm_pmu_lmc_events_attr[] = {\n> >+\tCVM_PMU_LMC_EVENT_ATTR(ifb_cnt,\t\t0),\n> >+\tCVM_PMU_LMC_EVENT_ATTR(ops_cnt,\t\t1),\n> >+\tCVM_PMU_LMC_EVENT_ATTR(dclk_cnt,\t2),\n> >+\tCVM_PMU_LMC_EVENT_ATTR(bank_conflict1,\t3),\n> >+\tCVM_PMU_LMC_EVENT_ATTR(bank_conflict2,\t4),\n> >+\tNULL,\n> >+};","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1760857,"web_url":"http://patchwork.ozlabs.org/comment/1760857/","msgid":"<20170831113803.GF15906@hc>","list_archive_url":null,"date":"2017-08-31T11:38:03","subject":"Re: [RFC PATCH v9 0/7] Cavium ARM64 uncore PMU support","submitter":{"id":68474,"url":"http://patchwork.ozlabs.org/api/people/68474/","name":"Jan Glauber","email":"jan.glauber@caviumnetworks.com"},"content":"So what about the general idea with the wrapper, does this look sane?\nAny objections to that?\n\nthanks,\nJan\n\nOn Tue, Aug 29, 2017 at 03:12:31PM +0200, Jan Glauber wrote:\n> I'm posting this as RFC following this discussion:\n> https://marc.info/?l=linux-arm-kernel&m=150099526923838&w=2\n> \n> I've implemented the wrapper for the PCI devices and put it under\n> drivers/soc/cavium which I found more appropriate than drivers/misc.\n> \n> I was not able to find a way to build the EDAC driver and the PMU driver\n> with all combinations (builtin and module) so I limited the build options\n> to module only. The problem is that the select from EDAC or PMU\n> sets the wrappers build type to whatever EDAC or PMU choose.\n> But all parts must be either built-in or modules, having the wrapper\n> builtin and calling into module code will not work. If there is a better\n> solution please let me know.\n> \n> The PMU code is the same as in v8.\n> \n> Add support for various PMU counters found on the Cavium ThunderX and\n> OcteonTx SoC.\n> \n> The PMU driver provides common \"uncore\" functions to avoid code duplication\n> and support adding more device PMUs (like L2 cache) in the future.\n> \n> Changes to v8:\n> - Wrapper for PCI devices\n> \n> Jan Glauber (7):\n> edac: thunderx: Remove suspend/resume support\n> edac,soc: thunderx: Add wrapper for EDAC LMC PCI device\n> edac,soc: thunderx: Add wrapper for EDAC OCX PCI device\n> perf: export perf_event_update_userpage()\n> perf: cavium: Support memory controller PMU counters\n> perf: cavium: Support transmit-link PMU counters\n> perf: cavium: Add Documentation\n> \n> Documentation/perf/cavium-pmu.txt | 75 +++++\n> drivers/edac/Kconfig | 3 +\n> drivers/edac/thunderx_edac.c | 92 +-----\n> drivers/perf/Kconfig | 15 +\n> drivers/perf/Makefile | 1 +\n> drivers/perf/cavium_pmu.c | 680 ++++++++++++++++++++++++++++++++++++++\n> drivers/soc/Kconfig | 1 +\n> drivers/soc/Makefile | 1 +\n> drivers/soc/cavium/Kconfig | 14 +\n> drivers/soc/cavium/Makefile | 2 +\n> drivers/soc/cavium/cavium_lmc.c | 53 +++\n> drivers/soc/cavium/cavium_ocx.c | 49 +++\n> include/linux/cpuhotplug.h | 1 +\n> include/linux/soc/cavium/lmc.h | 12 +\n> include/linux/soc/cavium/ocx.h | 12 +\n> kernel/events/core.c | 1 +\n> 16 files changed, 933 insertions(+), 79 deletions(-)\n> create mode 100644 Documentation/perf/cavium-pmu.txt\n> create mode 100644 drivers/perf/cavium_pmu.c\n> create mode 100644 drivers/soc/cavium/Kconfig\n> create mode 100644 drivers/soc/cavium/Makefile\n> create mode 100644 drivers/soc/cavium/cavium_lmc.c\n> create mode 100644 drivers/soc/cavium/cavium_ocx.c\n> create mode 100644 include/linux/soc/cavium/lmc.h\n> create mode 100644 include/linux/soc/cavium/ocx.h\n> \n> -- \n> 2.9.0.rc0.21.g7777322","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1760988,"web_url":"http://patchwork.ozlabs.org/comment/1760988/","msgid":"","list_archive_url":null,"date":"2017-08-31T13:26:22","subject":"Re: [RFC PATCH v9 5/7] perf: cavium: Support memory controller PMU\n\tcounters","submitter":{"id":65822,"url":"http://patchwork.ozlabs.org/api/people/65822/","name":"Suzuki K Poulose","email":"suzuki.poulose@arm.com"},"content":"On 31/08/17 12:35, Jan Glauber wrote:\n> On Wed, Aug 30, 2017 at 11:03:00AM +0100, Suzuki K Poulose wrote:\n>> On 29/08/17 14:12, Jan Glauber wrote:\n>>> Add support for the PMU counters on Cavium SOC memory controllers.\n>>>\n>>> This patch also adds generic functions to allow supporting more\n>>> devices with PMU counters.\n>>>\n>>> Properties of the LMC PMU counters:\n>>> - not stoppable\n>>> - fixed purpose\n>>> - read-only\n>>> - one PCI device per memory controller\n>>>\n>>> Signed-off-by: Jan Glauber \n>>\n>> Jan,\n>>\n>> Some minor comments below.\n>>\n>>> +static void cvm_pmu_del(struct perf_event *event, int flags)\n>>> +{\n>>> +\tstruct cvm_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);\n>>> +\tstruct hw_perf_event *hwc = &event->hw;\n>>> +\tint i;\n>>> +\n>>> +\tevent->pmu->stop(event, PERF_EF_UPDATE);\n>>> +\n>>> +\t/*\n>>> +\t * For programmable counters we need to check where we installed it.\n>>> +\t * To keep this function generic always test the more complicated\n>>> +\t * case (free running counters won't need the loop).\n>>> +\t */\n>>> +\tfor (i = 0; i < pmu_dev->num_counters; i++)\n>>> +\t\tif (cmpxchg(&pmu_dev->events[i], event, NULL) == event)\n>>> +\t\t\tbreak;\n>>\n>> Does this mean, it is the only way to map any given event (for programmable counters)\n>> to a hardware counter ? What do we store in hwc->idx ? We have 2 additional\n>> struct hw_perf_event_extra fields. We should be able to use one field to map it\n>> back to the counter, isn't it ?\n>\n> Hmm, I might be able to use hwc-idx directly instead of the loop, will\n> check that.\n>\n>>> +\n>>> +\tperf_event_update_userpage(event);\n>>> +\thwc->idx = -1;\n>>> +}\n>>> +\n>>\n>> ...\n>>\n>>> +/* LMC events */\n>>> +#define LMC_EVENT_IFB_CNT\t\t0x1d0\n>>> +#define LMC_EVENT_OPS_CNT\t\t0x1d8\n>>> +#define LMC_EVENT_DCLK_CNT\t\t0x1e0\n>>> +#define LMC_EVENT_BANK_CONFLICT1\t0x360\n>>> +#define LMC_EVENT_BANK_CONFLICT2\t0x368\n>>> +\n>>> +#define CVM_PMU_LMC_EVENT_ATTR(_name, _id)\t\t\t\t\t\t\\\n>>> +\t&((struct perf_pmu_events_attr[]) {\t\t\t\t\t\t\\\n>>> +\t\t{\t\t\t\t\t\t\t\t\t\\\n>>> +\t\t\t__ATTR(_name, S_IRUGO, cvm_pmu_event_sysfs_show, NULL),\t\t\\\n>>> +\t\t\t_id,\t\t\t\t\t\t\t\t\\\n>>> +\t\t\t\"lmc_event=\" __stringify(_id),\t\t\t\t\t\\\n>>> +\t\t}\t\t\t\t\t\t\t\t\t\\\n>>> +\t})[0].attr.attr\n>>> +\n>>> +/* map counter numbers to register offsets */\n>>> +static int lmc_events[] = {\n>>> +\tLMC_EVENT_IFB_CNT,\n>>> +\tLMC_EVENT_OPS_CNT,\n>>> +\tLMC_EVENT_DCLK_CNT,\n>>> +\tLMC_EVENT_BANK_CONFLICT1,\n>>> +\tLMC_EVENT_BANK_CONFLICT2,\n>>> +};\n>>> +\n>>> +static int cvm_pmu_lmc_add(struct perf_event *event, int flags)\n>>> +{\n>>> +\tstruct hw_perf_event *hwc = &event->hw;\n>>> +\n>>> +\treturn cvm_pmu_add(event, flags, LMC_CONFIG_OFFSET,\n>>> +\t\t\t lmc_events[hwc->config]);\n>>> +}\n>>> +\n>>\n>> Is there any reason why we can't use the LMC event code directly\n>> here, avoiding the mapping altogether ?\n>\n> I wanted to avoid exposing the raw numbers (0x1d0 - 0x368) here.\n\nThats the primarily the reason why we expose the \"aliases\" in events/.\nThe other problem with adding another layer of mapping is, you are preventing\nsomeone from actually mapping the raw code used by the perf tool (which is now\na mapping index) to the real raw code used by the hardware unless they have\nthe kernel source handy. If you choose to expose the raw numbers, like *all*\nthe other PMUs, the user can map it by looking up the manual.\n\nCheers\nSuzuki","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"Q4GBq+1b\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjjp43Zcrz9sPt\n\tfor ;\n\tThu, 31 Aug 2017 23:26:52 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dnPUf-0006F6-OH; Thu, 31 Aug 2017 13:26:49 +0000","from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]\n\thelo=foss.arm.com)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dnPUb-0005uh-NI for linux-arm-kernel@lists.infradead.org;\n\tThu, 31 Aug 2017 13:26:47 +0000","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 315742B;\n\tThu, 31 Aug 2017 06:26:25 -0700 (PDT)","from [10.1.206.28] (e107814-lin.cambridge.arm.com [10.1.206.28])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\tD80DF3F540; Thu, 31 Aug 2017 06:26:23 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type:\n\tContent-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive:\n\tList-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From:\n\tReferences:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;\n\tbh=FGtP5s+7tKr2AJ2+UEXWhg6M8pivOJodxHvuiUbX7vY=;\n\tb=Q4GBq+1b7U8/kkq6MA3WQyPU5\n\tKvK9bQF1pdEhsYHNNG3+r/q2SEflK2x9v2YsdwBhT3g+iN613oxPjFCgBWJ6JjMMqSW0IbY1b3fHd\n\tkls0GmXfuJZaBIWgNOntEhlpyCBsJI8hcuWwgWx+yhJ+vreswxIbVE4o4XkZa2ljBcUsQ7uLrVSG/\n\teT4zVE51E2heuSZ9WHe17oUHskuMkVLJYZCcLNNLmPi//JB/+1FRQ963aN1t67mHjmPCaJ8/G5fld\n\tnphmLobk/sDv8/VjnIGPnwEDpVlwklju741aJZae/ANhwzqLZLQyhk+PpT7QeKEI9sworACp1Kv4T\n\t8l45PPETw==;","Subject":"Re: [RFC PATCH v9 5/7] perf: cavium: Support memory controller PMU\n\tcounters","To":"Jan Glauber ","References":"<20170829131238.4988-1-jglauber@cavium.com>\n\t<20170829131238.4988-6-jglauber@cavium.com>\n\t<09997d9f-0003-0eb0-63d1-9b31e26e2229@arm.com>\n\t<20170831113508.GE15906@hc>","From":"Suzuki K Poulose ","Message-ID":"","Date":"Thu, 31 Aug 2017 14:26:22 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.8.0","MIME-Version":"1.0","In-Reply-To":"<20170831113508.GE15906@hc>","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170831_062645_776986_EA00948B ","X-CRM114-Status":"GOOD ( 19.47 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Mark Rutland , David Daney ,\n\tWill Deacon , linux-kernel@vger.kernel.org,\n\tBorislav Petkov , linux-arm-kernel@lists.infradead.org","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1761118,"web_url":"http://patchwork.ozlabs.org/comment/1761118/","msgid":"<20170831152723.GA23982@hc>","list_archive_url":null,"date":"2017-08-31T15:27:23","subject":"Re: [RFC PATCH v9 5/7] perf: cavium: Support memory controller PMU\n\tcounters","submitter":{"id":68474,"url":"http://patchwork.ozlabs.org/api/people/68474/","name":"Jan Glauber","email":"jan.glauber@caviumnetworks.com"},"content":"On Thu, Aug 31, 2017 at 02:26:22PM +0100, Suzuki K Poulose wrote:\n> On 31/08/17 12:35, Jan Glauber wrote:\n> >On Wed, Aug 30, 2017 at 11:03:00AM +0100, Suzuki K Poulose wrote:\n> >>On 29/08/17 14:12, Jan Glauber wrote:\n\n[...]\n\n> >>>+/* LMC events */\n> >>>+#define LMC_EVENT_IFB_CNT\t\t0x1d0\n> >>>+#define LMC_EVENT_OPS_CNT\t\t0x1d8\n> >>>+#define LMC_EVENT_DCLK_CNT\t\t0x1e0\n> >>>+#define LMC_EVENT_BANK_CONFLICT1\t0x360\n> >>>+#define LMC_EVENT_BANK_CONFLICT2\t0x368\n> >>>+\n> >>>+#define CVM_PMU_LMC_EVENT_ATTR(_name, _id)\t\t\t\t\t\t\\\n> >>>+\t&((struct perf_pmu_events_attr[]) {\t\t\t\t\t\t\\\n> >>>+\t\t{\t\t\t\t\t\t\t\t\t\\\n> >>>+\t\t\t__ATTR(_name, S_IRUGO, cvm_pmu_event_sysfs_show, NULL),\t\t\\\n> >>>+\t\t\t_id,\t\t\t\t\t\t\t\t\\\n> >>>+\t\t\t\"lmc_event=\" __stringify(_id),\t\t\t\t\t\\\n> >>>+\t\t}\t\t\t\t\t\t\t\t\t\\\n> >>>+\t})[0].attr.attr\n> >>>+\n> >>>+/* map counter numbers to register offsets */\n> >>>+static int lmc_events[] = {\n> >>>+\tLMC_EVENT_IFB_CNT,\n> >>>+\tLMC_EVENT_OPS_CNT,\n> >>>+\tLMC_EVENT_DCLK_CNT,\n> >>>+\tLMC_EVENT_BANK_CONFLICT1,\n> >>>+\tLMC_EVENT_BANK_CONFLICT2,\n> >>>+};\n> >>>+\n> >>>+static int cvm_pmu_lmc_add(struct perf_event *event, int flags)\n> >>>+{\n> >>>+\tstruct hw_perf_event *hwc = &event->hw;\n> >>>+\n> >>>+\treturn cvm_pmu_add(event, flags, LMC_CONFIG_OFFSET,\n> >>>+\t\t\t lmc_events[hwc->config]);\n> >>>+}\n> >>>+\n> >>\n> >>Is there any reason why we can't use the LMC event code directly\n> >>here, avoiding the mapping altogether ?\n> >\n> >I wanted to avoid exposing the raw numbers (0x1d0 - 0x368) here.\n> \n> Thats the primarily the reason why we expose the \"aliases\" in events/.\n> The other problem with adding another layer of mapping is, you are preventing\n> someone from actually mapping the raw code used by the perf tool (which is now\n> a mapping index) to the real raw code used by the hardware unless they have\n> the kernel source handy. If you choose to expose the raw numbers, like *all*\n> the other PMUs, the user can map it by looking up the manual.\n\nSo what would that do to the config bits? Currently they are:\nPMU_FORMAT_ATTR(lmc_event, \"config:0-2\");\n\nShould I have config:0-9 then? Wouldn't that be confusing as there are\nonly 5 events?\n\nAlso I need to be very careful as we need to prevent a user from\naccessing anything else then the counters. I can do that with the\nevent_valid callback though.\n\nthanks,\nJan\n\n> Cheers\n> Suzuki","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"tb4OSvJ7\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=CAVIUMNETWORKS.onmicrosoft.com\n\theader.i=@CAVIUMNETWORKS.onmicrosoft.com header.b=\"GjHDZEFI\"; \n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=Jan.Glauber@cavium.com; "],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjmV25jwHz9s83\n\tfor ;\n\tFri, 1 Sep 2017 01:28:10 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dnRO0-0002nS-93; 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