[{"id":1758715,"web_url":"http://patchwork.ozlabs.org/comment/1758715/","msgid":"","list_archive_url":null,"date":"2017-08-28T16:59:34","subject":"Re: [PATCH 0/3] DWC host without MSI controller","submitter":{"id":41730,"url":"http://patchwork.ozlabs.org/api/people/41730/","name":"Tim Harvey","email":"tharvey@gateworks.com"},"content":"On Mon, Aug 28, 2017 at 7:23 AM, Lucas Stach wrote:\n> Hi all,\n>\n> this small series tries to fix/workaround a serious design flaw of the DWC PCIe\n> host controller: it is unable to work with both legacy and MSI IRQs enabled at\n> the same time. As soon as the first MSI is enabled in the DWC MSI controller,\n> the host stops forwarding legacy IRQs.\n>\n> If the MSI controller is present, MSIs will be used for the PCIe port services\n> IRQs, leaving endpoint devices which don't support MSIs unable to raise IRQs.\n> It is only safe to enable the MSI controller if it is validated that all PCIe\n> devices and drivers in the system support working MSIs. As most devices\n> support falling back to using legacy PCIe IRQs if MSI support is missing it is\n> much safer to disable the MSI by default and only enable it on validated\n> systems.\n>\n> Feedback welcome.\n>\n> Regards,\n> Lucas\n>\n> Lucas Stach (3):\n> PCI: designware: only register MSI controller when MSI irq line is\n> valid\n> PCI: imx6: allow MSI irq to be absent\n> ARM: dts: imx6qdl: remove MSI irq line\n>\n> .../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 8 ++++----\n> arch/arm/boot/dts/imx6qdl.dtsi | 2 --\n> drivers/pci/dwc/pci-imx6.c | 23 +++++++++++-----------\n> drivers/pci/dwc/pcie-designware-host.c | 4 ++--\n> 4 files changed, 17 insertions(+), 20 deletions(-)\n>\n\nLucas,\n\nThank you for following up on this!\n\nI tested it with and without the third patch that removes msi from the\ndt thus with both an ath9k 802.11 device which only supports legacy\ninterrupts and a Marvell sky2 device which supports msi as well as\nlegacy interrupts and it works as expected:\n - without msi enabled in dts (default): both sky2 and ath9k work\n - with msi enabled in dt: sky2 works ath9k does not\n\nTested-by: Tim Harvey \n\nRegards,\n\nTim","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1761192,"web_url":"http://patchwork.ozlabs.org/comment/1761192/","msgid":"<20170831165817.GD18250@bhelgaas-glaptop.roam.corp.google.com>","list_archive_url":null,"date":"2017-08-31T16:58:17","subject":"Re: [PATCH 1/3] PCI: designware: only register MSI controller when\n\tMSI irq line is valid","submitter":{"id":67298,"url":"http://patchwork.ozlabs.org/api/people/67298/","name":"Bjorn Helgaas","email":"helgaas@kernel.org"},"content":"[+cc Kishon, Thomas, Niklas, Jesper, Zhou, Gabriele, Xiaowei, Binghui,\nStanimir, Pratyush, Kukjin, Krzysztof, Richard, Murali, Minghuan, Mingkai,\nRoy]\n\nSorry about the unwieldy cc list. It seems like this affects every\nDesignWare-based driver.\n\nOn Mon, Aug 28, 2017 at 04:23:05PM +0200, Lucas Stach wrote:\n> The MSI part of the controller isn't essential, so the host controller can\n> be registered without the MSI controller being present. This allows the\n> host to work in PCIe legancy interrupt only mode, if the IRQ line for the\n\ns/legancy/legacy/\n\n> MSI controller is missing.\n> \n> Signed-off-by: Lucas Stach \n> ---\n> drivers/pci/dwc/pcie-designware-host.c | 4 ++--\n> 1 file changed, 2 insertions(+), 2 deletions(-)\n> \n> diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c\n> index d29c020da082..8494089f088d 100644\n> --- a/drivers/pci/dwc/pcie-designware-host.c\n> +++ b/drivers/pci/dwc/pcie-designware-host.c\n> @@ -381,7 +381,7 @@ int dw_pcie_host_init(struct pcie_port *pp)\n> \tif (ret)\n> \t\tpci->num_viewport = 2;\n> \n> -\tif (IS_ENABLED(CONFIG_PCI_MSI)) {\n> +\tif (IS_ENABLED(CONFIG_PCI_MSI) && pp->msi_irq > 0) {\n> \t\tif (!pp->ops->msi_host_init) {\n> \t\t\tpp->irq_domain = irq_domain_add_linear(dev->of_node,\n> \t\t\t\t\t\tMAX_MSI_IRQS, &msi_domain_ops,\n> @@ -412,7 +412,7 @@ int dw_pcie_host_init(struct pcie_port *pp)\n> \tbridge->ops = &dw_pcie_ops;\n> \tbridge->map_irq = of_irq_parse_and_map_pci;\n> \tbridge->swizzle_irq = pci_common_swizzle;\n> -\tif (IS_ENABLED(CONFIG_PCI_MSI)) {\n> +\tif (IS_ENABLED(CONFIG_PCI_MSI) && pp->msi_irq > 0) {\n> \t\tbridge->msi = &dw_pcie_msi_chip;\n> \t\tdw_pcie_msi_chip.dev = dev;\n> \t}\n\nHere are the callers of dw_pcie_host_init():\n\n armada8k_add_pcie_port\n artpec6_add_pcie_port # sets pp->msi_irq\n dra7xx_add_pcie_port\n dw_plat_add_pcie_port # sets pp->msi_irq\n exynos_add_pcie_port # sets pp->msi_irq\n hisi_add_pcie_port\n imx6_add_pcie_port # sets pp->msi_irq\n kirin_add_pcie_port\n ks_dw_pcie_host_init # sets pp->ops->msi_host_init\n ls_add_pcie_port # sets pp->ops->msi_host_init\n qcom_pcie_probe # sets pp->msi_irq\n spear13xx_add_pcie_port\n\nFor the drivers that set pp->msi_irq (artpec6, dw_plat, exynos, imx6,\nqcom), it seems like you'd want a similar follow-up change for all of\nthem to make the MSI IRQ optional, but you only changed imx6. What\nabout the others?\n\nFor the drivers that don't set pp->msi_irq and don't set\npp->ops->msi_host_init (armada8k, dra7xx, hisi, kirin, spear13xx),\nthis patch means they no longer set up pp->irq_domain. Do you intend\nthat?\n\nIncidental observations not strictly related to this series:\n\n - It looks like exynos_add_pcie_port() incorrectly assumes\n platform_get_irq() returns zero on failure (twice).\n\n - It'd be nice if qcom_pcie_probe() followed the same\n add_pcie_port() structure as the other drivers.\n\nBjorn","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"tHv80KbB\"; dkim-atps=neutral","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=helgaas@kernel.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjpW41YlGz9sD5\n\tfor ;\n\tFri, 1 Sep 2017 02:59:10 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dnSo6-00057b-3m; Thu, 31 Aug 2017 16:59:06 +0000","from mail.kernel.org ([198.145.29.99])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dnSng-00054J-Gx for linux-arm-kernel@lists.infradead.org;\n\tThu, 31 Aug 2017 16:58:42 +0000","from localhost (unknown [69.55.156.165])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 87D562199E;\n\tThu, 31 Aug 2017 16:58:19 +0000 (UTC)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=zMBp+TpfArcCnEzO8T0dU77fhYz3zwBrZJFhgLSwVXU=;\n\tb=tHv80KbBoNLvPA\n\tteyDXBOKUFhjWMBfdB9OoXAUbIZ3axoMdK8Qcv5xAwHMde6jufE7norWYZPgHMmO1BAaA/DIO/P/r\n\td15fm921p2Hdf8halOHgn/9QM5pIg+yPzziJt+b7CVLdBjWpFK3UUQrk1kxQOjmQQA1GVb1qTaHVL\n\t4IQCHB4q0Vh9UAw1XR6MpwWgJ+Vhlp4F/fjg+csB++XCFfAXlWpvXjdLSDBNR4+HS6Jp2X5GcmR+W\n\t632akMAZEkTvLY6/7g8DzU+x8PNiy5hHjtCU4HfxuGNAhKgT4H1QqNya7xRb9U09D2QXb4U468/5W\n\tPZXEirZHw0QKAC4Cg+rg==;","DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org 87D562199E","Date":"Thu, 31 Aug 2017 11:58:17 -0500","From":"Bjorn Helgaas ","To":"Lucas Stach ","Subject":"Re: [PATCH 1/3] PCI: designware: only register MSI controller when\n\tMSI irq line is valid","Message-ID":"<20170831165817.GD18250@bhelgaas-glaptop.roam.corp.google.com>","References":"<20170828142307.30061-1-l.stach@pengutronix.de>\n\t<20170828142307.30061-2-l.stach@pengutronix.de>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<20170828142307.30061-2-l.stach@pengutronix.de>","User-Agent":"Mutt/1.5.21 (2010-09-15)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170831_095840_690091_8ADB3796 ","X-CRM114-Status":"GOOD ( 17.10 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [198.145.29.99 listed in list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Gabriele Paoloni , linux-pci@vger.kernel.org,\n\tBinghui Wang ,\n\tRoy Zang ,\n\tKishon Vijay Abraham I , \n\tJesper Nilsson ,\n\tJoao Pinto , \n\tPratyush Anand ,\n\tKrzysztof Kozlowski , patchwork-lst@pengutronix.de, \n\tKukjin Kim , Niklas Cassel ,\n\tRichard Zhu , Tim Harvey ,\n\tXiaowei Song ,\n\tMurali Karicheri ,\n\tBjorn Helgaas , \n\tMingkai Hu ,\n\tlinux-arm-kernel@lists.infradead.org, \n\tThomas Petazzoni ,\n\tJingoo Han ,\n\tStanimir Varbanov , \n\tMinghuan Lian ,\n\tZhou Wang , kernel@pengutronix.de,\n\tShawn Guo ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1761211,"web_url":"http://patchwork.ozlabs.org/comment/1761211/","msgid":"","list_archive_url":null,"date":"2017-08-31T17:32:55","subject":"Re: [PATCH 1/3] PCI: designware: only register MSI controller when\n\tMSI irq line is valid","submitter":{"id":6978,"url":"http://patchwork.ozlabs.org/api/people/6978/","name":"Fabio Estevam","email":"festevam@gmail.com"},"content":"Hi Bjorn,\n\nOn Thu, Aug 31, 2017 at 1:58 PM, Bjorn Helgaas wrote:\n\n> Incidental observations not strictly related to this series:\n>\n> - It looks like exynos_add_pcie_port() incorrectly assumes\n> platform_get_irq() returns zero on failure (twice).\n\nI will send a series cleaning up the error handling in\nplatform_get_irq() for the various PCI drivers.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1775054,"web_url":"http://patchwork.ozlabs.org/comment/1775054/","msgid":"<20170925235405.GJ15970@bhelgaas-glaptop.roam.corp.google.com>","list_archive_url":null,"date":"2017-09-25T23:54:05","subject":"Re: [PATCH 1/3] PCI: designware: only register MSI controller when\n\tMSI irq line is valid","submitter":{"id":67298,"url":"http://patchwork.ozlabs.org/api/people/67298/","name":"Bjorn Helgaas","email":"helgaas@kernel.org"},"content":"On Thu, Aug 31, 2017 at 11:58:17AM -0500, Bjorn Helgaas wrote:\n> [+cc Kishon, Thomas, Niklas, Jesper, Zhou, Gabriele, Xiaowei, Binghui,\n> Stanimir, Pratyush, Kukjin, Krzysztof, Richard, Murali, Minghuan, Mingkai,\n> Roy]\n> \n> Sorry about the unwieldy cc list. It seems like this affects every\n> DesignWare-based driver.\n> \n> On Mon, Aug 28, 2017 at 04:23:05PM +0200, Lucas Stach wrote:\n> > The MSI part of the controller isn't essential, so the host controller can\n> > be registered without the MSI controller being present. This allows the\n> > host to work in PCIe legancy interrupt only mode, if the IRQ line for the\n> \n> s/legancy/legacy/\n> \n> > MSI controller is missing.\n> > \n> > Signed-off-by: Lucas Stach \n> > ---\n> > drivers/pci/dwc/pcie-designware-host.c | 4 ++--\n> > 1 file changed, 2 insertions(+), 2 deletions(-)\n> > \n> > diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c\n> > index d29c020da082..8494089f088d 100644\n> > --- a/drivers/pci/dwc/pcie-designware-host.c\n> > +++ b/drivers/pci/dwc/pcie-designware-host.c\n> > @@ -381,7 +381,7 @@ int dw_pcie_host_init(struct pcie_port *pp)\n> > \tif (ret)\n> > \t\tpci->num_viewport = 2;\n> > \n> > -\tif (IS_ENABLED(CONFIG_PCI_MSI)) {\n> > +\tif (IS_ENABLED(CONFIG_PCI_MSI) && pp->msi_irq > 0) {\n> > \t\tif (!pp->ops->msi_host_init) {\n> > \t\t\tpp->irq_domain = irq_domain_add_linear(dev->of_node,\n> > \t\t\t\t\t\tMAX_MSI_IRQS, &msi_domain_ops,\n> > @@ -412,7 +412,7 @@ int dw_pcie_host_init(struct pcie_port *pp)\n> > \tbridge->ops = &dw_pcie_ops;\n> > \tbridge->map_irq = of_irq_parse_and_map_pci;\n> > \tbridge->swizzle_irq = pci_common_swizzle;\n> > -\tif (IS_ENABLED(CONFIG_PCI_MSI)) {\n> > +\tif (IS_ENABLED(CONFIG_PCI_MSI) && pp->msi_irq > 0) {\n> > \t\tbridge->msi = &dw_pcie_msi_chip;\n> > \t\tdw_pcie_msi_chip.dev = dev;\n> > \t}\n> \n> Here are the callers of dw_pcie_host_init():\n> \n> armada8k_add_pcie_port\n> artpec6_add_pcie_port # sets pp->msi_irq\n> dra7xx_add_pcie_port\n> dw_plat_add_pcie_port # sets pp->msi_irq\n> exynos_add_pcie_port # sets pp->msi_irq\n> hisi_add_pcie_port\n> imx6_add_pcie_port # sets pp->msi_irq\n> kirin_add_pcie_port\n> ks_dw_pcie_host_init # sets pp->ops->msi_host_init\n> ls_add_pcie_port # sets pp->ops->msi_host_init\n> qcom_pcie_probe # sets pp->msi_irq\n> spear13xx_add_pcie_port\n> \n> For the drivers that set pp->msi_irq (artpec6, dw_plat, exynos, imx6,\n> qcom), it seems like you'd want a similar follow-up change for all of\n> them to make the MSI IRQ optional, but you only changed imx6. What\n> about the others?\n> \n> For the drivers that don't set pp->msi_irq and don't set\n> pp->ops->msi_host_init (armada8k, dra7xx, hisi, kirin, spear13xx),\n> this patch means they no longer set up pp->irq_domain. Do you intend\n> that?\n\nPing, I'm looking for a v2 that addresses this. No hurry, just\nmaking sure you're not waiting on me.\n\nBjorn","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"fyRRlbig\"; dkim-atps=neutral","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=helgaas@kernel.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y1LXr430xz9sRV\n\tfor ;\n\tTue, 26 Sep 2017 09:54:36 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dwdCq-0006k7-Fw; Mon, 25 Sep 2017 23:54:32 +0000","from mail.kernel.org ([198.145.29.99])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dwdCm-0006VL-C2 for linux-arm-kernel@lists.infradead.org;\n\tMon, 25 Sep 2017 23:54:30 +0000","from localhost (unknown [69.71.4.159])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 04E74214E2;\n\tMon, 25 Sep 2017 23:54:07 +0000 (UTC)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=mHM/ptSbXYq0dMVnPBtmOkYGL4KbE2Eb7Mza2NUCSIk=;\n\tb=fyRRlbigSURHD9\n\tHCAttNjWqvDREfifIEiTZTxuu9FRCyQlZCFGjXD4xyBvVbWitRCCkHEjlkbFh9+WW4RpjgOWpdjEp\n\tWQ9BiMqtrA9/nsDpwKR+prOqa0HpGbBC20N+r++H5xVRGCzisQhqPbk97kPgCrVlafn7Bt6Mpo0Az\n\tsNSU1+2FeUgDq/XPlZMq4w5MROfJdpS/ndQ6Z3xmCbnQqCcvlG8wQx+T9KQ9UAzMGUQukmwU7hZea\n\tfneKLSbqMgM6k9HXBdpb+GfyEtWFWL+jjWddBB1wX6aAAK5mY6i8M7qq0UsiClXQAINYw2//j8nm4\n\tuisK244pcN4Z242slsKA==;","DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org 04E74214E2","Date":"Mon, 25 Sep 2017 18:54:05 -0500","From":"Bjorn Helgaas ","To":"Lucas Stach ","Subject":"Re: [PATCH 1/3] PCI: designware: only register MSI controller when\n\tMSI irq line is valid","Message-ID":"<20170925235405.GJ15970@bhelgaas-glaptop.roam.corp.google.com>","References":"<20170828142307.30061-1-l.stach@pengutronix.de>\n\t<20170828142307.30061-2-l.stach@pengutronix.de>\n\t<20170831165817.GD18250@bhelgaas-glaptop.roam.corp.google.com>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<20170831165817.GD18250@bhelgaas-glaptop.roam.corp.google.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170925_165428_605106_6B000A99 ","X-CRM114-Status":"GOOD ( 19.84 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [198.145.29.99 listed in list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Gabriele Paoloni , linux-pci@vger.kernel.org,\n\tBinghui Wang ,\n\tShawn Guo , \n\tpatchwork-lst@pengutronix.de, Jesper Nilsson ,\n\tJoao Pinto ,\n\tPratyush Anand ,\n\tKrzysztof Kozlowski ,\n\tKishon Vijay Abraham I , \n\tKukjin Kim , Niklas Cassel ,\n\tRichard Zhu , Tim Harvey ,\n\tXiaowei Song ,\n\tMurali Karicheri ,\n\tBjorn Helgaas , \n\tMingkai Hu ,\n\tlinux-arm-kernel@lists.infradead.org, \n\tThomas Petazzoni ,\n\tJingoo Han ,\n\tStanimir Varbanov , \n\tMinghuan Lian ,\n\tZhou Wang , kernel@pengutronix.de,\n\tRoy Zang ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1782763,"web_url":"http://patchwork.ozlabs.org/comment/1782763/","msgid":"","list_archive_url":null,"date":"2017-10-09T12:14:19","subject":"Re: [PATCH 0/3] DWC host without MSI controller","submitter":{"id":6978,"url":"http://patchwork.ozlabs.org/api/people/6978/","name":"Fabio Estevam","email":"festevam@gmail.com"},"content":"Hi Bjorn,\n\nOn Mon, Aug 28, 2017 at 1:59 PM, Tim Harvey wrote:\n> On Mon, Aug 28, 2017 at 7:23 AM, Lucas Stach wrote:\n>> Hi all,\n>>\n>> this small series tries to fix/workaround a serious design flaw of the DWC PCIe\n>> host controller: it is unable to work with both legacy and MSI IRQs enabled at\n>> the same time. As soon as the first MSI is enabled in the DWC MSI controller,\n>> the host stops forwarding legacy IRQs.\n>>\n>> If the MSI controller is present, MSIs will be used for the PCIe port services\n>> IRQs, leaving endpoint devices which don't support MSIs unable to raise IRQs.\n>> It is only safe to enable the MSI controller if it is validated that all PCIe\n>> devices and drivers in the system support working MSIs. As most devices\n>> support falling back to using legacy PCIe IRQs if MSI support is missing it is\n>> much safer to disable the MSI by default and only enable it on validated\n>> systems.\n>>\n>> Feedback welcome.\n>>\n>> Regards,\n>> Lucas\n>>\n>> Lucas Stach (3):\n>> PCI: designware: only register MSI controller when MSI irq line is\n>> valid\n>> PCI: imx6: allow MSI irq to be absent\n>> ARM: dts: imx6qdl: remove MSI irq line\n>>\n>> .../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 8 ++++----\n>> arch/arm/boot/dts/imx6qdl.dtsi | 2 --\n>> drivers/pci/dwc/pci-imx6.c | 23 +++++++++++-----------\n>> drivers/pci/dwc/pcie-designware-host.c | 4 ++--\n>> 4 files changed, 17 insertions(+), 20 deletions(-)\n>>\n>\n> Lucas,\n>\n> Thank you for following up on this!\n>\n> I tested it with and without the third patch that removes msi from the\n> dt thus with both an ath9k 802.11 device which only supports legacy\n> interrupts and a Marvell sky2 device which supports msi as well as\n> legacy interrupts and it works as expected:\n> - without msi enabled in dts (default): both sky2 and ath9k work\n> - with msi enabled in dt: sky2 works ath9k does not\n>\n> Tested-by: Tim Harvey \n\nAny comments about this series?","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1782766,"web_url":"http://patchwork.ozlabs.org/comment/1782766/","msgid":"<1507551771.2745.2.camel@pengutronix.de>","list_archive_url":null,"date":"2017-10-09T12:22:51","subject":"Re: [PATCH 0/3] DWC host without MSI controller","submitter":{"id":23583,"url":"http://patchwork.ozlabs.org/api/people/23583/","name":"Lucas Stach","email":"l.stach@pengutronix.de"},"content":"Hi Fabio,\n\nAm Montag, den 09.10.2017, 09:14 -0300 schrieb Fabio Estevam:\n> Hi Bjorn,\n> \n> On Mon, Aug 28, 2017 at 1:59 PM, Tim Harvey \n> wrote:\n> > On Mon, Aug 28, 2017 at 7:23 AM, Lucas Stach > e> wrote:\n> > > Hi all,\n> > > \n> > > this small series tries to fix/workaround a serious design flaw\n> > > of the DWC PCIe\n> > > host controller: it is unable to work with both legacy and MSI\n> > > IRQs enabled at\n> > > the same time. As soon as the first MSI is enabled in the DWC MSI\n> > > controller,\n> > > the host stops forwarding legacy IRQs.\n> > > \n> > > If the MSI controller is present, MSIs will be used for the PCIe\n> > > port services\n> > > IRQs, leaving endpoint devices which don't support MSIs unable to\n> > > raise IRQs.\n> > > It is only safe to enable the MSI controller if it is validated\n> > > that all PCIe\n> > > devices and drivers in the system support working MSIs. As most\n> > > devices\n> > > support falling back to using legacy PCIe IRQs if MSI support is\n> > > missing it is\n> > > much safer to disable the MSI by default and only enable it on\n> > > validated\n> > > systems.\n> > > \n> > > Feedback welcome.\n> > > \n> > > Regards,\n> > > Lucas\n> > > \n> > > Lucas Stach (3):\n> > >   PCI: designware: only register MSI controller when MSI irq line\n> > > is\n> > >     valid\n> > >   PCI: imx6: allow MSI irq to be absent\n> > >   ARM: dts: imx6qdl: remove MSI irq line\n> > > \n> > >  .../devicetree/bindings/pci/fsl,imx6q-pcie.txt     |  8 ++++----\n> > >  arch/arm/boot/dts/imx6qdl.dtsi                     |  2 --\n> > >  drivers/pci/dwc/pci-imx6.c                         | 23\n> > > +++++++++++-----------\n> > >  drivers/pci/dwc/pcie-designware-host.c             |  4 ++--\n> > >  4 files changed, 17 insertions(+), 20 deletions(-)\n> > > \n> > \n> > Lucas,\n> > \n> > Thank you for following up on this!\n> > \n> > I tested it with and without the third patch that removes msi from\n> > the\n> > dt thus with both an ath9k 802.11 device which only supports legacy\n> > interrupts and a Marvell sky2 device which supports msi as well as\n> > legacy interrupts and it works as expected:\n> >  - without msi enabled in dts (default): both sky2 and ath9k work\n> >  - with msi enabled in dt: sky2 works ath9k does not\n> > \n> > Tested-by: Tim Harvey \n> \n> Any comments about this series?\n\nBjorn already commented on the series and I'm trying free up a slot to\naddress the feedback.\n\nRegards,\nLucas","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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