[{"id":3682676,"web_url":"http://patchwork.ozlabs.org/comment/3682676/","msgid":"","list_archive_url":null,"date":"2026-04-27T12:20:09","subject":"Re: [PATCH 0/5] Improvements to PCI hibernate path","submitter":{"id":64267,"url":"http://patchwork.ozlabs.org/api/people/64267/","name":"Rafael J. Wysocki","email":"rafael@kernel.org"},"content":"On Mon, Apr 27, 2026 at 5:53 AM Mario Limonciello (AMD)\n wrote:\n>\n> A few cycles ago I sent out a kernel series for using the S4 paths when\n> the system goes to S5. Some parts of it got merged, and Rafael suggested\n> to split the other parts into smaller pieces across multiple kernel cycles\n> to make bisecting easier.\n>\n> This fell into my backlog behind other things, so I wanted to try again\n> this cycle for the PCI pieces. I have been carrying it, rebasing it and\n> personally using it for a while now though.\n>\n> This series attempts to unify the PCI suspend and hibernate paths and to\n> fix some things that I observed to be wrong with how I expect hibernate\n> to work.\n>\n> It is based off 7.1-rc1 + Lukas' patch:\n> \"PCI: Stop setting cached power state to \"unknown\" on unbind\"\n>\n> Mario Limonciello (AMD) (5):\n> PCI/PM: Disable device wakeups when halting or powering off system\n> PCI/PM: Split out code from pci_pm_suspend_noirq() into helper\n> PCI/PM: Run bridge power up actions as part of restore phase\n> PCI/PM: Use pci_power_manageable() in pci_pm_poweroff_noirq()\n> PCI: Put PCIe bridges with downstream devices into D3 at hibernate\n>\n> drivers/pci/pci-driver.c | 103 ++++++++++++++++++++++++++-------------\n> 1 file changed, 69 insertions(+), 34 deletions(-)\n>\n> --\n\nIt would be good to CC this to linux-pm.","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=ex4jWHGg;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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Mon, 27 Apr 2026\n 05:20:23 -0700 (PDT)","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","References":"<20260427035341.1425576-1-superm1@kernel.org>","In-Reply-To":"<20260427035341.1425576-1-superm1@kernel.org>","From":"\"Rafael J. Wysocki\" ","Date":"Mon, 27 Apr 2026 14:20:09 +0200","X-Gmail-Original-Message-ID":"\n ","X-Gm-Features":"AVHnY4IKYHDd9ijs1yd9zSMdTYJ07ye1RpvHHgMd-tlxpDW3LjKGPKTN06B0nEo","Message-ID":"\n ","Subject":"Re: [PATCH 0/5] Improvements to PCI hibernate path","To":"\"Mario Limonciello (AMD)\" ","Cc":"Bjorn Helgaas ,\n\t\"open list:PCI SUBSYSTEM\" ,\n open list ,\n\t\"Rafael J . Wysocki\" , Lukas Wunner ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable"}},{"id":3682735,"web_url":"http://patchwork.ozlabs.org/comment/3682735/","msgid":"","list_archive_url":null,"date":"2026-04-27T14:14:29","subject":"Re: [PATCH 0/5] Improvements to PCI hibernate path","submitter":{"id":88834,"url":"http://patchwork.ozlabs.org/api/people/88834/","name":"Mario Limonciello","email":"superm1@kernel.org"},"content":"On 4/27/26 07:20, Rafael J. Wysocki wrote:\n> On Mon, Apr 27, 2026 at 5:53 AM Mario Limonciello (AMD)\n> wrote:\n>>\n>> A few cycles ago I sent out a kernel series for using the S4 paths when\n>> the system goes to S5. Some parts of it got merged, and Rafael suggested\n>> to split the other parts into smaller pieces across multiple kernel cycles\n>> to make bisecting easier.\n>>\n>> This fell into my backlog behind other things, so I wanted to try again\n>> this cycle for the PCI pieces. I have been carrying it, rebasing it and\n>> personally using it for a while now though.\n>>\n>> This series attempts to unify the PCI suspend and hibernate paths and to\n>> fix some things that I observed to be wrong with how I expect hibernate\n>> to work.\n>>\n>> It is based off 7.1-rc1 + Lukas' patch:\n>> \"PCI: Stop setting cached power state to \"unknown\" on unbind\"\n>>\n>> Mario Limonciello (AMD) (5):\n>> PCI/PM: Disable device wakeups when halting or powering off system\n>> PCI/PM: Split out code from pci_pm_suspend_noirq() into helper\n>> PCI/PM: Run bridge power up actions as part of restore phase\n>> PCI/PM: Use pci_power_manageable() in pci_pm_poweroff_noirq()\n>> PCI: Put PCIe bridges with downstream devices into D3 at hibernate\n>>\n>> drivers/pci/pci-driver.c | 103 ++++++++++++++++++++++++++-------------\n>> 1 file changed, 69 insertions(+), 34 deletions(-)\n>>\n>> --\n> \n> It would be good to CC this to linux-pm.\n\nSure thing - if there is a need for a v2, I will include linux-pm in CC.","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=eW117Hex;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-53219-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"eW117Hex\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g45Fc1cjkz1yHX\n\tfor ; Tue, 28 Apr 2026 00:15:48 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id EBDDD3011124\n\tfor ; Mon, 27 Apr 2026 14:14:31 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 2B51B3D1711;\n\tMon, 27 Apr 2026 14:14:31 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 0846E3B388F;\n\tMon, 27 Apr 2026 14:14:31 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id 8F3FDC19425;\n\tMon, 27 Apr 2026 14:14:30 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777299271; cv=none;\n b=r0RGFXlHXtLblkNG8kBdJ35g5WWOOnNs5C+ha7IABHhD70y3o2RY0huDL9CGxdcPN1/XLolMMscyViR2bGS/GlbA8zJp0+Jo8b7PEmd/Ar2JWiJYH9ZbvATNHJkhiwgzNQ6ocYd/QC37jLxJ9rU57n+WILjL0ZSEujKzP0Zla8g=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777299271; c=relaxed/simple;\n\tbh=On7qwBANiqEaPQGbTVETe24hmuBF1r9IigiTMeiamL4=;\n\th=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From:\n\t In-Reply-To:Content-Type;\n b=Q0aRtDsNwk1jEo+qRjyhHg2PDImNmqVgc1nb0U8HbXjkicvQzY1P0hCstZJ14nQmLvuCYUk+j3B01RCPgsP7hAV4McgaDqPbSwQ/6MkmLozFL5cas4AG5Fbg3v/WEHuqXlpApLu2j56AcK9Vez/91Og1VOdrdIrLUq9NwlB/PlQ=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=eW117Hex; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1777299270;\n\tbh=On7qwBANiqEaPQGbTVETe24hmuBF1r9IigiTMeiamL4=;\n\th=Date:Subject:To:Cc:References:From:In-Reply-To:From;\n\tb=eW117Hexek8S0yFBftTL9eFMoR4R7yUw52gw0nvs3tz3R0OPyMKRkpt30Q7YFenWD\n\t gfzaJaEIT8RDuM1mCCQN5Oe8vhf+xcEcHZiJGf5PxzfZIB5FR/LsbOrGLmOzldvuDe\n\t O0jCUT/WnRqVVDvMnm9QgEhNYhOFqAvhx9ZTc/hIMIAZhjD2EYxMLDUJLXSxtZSwXp\n\t Y8dFcXw3zkqzisjgo/Qig1PgUA9MIaQ1JtIa1wcuCOs4wHu5qz43XaaX73HeQwHxo/\n\t 9NYBLx6lIzEgzg/2EDDnFJIF52VC+qxp0yRrGpG5cwiVE7i+upBzvW5A2/EyhiDjQ1\n\t Wy78HIgjCcARQ==","Message-ID":"","Date":"Mon, 27 Apr 2026 09:14:29 -0500","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","Subject":"Re: [PATCH 0/5] Improvements to PCI hibernate path","Content-Language":"en-US","To":"\"Rafael J. Wysocki\" ","Cc":"Bjorn Helgaas ,\n \"open list:PCI SUBSYSTEM\" ,\n open list , Lukas Wunner ","References":"<20260427035341.1425576-1-superm1@kernel.org>\n ","From":"Mario Limonciello ","In-Reply-To":"\n ","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit"}},{"id":3682770,"web_url":"http://patchwork.ozlabs.org/comment/3682770/","msgid":"","list_archive_url":null,"date":"2026-04-27T15:09:36","subject":"Re: [PATCH 0/5] Improvements to PCI hibernate path","submitter":{"id":64267,"url":"http://patchwork.ozlabs.org/api/people/64267/","name":"Rafael J. Wysocki","email":"rafael@kernel.org"},"content":"On Mon, Apr 27, 2026 at 4:14 PM Mario Limonciello wrote:\n>\n> On 4/27/26 07:20, Rafael J. Wysocki wrote:\n> > On Mon, Apr 27, 2026 at 5:53 AM Mario Limonciello (AMD)\n> > wrote:\n> >>\n> >> A few cycles ago I sent out a kernel series for using the S4 paths when\n> >> the system goes to S5. Some parts of it got merged, and Rafael suggested\n> >> to split the other parts into smaller pieces across multiple kernel cycles\n> >> to make bisecting easier.\n> >>\n> >> This fell into my backlog behind other things, so I wanted to try again\n> >> this cycle for the PCI pieces. I have been carrying it, rebasing it and\n> >> personally using it for a while now though.\n> >>\n> >> This series attempts to unify the PCI suspend and hibernate paths and to\n> >> fix some things that I observed to be wrong with how I expect hibernate\n> >> to work.\n> >>\n> >> It is based off 7.1-rc1 + Lukas' patch:\n> >> \"PCI: Stop setting cached power state to \"unknown\" on unbind\"\n> >>\n> >> Mario Limonciello (AMD) (5):\n> >> PCI/PM: Disable device wakeups when halting or powering off system\n> >> PCI/PM: Split out code from pci_pm_suspend_noirq() into helper\n> >> PCI/PM: Run bridge power up actions as part of restore phase\n> >> PCI/PM: Use pci_power_manageable() in pci_pm_poweroff_noirq()\n> >> PCI: Put PCIe bridges with downstream devices into D3 at hibernate\n> >>\n> >> drivers/pci/pci-driver.c | 103 ++++++++++++++++++++++++++-------------\n> >> 1 file changed, 69 insertions(+), 34 deletions(-)\n> >>\n> >> --\n> >\n> > It would be good to CC this to linux-pm.\n>\n> Sure thing - if there is a need for a v2, I will include linux-pm in CC.\n\nThe thing is, you may not know if there's a need for a v2 without resending.","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=lAgf3vyH;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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Wysocki\" ","Date":"Mon, 27 Apr 2026 17:09:36 +0200","X-Gmail-Original-Message-ID":"\n ","X-Gm-Features":"AVHnY4JhRW-xCPF9OWt7F-_Fif0sxFvV8_89EcXgbTHIG6hBGampOS3GCVCQfD0","Message-ID":"\n ","Subject":"Re: [PATCH 0/5] Improvements to PCI hibernate path","To":"Mario Limonciello ","Cc":"\"Rafael J. Wysocki\" ,\n Bjorn Helgaas ,\n\t\"open list:PCI SUBSYSTEM\" ,\n open list ,\n\tLukas Wunner ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable"}},{"id":3682778,"web_url":"http://patchwork.ozlabs.org/comment/3682778/","msgid":"<286b39c3-f368-4477-bb67-2ce53f62d6a3@kernel.org>","list_archive_url":null,"date":"2026-04-27T15:19:47","subject":"Re: [PATCH 0/5] Improvements to PCI hibernate path","submitter":{"id":88834,"url":"http://patchwork.ozlabs.org/api/people/88834/","name":"Mario Limonciello","email":"superm1@kernel.org"},"content":"On 4/27/26 10:09, Rafael J. Wysocki wrote:\n> On Mon, Apr 27, 2026 at 4:14 PM Mario Limonciello wrote:\n>>\n>> On 4/27/26 07:20, Rafael J. Wysocki wrote:\n>>> On Mon, Apr 27, 2026 at 5:53 AM Mario Limonciello (AMD)\n>>> wrote:\n>>>>\n>>>> A few cycles ago I sent out a kernel series for using the S4 paths when\n>>>> the system goes to S5. Some parts of it got merged, and Rafael suggested\n>>>> to split the other parts into smaller pieces across multiple kernel cycles\n>>>> to make bisecting easier.\n>>>>\n>>>> This fell into my backlog behind other things, so I wanted to try again\n>>>> this cycle for the PCI pieces. I have been carrying it, rebasing it and\n>>>> personally using it for a while now though.\n>>>>\n>>>> This series attempts to unify the PCI suspend and hibernate paths and to\n>>>> fix some things that I observed to be wrong with how I expect hibernate\n>>>> to work.\n>>>>\n>>>> It is based off 7.1-rc1 + Lukas' patch:\n>>>> \"PCI: Stop setting cached power state to \"unknown\" on unbind\"\n>>>>\n>>>> Mario Limonciello (AMD) (5):\n>>>> PCI/PM: Disable device wakeups when halting or powering off system\n>>>> PCI/PM: Split out code from pci_pm_suspend_noirq() into helper\n>>>> PCI/PM: Run bridge power up actions as part of restore phase\n>>>> PCI/PM: Use pci_power_manageable() in pci_pm_poweroff_noirq()\n>>>> PCI: Put PCIe bridges with downstream devices into D3 at hibernate\n>>>>\n>>>> drivers/pci/pci-driver.c | 103 ++++++++++++++++++++++++++-------------\n>>>> 1 file changed, 69 insertions(+), 34 deletions(-)\n>>>>\n>>>> --\n>>>\n>>> It would be good to CC this to linux-pm.\n>>\n>> Sure thing - if there is a need for a v2, I will include linux-pm in CC.\n> \n> The thing is, you may not know if there's a need for a v2 without resending.\n\nI would think Lukas and Bjorn will at least have some comments and I \nwant to give them some time before cluttering inboxes with a second copy \nof the series at the start of the dev cycle.\n\nHow about if it looks good to them as is I'll send a v2 with their tags \nadded for linux-pm to get a chance to see and review as well.\n\nAnd if they have feedback I'll incorporate and v2 will also go to linux-pm.","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=PhMND0/p;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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Wysocki\" ","Cc":"Bjorn Helgaas ,\n \"open list:PCI SUBSYSTEM\" ,\n open list , Lukas Wunner ","References":"<20260427035341.1425576-1-superm1@kernel.org>\n \n \n ","From":"Mario Limonciello ","In-Reply-To":"\n ","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit"}},{"id":3682811,"web_url":"http://patchwork.ozlabs.org/comment/3682811/","msgid":"","list_archive_url":null,"date":"2026-04-27T16:06:12","subject":"Re: [PATCH 0/5] Improvements to PCI hibernate path","submitter":{"id":64267,"url":"http://patchwork.ozlabs.org/api/people/64267/","name":"Rafael J. Wysocki","email":"rafael@kernel.org"},"content":"On Mon, Apr 27, 2026 at 5:19 PM Mario Limonciello wrote:\n>\n> On 4/27/26 10:09, Rafael J. Wysocki wrote:\n> > On Mon, Apr 27, 2026 at 4:14 PM Mario Limonciello wrote:\n> >>\n> >> On 4/27/26 07:20, Rafael J. Wysocki wrote:\n> >>> On Mon, Apr 27, 2026 at 5:53 AM Mario Limonciello (AMD)\n> >>> wrote:\n> >>>>\n> >>>> A few cycles ago I sent out a kernel series for using the S4 paths when\n> >>>> the system goes to S5. Some parts of it got merged, and Rafael suggested\n> >>>> to split the other parts into smaller pieces across multiple kernel cycles\n> >>>> to make bisecting easier.\n> >>>>\n> >>>> This fell into my backlog behind other things, so I wanted to try again\n> >>>> this cycle for the PCI pieces. I have been carrying it, rebasing it and\n> >>>> personally using it for a while now though.\n> >>>>\n> >>>> This series attempts to unify the PCI suspend and hibernate paths and to\n> >>>> fix some things that I observed to be wrong with how I expect hibernate\n> >>>> to work.\n> >>>>\n> >>>> It is based off 7.1-rc1 + Lukas' patch:\n> >>>> \"PCI: Stop setting cached power state to \"unknown\" on unbind\"\n> >>>>\n> >>>> Mario Limonciello (AMD) (5):\n> >>>> PCI/PM: Disable device wakeups when halting or powering off system\n> >>>> PCI/PM: Split out code from pci_pm_suspend_noirq() into helper\n> >>>> PCI/PM: Run bridge power up actions as part of restore phase\n> >>>> PCI/PM: Use pci_power_manageable() in pci_pm_poweroff_noirq()\n> >>>> PCI: Put PCIe bridges with downstream devices into D3 at hibernate\n> >>>>\n> >>>> drivers/pci/pci-driver.c | 103 ++++++++++++++++++++++++++-------------\n> >>>> 1 file changed, 69 insertions(+), 34 deletions(-)\n> >>>>\n> >>>> --\n> >>>\n> >>> It would be good to CC this to linux-pm.\n> >>\n> >> Sure thing - if there is a need for a v2, I will include linux-pm in CC.\n> >\n> > The thing is, you may not know if there's a need for a v2 without resending.\n>\n> I would think Lukas and Bjorn will at least have some comments and I\n> want to give them some time before cluttering inboxes with a second copy\n> of the series at the start of the dev cycle.\n\nFair enough.\n\n> How about if it looks good to them as is I'll send a v2 with their tags\n> added for linux-pm to get a chance to see and review as well.\n>\n> And if they have feedback I'll incorporate and v2 will also go to linux-pm.\n\nThat should work, thanks!","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=jIJI6Xjv;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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Mon, 27 Apr 2026\n 09:06:25 -0700 (PDT)","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","References":"<20260427035341.1425576-1-superm1@kernel.org>\n \n \n \n <286b39c3-f368-4477-bb67-2ce53f62d6a3@kernel.org>","In-Reply-To":"<286b39c3-f368-4477-bb67-2ce53f62d6a3@kernel.org>","From":"\"Rafael J. Wysocki\" ","Date":"Mon, 27 Apr 2026 18:06:12 +0200","X-Gmail-Original-Message-ID":"\n ","X-Gm-Features":"AVHnY4KL77CBX2eOvzOja-rUlowIlR2w4LDNvaWH1P3TwbK7iTivGwG87TWNUeg","Message-ID":"\n ","Subject":"Re: [PATCH 0/5] Improvements to PCI hibernate path","To":"Mario Limonciello ","Cc":"\"Rafael J. Wysocki\" ,\n Bjorn Helgaas ,\n\t\"open list:PCI SUBSYSTEM\" ,\n open list ,\n\tLukas Wunner ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable"}},{"id":3682971,"web_url":"http://patchwork.ozlabs.org/comment/3682971/","msgid":"<20260427203404.GA182096@bhelgaas>","list_archive_url":null,"date":"2026-04-27T20:34:04","subject":"Re: [PATCH 0/5] Improvements to PCI hibernate path","submitter":{"id":67298,"url":"http://patchwork.ozlabs.org/api/people/67298/","name":"Bjorn Helgaas","email":"helgaas@kernel.org"},"content":"On Sun, Apr 26, 2026 at 10:53:36PM -0500, Mario Limonciello (AMD) wrote:\n> A few cycles ago I sent out a kernel series for using the S4 paths when\n> the system goes to S5. Some parts of it got merged, and Rafael suggested\n> to split the other parts into smaller pieces across multiple kernel cycles\n> to make bisecting easier.\n> \n> This fell into my backlog behind other things, so I wanted to try again\n> this cycle for the PCI pieces. I have been carrying it, rebasing it and\n> personally using it for a while now though.\n> \n> This series attempts to unify the PCI suspend and hibernate paths and to\n> fix some things that I observed to be wrong with how I expect hibernate\n> to work.\n> \n> It is based off 7.1-rc1 + Lukas' patch:\n> \"PCI: Stop setting cached power state to \"unknown\" on unbind\"\n\nHi Mario, would you mind posting a v2 that includes Lukas' patch, so\nthe whole series applies cleanly so Sashiko can go through it?\n\nI already applied Lukas' patch on pci/pm, but I guess Sashiko can't\nparse that dependency.\n\n> Mario Limonciello (AMD) (5):\n> PCI/PM: Disable device wakeups when halting or powering off system\n> PCI/PM: Split out code from pci_pm_suspend_noirq() into helper\n> PCI/PM: Run bridge power up actions as part of restore phase\n> PCI/PM: Use pci_power_manageable() in pci_pm_poweroff_noirq()\n> PCI: Put PCIe bridges with downstream devices into D3 at hibernate\n> \n> drivers/pci/pci-driver.c | 103 ++++++++++++++++++++++++++-------------\n> 1 file changed, 69 insertions(+), 34 deletions(-)\n> \n> -- \n> 2.43.0\n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=o7cOhVp1;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-53248-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"o7cOhVp1\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g4FnB1n2Kz1yHv\n\tfor ; Tue, 28 Apr 2026 06:40:14 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 18A9330D8F1C\n\tfor ; Mon, 27 Apr 2026 20:34:07 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id E0935371D04;\n\tMon, 27 Apr 2026 20:34:05 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id BC946371CFF;\n\tMon, 27 Apr 2026 20:34:05 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id 57A58C2BCB9;\n\tMon, 27 Apr 2026 20:34:05 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777322045; cv=none;\n b=njvlg8kYuEUUd3JqtOw+b+x9yGVmQJDv3bP51FLzhBug8/FAi6meg+/smqslokZXBLd2DGOJuK6/GwSbaRw0BABabrN4CvVGwU+t1kqEOnGaeebzUzfeCPtKXdlsNxyaN/TGOzGbTi6n8dqgx9XYBO6GJcRm/Wm8CSghFDuJjNE=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777322045; c=relaxed/simple;\n\tbh=SdulBXz7GBAyzVrKSc8VCh1nbo1vRKI12nbpooE3Mig=;\n\th=Date:From:To:Cc:Subject:Message-ID:MIME-Version:Content-Type:\n\t Content-Disposition:In-Reply-To;\n b=bOX+pNnlXjSUx8Oz/jUDueEmdNgF9ZyTfA4cU6d2zeQvCxBgOiKzIi60Ely9p1OEPBaPnEkwsvnHMvM1AedDXYBFrgk57hP18HwV6XAtBP+Y/ei4RLAk8HGAK9o/EZAd0tIkHsQ+PdLvp8+jMyo9/kg3xSMsNxyyWlmAhG6Ksqk=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=o7cOhVp1; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1777322045;\n\tbh=SdulBXz7GBAyzVrKSc8VCh1nbo1vRKI12nbpooE3Mig=;\n\th=Date:From:To:Cc:Subject:In-Reply-To:From;\n\tb=o7cOhVp1EeRXf1GFuHHh9wfMDS8SdTX3DP1bOXNCPBFQ8Z/VJk0aPsTo9furWDtWz\n\t YvbPUw0TgRukwBu2O1I9WMkvUstyxYw3JO4Oa0hsP/oXqRXc/FRovLCr1SbbOdJZHy\n\t /Q7a90UCFKxYcK1xh8P8yfWjtoQNf+FfiY3AlUOv8rK4+VL4DO0RYbo6xRupY2P+E6\n\t HDlRIKnhgKTY5aaQ9VecpKgd5pXqbbU92GzRJPIVVMQJ62OIu8ZkYNOdbwBU2yt/va\n\t 7qo0BGUxni2bEAZJOYScUAyxBF1u7CPQfbfpwk4YjHcBg2tRwsNtdiFgzRfK62qTbC\n\t PIIoPXgEvkcgw==","Date":"Mon, 27 Apr 2026 15:34:04 -0500","From":"Bjorn Helgaas ","To":"\"Mario Limonciello (AMD)\" ","Cc":"Bjorn Helgaas ,\n\t\"open list:PCI SUBSYSTEM\" ,\n\topen list ,\n\t\"Rafael J . Wysocki\" ,\n\tLukas Wunner ","Subject":"Re: [PATCH 0/5] Improvements to PCI hibernate path","Message-ID":"<20260427203404.GA182096@bhelgaas>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20260427035341.1425576-1-superm1@kernel.org>"}},{"id":3682975,"web_url":"http://patchwork.ozlabs.org/comment/3682975/","msgid":"<548b719f-a98f-452f-98d7-1f2b184e0eb3@kernel.org>","list_archive_url":null,"date":"2026-04-27T20:36:21","subject":"Re: [PATCH 0/5] Improvements to PCI hibernate path","submitter":{"id":88834,"url":"http://patchwork.ozlabs.org/api/people/88834/","name":"Mario Limonciello","email":"superm1@kernel.org"},"content":"On 4/27/26 15:34, Bjorn Helgaas wrote:\n> On Sun, Apr 26, 2026 at 10:53:36PM -0500, Mario Limonciello (AMD) wrote:\n>> A few cycles ago I sent out a kernel series for using the S4 paths when\n>> the system goes to S5. Some parts of it got merged, and Rafael suggested\n>> to split the other parts into smaller pieces across multiple kernel cycles\n>> to make bisecting easier.\n>>\n>> This fell into my backlog behind other things, so I wanted to try again\n>> this cycle for the PCI pieces. I have been carrying it, rebasing it and\n>> personally using it for a while now though.\n>>\n>> This series attempts to unify the PCI suspend and hibernate paths and to\n>> fix some things that I observed to be wrong with how I expect hibernate\n>> to work.\n>>\n>> It is based off 7.1-rc1 + Lukas' patch:\n>> \"PCI: Stop setting cached power state to \"unknown\" on unbind\"\n> \n> Hi Mario, would you mind posting a v2 that includes Lukas' patch, so\n> the whole series applies cleanly so Sashiko can go through it?\n> \n> I already applied Lukas' patch on pci/pm, but I guess Sashiko can't\n> parse that dependency.\n\nBjorn,\n\nSure. I'll repost with his patch front-loaded. I assume you'll just \ndrop that when applying if/when everything else looks good right?\n\nFWIW, I did run review-prompts offline on the series already with Claude \nmodels so hopefully no new surprises when it runs with Google's models :P\n\nThanks,\n\n> \n>> Mario Limonciello (AMD) (5):\n>> PCI/PM: Disable device wakeups when halting or powering off system\n>> PCI/PM: Split out code from pci_pm_suspend_noirq() into helper\n>> PCI/PM: Run bridge power up actions as part of restore phase\n>> PCI/PM: Use pci_power_manageable() in pci_pm_poweroff_noirq()\n>> PCI: Put PCIe bridges with downstream devices into D3 at hibernate\n>>\n>> drivers/pci/pci-driver.c | 103 ++++++++++++++++++++++++++-------------\n>> 1 file changed, 69 insertions(+), 34 deletions(-)\n>>\n>> -- \n>> 2.43.0\n>>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=n/zpUJn3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-53250-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"n/zpUJn3\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g4Fq61ZFBz1yHv\n\tfor ; Tue, 28 Apr 2026 06:41:54 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id C581230A544F\n\tfor ; Mon, 27 Apr 2026 20:36:23 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 391DB370D5C;\n\tMon, 27 Apr 2026 20:36:23 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 15AC536D500;\n\tMon, 27 Apr 2026 20:36:22 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id 5C968C19425;\n\tMon, 27 Apr 2026 20:36:22 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777322183; cv=none;\n b=s9IzgfIL98fz0BM4nQxTeP596Ekf6+kBPMAqfMHN9MGfYaZMfNUOGaYG7WSr38y8UxYnzjE7xkzL3Z1q/fwkuDj1iQu/FI1knw9I9AK1DSKRTHrYCktVY9L5nd+HuMG0Qng2reoXher6tgTXeZIoMqsZ3J3XQsSyfBA2TKF5xmw=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777322183; c=relaxed/simple;\n\tbh=gXVCxCp29EvKmAmHIXJVi8WyJGgDq+yAJEyEZZQ7G0A=;\n\th=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From:\n\t In-Reply-To:Content-Type;\n b=SU2ryujlRwdO+OsJwGvpGgzAaZiCPwn0BWsT8YW8tAombjQncxVwh71wjJq3SSMsXHS1idL3SAhjkMD4ixKiT10hRsSOwo9ZnlDHPFpQShfBf0lZN+b0Agm3XQy4kkjopRZwUw/TuCjM0WH7UovN/9bszn7ljbvdZ9ZvuLCSth8=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=n/zpUJn3; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1777322182;\n\tbh=gXVCxCp29EvKmAmHIXJVi8WyJGgDq+yAJEyEZZQ7G0A=;\n\th=Date:Subject:To:Cc:References:From:In-Reply-To:From;\n\tb=n/zpUJn3nhwyt5IZIgsSStvJ8vjQGK3BKpiQL/Oyt1CnoFmGsLKAH03FAAWOw0rXB\n\t B9HJpDuuSwBckIaxNfHJFaNdrdvcOe+/se+6w0GIME4a35g5hEqX9zJoHxVkHPeINp\n\t wO3rpcubuTX5zBkpNA8USjwa+yij3u+wW7jd+q2PQo8LSTjh7arp+GulqK094eVJRM\n\t dW2wQ+zqXWLRUdxJwmAcO3ccmVVV6whMGfYt4vbvRPRkRryzpP1sSBDDr37AFXBz9k\n\t 3DltREpj04ysCogrG2Ow1JgQRb/YJYLpZ1IH/qO9JEbE6BBp4PYyDxiko+Bsq4z1Fn\n\t p3AZMN6KkveWQ==","Message-ID":"<548b719f-a98f-452f-98d7-1f2b184e0eb3@kernel.org>","Date":"Mon, 27 Apr 2026 15:36:21 -0500","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","Subject":"Re: [PATCH 0/5] Improvements to PCI hibernate path","Content-Language":"en-US","To":"Bjorn Helgaas ","Cc":"Bjorn Helgaas ,\n \"open list:PCI SUBSYSTEM\" ,\n open list ,\n \"Rafael J . Wysocki\" , Lukas Wunner ","References":"<20260427203404.GA182096@bhelgaas>","From":"Mario Limonciello ","In-Reply-To":"<20260427203404.GA182096@bhelgaas>","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit"}}]