[{"id":3680845,"web_url":"http://patchwork.ozlabs.org/comment/3680845/","msgid":"","list_archive_url":null,"date":"2026-04-22T18:34:19","subject":"Re: [PATCH v1 0/1] arm: always enable both simd and mve builtins","submitter":{"id":93212,"url":"http://patchwork.ozlabs.org/api/people/93212/","name":"Lichenor Forgejo Bot via Sourceware Forge","email":"forge-bot+forge-bot@forge-stage.sourceware.org"},"content":"\nVersion 1 of this pull request has been stored. It includes the following commits:\n- arm: always enable both simd and mve builtins - 152d42122b80496a613e3cc19ffaf4e4e60727c6\n\n\n--\nhttps://forge.sourceware.org/gcc/gcc-TEST/pulls/63#issuecomment-5659","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)","sourceware.org; dmarc=none (p=none dis=none)\n header.from=forge-stage.sourceware.org","sourceware.org;\n spf=pass smtp.mailfrom=forge-stage.sourceware.org","server2.sourceware.org;\n arc=none smtp.remote-ip=38.145.34.39"],"Received":["from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g17kn3Ttgz1yGs\n\tfor ; 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a=rsa-sha256; d=sourceware.org; s=key; t=1776882888; cv=none;\n b=e9JOJ4Ssg3CV5CbAdwGzhXaGdcurkJ8H7Plwu50CJ6Hm3zjNfoD0u7LUUNEzzM3vKDq9UqEv48Rqpcfo/NFv7oGpnhDKnNKCjKi8JgbPnUPwIOvVIWvRF1SdOgtWycIGlvKYvIYxIxoS2GEU5VfT9ZC92h4JiTakRm3JN1SvPcg=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1776882888; c=relaxed/simple;\n bh=mKkpdQAHPxS4z0XvtCvGCwTfeo9COSvGwi869kxCslQ=;\n h=Subject:From:To:Date:Message-ID:MIME-Version;\n b=sMQkz6qYXVbwdl71x2iH7d9RxESAQpam11xd448ZBOWdtGdR9DyIfonZ8Y3dBlKv/g+zXgCuLj6ErlyQJAhAMhCZS8kqjxF1vnmPj5D079Jm4rJ79OtwT15X9YOqjfIc4EiX0ktNUz8eLa6ldEVjXLuyEY76Dyg9Vq6S4daTLXw=","ARC-Authentication-Results":"i=1; server2.sourceware.org","Subject":"Re: [PATCH v1 0/1] arm: always enable both simd and mve builtins","From":"Lichenor Forgejo Bot via Sourceware Forge\n ","To":"gcc-patches mailing list ","Date":"Wed, 22 Apr 2026 18:34:19 +0000","Message-ID":"\n ","In-Reply-To":"\n ","X-Mailer":"batrachomyomachia","X-Pull-Request-Organization":"gcc","X-Pull-Request-Repository":"gcc-TEST","X-Pull-Request":"https://forge.sourceware.org/gcc/gcc-TEST/pulls/63","X-Comment":"\n https://forge.sourceware.org/gcc/gcc-TEST/pulls/63#issuecomment-5659","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"quoted-printable","MIME-Version":"1.0","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"}},{"id":3680851,"web_url":"http://patchwork.ozlabs.org/comment/3680851/","msgid":"","list_archive_url":null,"date":"2026-04-22T18:34:46","subject":"Re: [PATCH v1 0/1] arm: always enable both simd and mve builtins","submitter":{"id":93212,"url":"http://patchwork.ozlabs.org/api/people/93212/","name":"Lichenor Forgejo Bot via Sourceware Forge","email":"forge-bot+forge-bot@forge-stage.sourceware.org"},"content":"Sent patch series version 1 containing 1 patches to gcc-patches mailing list .\n[Cover letter](https://inbox.sourceware.org/gcc-patches/bmm.hhuopdltxe.gcc.gcc-TEST.clyon.63.1.0@forge-stage.sourceware.org)\n\n--\nhttps://forge.sourceware.org/gcc/gcc-TEST/pulls/63#issuecomment-5661","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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server2.sourceware.org","Subject":"Re: [PATCH v1 0/1] arm: always enable both simd and mve builtins","From":"Lichenor Forgejo Bot via Sourceware Forge\n ","To":"gcc-patches mailing list ","Date":"Wed, 22 Apr 2026 18:34:46 +0000","Message-ID":"\n ","In-Reply-To":"\n ","X-Mailer":"batrachomyomachia","X-Pull-Request-Organization":"gcc","X-Pull-Request-Repository":"gcc-TEST","X-Pull-Request":"https://forge.sourceware.org/gcc/gcc-TEST/pulls/63","X-Comment":"\n https://forge.sourceware.org/gcc/gcc-TEST/pulls/63#issuecomment-5661","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"quoted-printable","MIME-Version":"1.0","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"}},{"id":3680857,"web_url":"http://patchwork.ozlabs.org/comment/3680857/","msgid":"","list_archive_url":null,"date":"2026-04-22T18:35:43","subject":"[SUMMARY] Re: [PATCH v1 0/1] arm: always enable both simd and mve\n builtins","submitter":{"id":92734,"url":"http://patchwork.ozlabs.org/api/people/92734/","name":"Christophe Lyon via Sourceware Forge","email":"forge-bot+clyon@forge-stage.sourceware.org"},"content":"This is a summary of discussions relative to the merge request created by Christophe Lyon (clyon) titled\narm: always enable both simd and mve builtins\nsince its creation.\n\nDescription: We get lots of error messages when compiling arm_neon.h under\ne.g. -mcpu=cortex-m55, because Neon builtins are enabled only when\n!TARGET_HAVE_MVE. This has been the case since MVE support was\nintroduced.\n\nThis patch uses an approach similar to what we do on aarch64, but only\npartially since Neon intrinsics do not use the \"new\" framework.\n\nWe register all types and Neon intrinsics, whether MVE is enabled or\nnot, which enables to compile arm_neon.h. However, we need to\nintroduce a \"switcher\" similar to aarch64's to avoid ICEs when LTO is\nenabled: in that case, since we have to enable the MVE intrinsics, we\ntemporarily change arm_active_target.isa to enable MVE bits. This\nenables hooks like arm_vector_mode_supported_p and arm_array_mode to\nbehave as expected by the MVE intrinsics framework. We switch back\nto the previous arm_active_target.isa immediately after.\n\nWith a toolchain targetting e.g. cortex-m55,\ngcc.target/arm/attr-neon3.c now compiles successfully, with only one\nfailure to be fixed separately:\nFAIL: gcc.target/arm/attr-neon3.c check-function-bodies my1\n\nBesides that, gcc.log is no longer full of errors messages when trying\nto compile arm_neon.h if MVE is forced somehow.\n\ngcc/ChangeLog:\n\n\t* config/arm/arm-builtins.cc (arm_init_simd_builtin_types): Remove\n\tTARGET_HAVE_MVE condition.\n\t(class arm_target_switcher): New.\n\t(arm_init_mve_builtins): Remove calls to\n\tarm_init_simd_builtin_types and\n\tarm_init_simd_builtin_scalar_types. Switch to MVE isa flags.\n\t(arm_init_neon_builtins): Remove calls to\n\tarm_init_simd_builtin_types and\n\tarm_init_simd_builtin_scalar_types.\n\t(arm_need_mve_mode_regs): New.\n\t(arm_need_neon_mode_regs): New.\n\t(arm_target_switcher::arm_target_switcher): New.\n\t(arm_target_switcher::~arm_target_switcher): New.\n\t(arm_init_builtins): Call arm_init_simd_builtin_scalar_types and\n\tarm_init_simd_builtin_types. Always call arm_init_mve_builtins\n\tand arm_init_neon_builtins.\n\nThanks for taking the time to contribute to GCC!\n\nPlease be advised that https://forge.sourceware.org/ is currently a trial\nthat is being used by the GCC community to experiment with a new workflow\nbased on pull requests.\n\nPull requests sent here may be forgotten or ignored. Patches that you want to\npropose for inclusion in GCC should use the existing email-based workflow,\nsee https://gcc.gnu.org/contribute.html\n\n\nThe full and up to date discussion can be found at https://forge.sourceware.org/gcc/gcc-TEST/pulls/63\n\nThe merge request has been closed without being merged directly on the forge repository.\n\n\nOn 2025-08-24 18:49:54+00:00, Christophe Lyon (clyon) wrote:\n\nnow tracked at https://forge.sourceware.org/gcc/gcc-TEST/pulls/66\n\n\n\nOn 2026-04-22 18:34:19+00:00, Lichenor Forgejo Bot (forge-bot) wrote:\n\n\nVersion 1 of this pull request has been stored. It includes the following commits:\n- arm: always enable both simd and mve builtins - 152d42122b80496a613e3cc19ffaf4e4e60727c6\n\n\n\nOn 2026-04-22 18:34:46+00:00, Lichenor Forgejo Bot (forge-bot) wrote:\n\nSent patch series version 1 containing 1 patches to gcc-patches mailing list .\n[Cover letter](https://inbox.sourceware.org/gcc-patches/bmm.hhuopdltxe.gcc.gcc-TEST.clyon.63.1.0@forge-stage.sourceware.org)","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)","sourceware.org; dmarc=none (p=none dis=none)\n header.from=forge-stage.sourceware.org","sourceware.org;\n spf=pass smtp.mailfrom=forge-stage.sourceware.org","server2.sourceware.org;\n arc=none smtp.remote-ip=38.145.34.39"],"Received":["from vm01.sourceware.org (vm01.sourceware.org\n [IPv6:2620:52:6:3111::32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g17q94HlMz1yD5\n\tfor ; Thu, 23 Apr 2026 05:01:09 +1000 (AEST)","from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id 9959C41BBF63\n\tfor ; Wed, 22 Apr 2026 19:01:07 +0000 (GMT)","from forge-stage.sourceware.org (vm08.sourceware.org [38.145.34.39])\n by sourceware.org (Postfix) with ESMTPS id 448C242CABC7\n for ; Wed, 22 Apr 2026 18:35:43 +0000 (GMT)","from forge-stage.sourceware.org (localhost [IPv6:::1])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange x25519 server-signature ECDSA (prime256v1) server-digest SHA256)\n (No client certificate requested)\n by forge-stage.sourceware.org (Postfix) with ESMTPS id 1F00F434D9\n for ; Wed, 22 Apr 2026 18:35:43 +0000 (UTC)"],"DKIM-Filter":["OpenDKIM Filter v2.11.0 sourceware.org 9959C41BBF63","OpenDKIM Filter v2.11.0 sourceware.org 448C242CABC7"],"DMARC-Filter":"OpenDMARC Filter v1.4.2 sourceware.org 448C242CABC7","ARC-Filter":"OpenARC Filter v1.0.0 sourceware.org 448C242CABC7","ARC-Seal":"i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1776882943; cv=none;\n b=w+d67CKWHk+Atn4Hfo+mDV4ToLDBN+xVvffplTnyF87WfeRapZ1v1ySdgF2pNu47QF6bM9P0wpSLk6dYnrA0vlwWwcrQH/s/EF6CEhulXwvQa4m534e0DB/a0yqwDS9wcsYISNVDanmo5B4Z0UbYRBHGlM1TGL3Vr6FzcLE6bAM=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1776882943; c=relaxed/simple;\n bh=El/pPbPhBUAcuQTRic0bvf0yq1fz4KefOc0I9Riy8/Q=;\n h=Subject:From:To:Message-ID:MIME-Version:Date;\n b=Bj8LSUHVvSy/uCtEnRxfD9brkBdM1SCPcfLe3TvP44IvHoRG1D0mUzIYJEHWQ4ESFbdh/E90z3zpeCnCJ62QM17xq+GHfTuf4takru13r7M0MjAPt/o4ko5t9jarU+gQyRDZVZSP4TfBTpFhFh/pFDjQzLD1LjEz5WnvOAQZnCI=","ARC-Authentication-Results":"i=1; server2.sourceware.org","Subject":"[SUMMARY] Re: [PATCH v1 0/1] arm: always enable both simd and mve\n builtins","From":"Christophe Lyon via Sourceware Forge\n ","To":"gcc-patches mailing list ","In-Reply-To":"\n ","Message-ID":"\n ","X-Mailer":"batrachomyomachia","X-Pull-Request-Organization":"gcc","X-Pull-Request-Repository":"gcc-TEST","X-Pull-Request":"https://forge.sourceware.org/gcc/gcc-TEST/pulls/63","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"quoted-printable","MIME-Version":"1.0","Date":"Wed, 22 Apr 2026 18:35:43 +0000 (UTC)","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"}}]