[{"id":3680092,"web_url":"http://patchwork.ozlabs.org/comment/3680092/","msgid":"<005262c8-7ac4-4bbe-9b69-39ebd8fca2f5@linaro.org>","list_archive_url":null,"date":"2026-04-21T22:22:44","subject":"Re: [PATCH v2 0/5] Defer the IOMMU translation and support\n access_type","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"Cc'ing Pierrick & Mark\n\nOn 21/4/26 18:29, Jim Shu wrote:\n> Note: v1 title is \"accel/tcg: Pass the access_type to IOMMUMemoryRegion\"\n> \n> Incoming security protection devices feature more complex IOMMUMemoryRegion\n> implementation in the CPU path than ARM MPC device. For example,\n> RISC-V wgChecker [1] may permit the access with only RO/WO permissions.\n> Consequently, the IOMMUMemoryRegion could return different sections for\n> read & write access.\n> \n> To support such IOMMUMemoryRegion behavior in the CPU path, the design\n> of IOMMU translation must be updated:\n> \n> 1. address_space_translate*() must now pass the access_type to\n> IOMMUMemoryRegion.\n> 2. Since IOMMU translation results are too complex to be fully stored\n> in the CPU TLB. we will defer the translation until the actual access\n> occurs. Also, TLB is allowed to store the untranslated IOMMU region.\n> \n> To implement deferred IOMMU translation, this patchset introduces the\n> following changes:\n> \n> 1. tlb_set_page_full() no longer translates the IOMMU region\n> immediately. Instead, it stores the untranslated region directly in\n> the TLB. A new slow-path flag, TLB_IOMMU, is introduced to force\n> access into the slow path when a region has not yet been translated\n> in the TLB entry.\n> \n> 2. When the CPU utilizes a TLB entry in the slow path, it should perform\n> the lazy IOMMU translation of the access_type first. The resulting\n> translated region and access type are stored in CPUTLBEntryFull.\n> Since the slow path always performs lazy translation first, we can\n> switch the CPUTLBEntryFull content to the correct access type before\n> use.\n> \n> 3. To accelerate memory access in the fast path, lazy translation can\n> update the addend of the CPUTLBEntry when translating the region to a\n> host memory region. We restrict the IOMMU region to have a single\n> non-zero 'addend' across all permissions. If a second 'addend' is\n> present for a CPUTLBEntry, QEMU will trigger an assertion. This\n> limitation is sufficient for security devices, as their \"secondary\"\n> region is typically an IO region used to emulate device error\n> handling when access is rejected.\n> \n> 4. To support non-slow TLB flags, lazy translation can update the TLB\n> flags in the 'addr_idx' of the CPUTLBEntry. Lazy translation only\n> updates the flags for the permissions specified in @prot. This\n> ensures that each access_type of a translated region to maintains\n> independent TLB flags. For example, TLB_DIRTY of memory region will\n> not be \"polluted\" from other permission that translated to different\n> region.\n> \n> Both RISC-V wgChecker [1] and RISC-V IOPMP [2] devices require this\n> feature.\n> \n> [1] RISC-V WG:\n> https://patchew.org/QEMU/20251021155548.584543-1-jim.shu@sifive.com/\n> [2] RISC-V IOPMP:\n> https://patchew.org/QEMU/20250312093735.1517740-1-ethan84@andestech.com/\n> \n> Changed since v1:\n> - Remove the ping-pong TLB entry behavior. Instead, defer the IOMMU\n> translation until actual access in the CPU path. Provide a IOMMU\n> lazy translation function with the special handling of 'addend'\n> and 'addr_idx' fields of CPUTLBEntry.\n> - Fix the checkpatch warning.\n> \n> \n> Jim Shu (5):\n> accel/tcg: Pass access_type as an argument of tlb_set_page*()\n> accel/tcg: address_space_translate*() will pass the correct\n> iommu_flags\n> accel/tcg: Provide early AS translate function\n> accel/tcg: Add IOMMU lazy translation function\n> accel/tcg: Support IOMMU lazy translation in CPU TLB","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=xVBU3rf3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0cLc5TKDz1yHB\n\tfor ; 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Iglesias\" ,\n Aurelien Jarno , Jiaxun Yang\n , Aleksandar Rikalo ,\n Stafford Horne , Nicholas Piggin ,\n Chinmay Rath , Glenn Miles ,\n Palmer Dabbelt ,\n Alistair Francis , Weiwei Li\n ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu ,\n Yoshinori Sato ,\n Ilya Leoshkevich , David Hildenbrand ,\n Cornelia Huck , Eric Farman ,\n Matthew Rosato ,\n Mark Cave-Ayland ,\n Artyom Tarasenko ,\n Bastian Koppelmann ,\n Max Filippov ,\n \"open list:PowerPC TCG CPUs\" ,\n \"open list:S390 TCG CPUs\" ,\n Mark Burton ","References":"<20260421162912.3295598-1-jim.shu@sifive.com>","From":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","In-Reply-To":"<20260421162912.3295598-1-jim.shu@sifive.com>","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::333;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-ppc@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}}]