[{"id":3680137,"web_url":"http://patchwork.ozlabs.org/comment/3680137/","msgid":"","list_archive_url":null,"date":"2026-04-21T23:40:54","subject":"Re: [PATCH v2 0/2] Add the implied rules for G and B extensions","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Tue, Apr 21, 2026 at 5:42 PM wrote:\n>\n> From: Frank Chang \n>\n> Add the implied rules for G and B extensions to enable the implied\n> extensions.\n>\n> Changelog:\n> v2: Remove riscv_cpu_validate_g() and riscv_cpu_validate_b() as the\n> implied extensions can be enabled by the implied rules.\n\nCan they though?\n\nThe original commit 8b3b3451052cd7a115c9352de1bb8c74ee54a62e says\n\nFor every RVG MISA bit (IMAFD), zicsr and zifencei, the logic then\nbecomes:\n\n- if enabled, do nothing;\n- if disabled and not user set, enable it;\n- if disabled and user set, throw a warning that it's a RVG mandatory\n extension.\n\nIsn't that what we want?\n\nAlistair\n\n>\n> Frank Chang (1):\n> target/riscv: Add standard B extension implied rule\n>\n> Jim Shu (1):\n> target/riscv: Add the implied rule for G extension\n>\n> target/riscv/cpu.c | 26 ++++++++++++-\n> target/riscv/tcg/tcg-cpu.c | 77 --------------------------------------\n> 2 files changed, 25 insertions(+), 78 deletions(-)\n>\n> --\n> 2.43.0\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=DTi5R/Qg;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Tue, 21 Apr 2026\n 16:41:21 -0700 (PDT)","MIME-Version":"1.0","References":"<20260421074204.2908422-1-frank.chang@sifive.com>","In-Reply-To":"<20260421074204.2908422-1-frank.chang@sifive.com>","From":"Alistair Francis ","Date":"Wed, 22 Apr 2026 09:40:54 +1000","X-Gm-Features":"AQROBzBjr-f-yCGYNvkqV_oaAwX8pbc1v6j2Tb_eDzivH7T9gehmSgn8m1_BpQM","Message-ID":"\n ","Subject":"Re: [PATCH v2 0/2] Add the implied rules for G and B extensions","To":"frank.chang@sifive.com","Cc":"qemu-devel@nongnu.org, Palmer Dabbelt ,\n Alistair Francis , Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu ,\n \"open list:RISC-V TCG CPUs\" ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2a00:1450:4864:20::631;\n envelope-from=alistair23@gmail.com; helo=mail-ej1-x631.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3681770,"web_url":"http://patchwork.ozlabs.org/comment/3681770/","msgid":"","list_archive_url":null,"date":"2026-04-24T04:22:40","subject":"Re: [PATCH v2 0/2] Add the implied rules for G and B extensions","submitter":{"id":79604,"url":"http://patchwork.ozlabs.org/api/people/79604/","name":"Frank Chang","email":"frank.chang@sifive.com"},"content":"On Wed, Apr 22, 2026 at 7:41 AM Alistair Francis \nwrote:\n\n> On Tue, Apr 21, 2026 at 5:42 PM wrote:\n> >\n> > From: Frank Chang \n> >\n> > Add the implied rules for G and B extensions to enable the implied\n> > extensions.\n> >\n> > Changelog:\n> > v2: Remove riscv_cpu_validate_g() and riscv_cpu_validate_b() as the\n> > implied extensions can be enabled by the implied rules.\n>\n> Can they though?\n>\n> The original commit 8b3b3451052cd7a115c9352de1bb8c74ee54a62e says\n>\n> For every RVG MISA bit (IMAFD), zicsr and zifencei, the logic then\n> becomes:\n>\n> - if enabled, do nothing;\n> - if disabled and not user set, enable it;\n> - if disabled and user set, throw a warning that it's a RVG mandatory\n> extension.\n>\n> Isn't that what we want?\n\n\n> Alistair\n>\n\nHi Alistair,\n\nThanks for the review.\nYou are right. I think the proper way is to remove the auto-enables in\nriscv_cpu_validate_g() and riscv_cpu_validate_b() only, but keep the\nwarnings.\n\nImplied rule won't enable the extensions that are set by the user.\nSo, if users disable the implied extension explicitly,\nwe should warn them without enabling the implied extension.\n\nFor examples,\n$ -cpu rv64,g=true,a=false\nqemu-system-riscv64: warning: RVG mandates disabled extension a\n\n$ -cpu rv64,g=true,zicsr=false\nqemu-system-riscv64: warning: RVG mandates disabled extension zicsr\nqemu-system-riscv64: F extension requires Zicsr\n\n$ -cpu rv64,b=true,zbb=false\nqemu-system-riscv64: warning: RVB mandates disabled extension zbb\n\nHowever, if user sets\"g=true\" or \"b=true\", the implied extensions will be\nenabled by the implied rules.\n\nI will fix it and send out a new patchset.\n\nRegards,\nFrank Chang\n\n>\n> >\n> > Frank Chang (1):\n> > target/riscv: Add standard B extension implied rule\n> >\n> > Jim Shu (1):\n> > target/riscv: Add the implied rule for G extension\n> >\n> > target/riscv/cpu.c | 26 ++++++++++++-\n> > target/riscv/tcg/tcg-cpu.c | 77 --------------------------------------\n> > 2 files changed, 25 insertions(+), 78 deletions(-)\n> >\n> > --\n> > 2.43.0\n> >\n> >\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=bRfnvor1;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Thu, 23 Apr 2026\n 21:22:52 -0700 (PDT)","MIME-Version":"1.0","References":"<20260421074204.2908422-1-frank.chang@sifive.com>\n ","In-Reply-To":"\n ","From":"Frank Chang ","Date":"Fri, 24 Apr 2026 12:22:40 +0800","X-Gm-Features":"AQROBzDehgGVBOEu4wpD2iDAgnRSHveVxfHuY8WdFuWd3E0Q9YCkjTHvNugJpn8","Message-ID":"\n ","Subject":"Re: [PATCH v2 0/2] Add the implied rules for G and B extensions","To":"Alistair Francis ","Cc":"qemu-devel@nongnu.org, Palmer Dabbelt ,\n Alistair Francis , Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu ,\n \"open list:RISC-V TCG CPUs\" ","Content-Type":"multipart/alternative; boundary=\"0000000000004ce61206502d1ed6\"","Received-SPF":"pass client-ip=2a00:1450:4864:20::52b;\n envelope-from=frank.chang@sifive.com; helo=mail-ed1-x52b.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}}]