[{"id":3682339,"web_url":"http://patchwork.ozlabs.org/comment/3682339/","msgid":"<20260425193152.38f80bf1@jic23-huawei>","list_archive_url":null,"date":"2026-04-25T18:31:52","subject":"Re: [PATCH v8 0/6] iio: adc: ad4691: add driver for AD4691\n multichannel SAR ADC family","submitter":{"id":10151,"url":"http://patchwork.ozlabs.org/api/people/10151/","name":"Jonathan Cameron","email":"jic23@kernel.org"},"content":"On Thu, 16 Apr 2026 12:18:45 +0300\nRadu Sabau via B4 Relay <devnull+radu.sabau.analog.com@kernel.org> wrote:\n\n> This series adds support for the Analog Devices AD4691 family of\n> high-speed, low-power multichannel successive approximation register\n> (SAR) ADCs with an SPI-compatible serial interface.\n> \n> The family includes:\n>   - AD4691: 16-channel, 500 kSPS\n>   - AD4692: 16-channel, 1 MSPS\n>   - AD4693: 8-channel, 500 kSPS\n>   - AD4694: 8-channel, 1 MSPS\n> \n> The devices support two operating modes, auto-detected from the device\n> tree:\n>   - CNV Burst Mode: external PWM drives CNV independently of SPI;\n>                     DATA_READY on a GP pin signals end of conversion\n>   - Manual Mode: CNV tied to SPI CS; each SPI transfer reads\n>                   the previous conversion result and starts the\n>                   next (pipelined N+1 scheme)\n> \n> A new driver is warranted rather than extending ad4695: the AD4691\n> data path uses an accumulator-register model — results are read from\n> AVG_IN registers, with ACC_MASK, ADC_SETUP, DEVICE_SETUP, and\n> GPIO_MODE registers controlling the sequencer — none of which exist\n> in AD4695. CNV Burst Mode (PWM drives CNV independently of SPI) and\n> Manual Mode (pipelined N+1 transfers) also have no equivalent in\n> AD4695's command-embedded single-cycle protocol.\n> \n> The series is structured as follows:\n>   1/6 - DT bindings (YAML schema) and MAINTAINERS entry\n>   2/6 - Initial driver: register map via custom regmap callbacks,\n>         IIO read_raw/write_raw, both operating modes, single-channel\n>         reads via internal oscillator (Autonomous Mode)\n>   3/6 - Triggered buffer support: IRQ-driven (DATA_READY on a GP pin\n>         selected via interrupt-names) for CNV Burst Mode; external IIO\n>         trigger for Manual Mode to handle the pipelined N+1 SPI protocol\n>   4/6 - SPI Engine offload support: DMA-backed high-throughput\n>         capture path using the SPI offload subsystem\n>   5/6 - Per-channel oversampling ratio support for CNV Burst Mode\n>   6/6 - Driver documentation (Documentation/iio/ad4691.rst)\n> \n> Datasheets:\n>   https://www.analog.com/en/products/ad4691.html\n>   https://www.analog.com/en/products/ad4692.html\n>   https://www.analog.com/en/products/ad4693.html\n>   https://www.analog.com/en/products/ad4694.html\n> \n> Signed-off-by: Radu Sabau <radu.sabau@analog.com>\ndrivers/iio/adc/ad4691.c: note: in included file:                                     \n./include/linux/bitmap.h:845:55: warning: shift too big (64) for type unsigned long   \n./include/linux/bitmap.h:845:55: warning: shift too big (64) for type unsigned long   \n./include/linux/bitmap.h:845:55: warning: shift too big (64) for type unsigned long   \n./include/linux/bitmap.h:845:55: warning: shift too big (64) for type unsigned long\n\nFrom sparse.  I think it's a false positive.\nIt's the bitmap_read() calls - probably the the nbits parameter.\nUsing bitmap_read() to copy the whole bitmap is unusual so maybe this is a corner\ncase that isn't handled. \n\nAny ideas?  I'm going to assume it's a false positive due to the ACCESS_PRIVATE()\nconfusing sparse.\n\nSo with that in mind, series applied to the testing branch of iio.git.\n\nthanks,\n\nJonathan","headers":{"Return-Path":"\n <linux-pwm+bounces-8693-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=ZmpgNkeJ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pwm+bounces-8693-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"ZmpgNkeJ\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g2z8W5sSqz1y2d\n\tfor <incoming@patchwork.ozlabs.org>; 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