[{"id":3677877,"web_url":"http://patchwork.ozlabs.org/comment/3677877/","msgid":"","list_archive_url":null,"date":"2026-04-16T00:16:48","subject":"Re: [PATCH v2 0/4] hw/riscv: Boot setup improvements","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Wed, Apr 15, 2026 at 4:50 PM Joel Stanley wrote:\n>\n> v2: Tweak commit message in patch 4, add Daniel's r-b\n>\n> The first two patches improve the boot infrastructure for riscv so\n> machines with split memory regions can load payloads into the correct\n> region.\n>\n> The second two patches improve usability when attempting to run opensbi\n> in less common situations.\n>\n> This series are prerequisites for the Atlantis machine.\n>\n> Nicholas Piggin (4):\n> hw/riscv/boot: Describe discontiguous memory in boot_info\n> hw/riscv/boot: Account for discontiguous memory when loading firmware\n> hw/riscv/boot: Warn if a ELF format file is loaded as a binary\n> hw/riscv/boot: Provide a simple halting payload\n\nI have pulled out and applied patch 3 to help, as I know this series\nand a few others from you got lost with some mailing list issues I\nhad.\n\nIn future please ping patches if you think they have been ignored,\nhttps://www.qemu.org/docs/master/devel/submitting-a-patch.html#if-your-patch-seems-to-have-been-ignored\n\nAlistair\n\n>\n> include/hw/riscv/boot.h | 14 +++++++-\n> hw/riscv/boot.c | 73 ++++++++++++++++++++++++++++++++------\n> hw/riscv/microchip_pfsoc.c | 6 ++--\n> hw/riscv/opentitan.c | 6 ++--\n> hw/riscv/shakti_c.c | 6 +++-\n> hw/riscv/sifive_u.c | 3 +-\n> hw/riscv/spike.c | 6 ++--\n> hw/riscv/virt.c | 7 ++--\n> hw/riscv/xiangshan_kmh.c | 6 +++-\n> 9 files changed, 104 insertions(+), 23 deletions(-)\n>\n> --\n> 2.47.3\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=o2bwcskF;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Wed, 15 Apr 2026\n 17:17:14 -0700 (PDT)","MIME-Version":"1.0","References":"<20260415064838.652297-1-joel@jms.id.au>","In-Reply-To":"<20260415064838.652297-1-joel@jms.id.au>","From":"Alistair Francis ","Date":"Thu, 16 Apr 2026 10:16:48 +1000","X-Gm-Features":"AQROBzAk_ENYIncnpfyRYu8XeRktvBIo40uqJ_r-Wd4oG7Gl-iwKp44cWyv2mvo","Message-ID":"\n ","Subject":"Re: [PATCH v2 0/4] hw/riscv: Boot setup improvements","To":"Joel Stanley ","Cc":"Alistair Francis ,\n Daniel Henrique Barboza ,\n qemu-devel@nongnu.org,\n Weiwei Li , Michael Ellerman ,\n Joel Stanley ,\n Nick Piggin ,\n Anirudh Srinivasan , qemu-riscv@nongnu.org","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2a00:1450:4864:20::634;\n envelope-from=alistair23@gmail.com; helo=mail-ej1-x634.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}}]