[{"id":3674883,"web_url":"http://patchwork.ozlabs.org/comment/3674883/","msgid":"<58f386b1-ae83-4faa-a05a-3f36d3bc2e51@linaro.org>","list_archive_url":null,"date":"2026-04-07T21:35:39","subject":"Re: [PATCH v10 00/21] target/arm: single-binary","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 7/4/26 21:59, Pierrick Bouvier wrote:\n> This series tackles (most of) the rest of target/arm, especially tcg folder.\n> \n> We extract tcg memory operation in a new header, with a new type representing\n> virtual addresses.\n> \n> Initially, I went down the way to have a dynamic definition of TCGv, which\n> required much more boilerplate and runtime checks. After discussing with\n> Richard, I realized it was not needed, and that could simply split 32 and 64 bit\n> properly in different files instead. This approach will not work with other\n> architectures, requiring something else, but it's enough for target/arm.\n> \n> Files left are:\n> - target/arm/tcg/mve_helper.c\n> - target/arm/tcg/m_helper.c\n> - target/arm/tcg/cpu32.c\n\nI remember having an issue with cpu32.c when it registers TYPE_CPU QOM\nobjects, \"max\" overlaps with cpu64.c one.\n\nAs a kludge we could rename arm_max_initfn -> aarch64_max_tcg_initfn\nand move it to target/arm/tcg/stubs32.c =)","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=vxNCfNTX;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (unknown [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frWs002Z5z1xy1\n\tfor ; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::335;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3674930,"web_url":"http://patchwork.ozlabs.org/comment/3674930/","msgid":"","list_archive_url":null,"date":"2026-04-07T22:25:26","subject":"Re: [PATCH v10 00/21] target/arm: single-binary","submitter":{"id":85798,"url":"http://patchwork.ozlabs.org/api/people/85798/","name":"Pierrick Bouvier","email":"pierrick.bouvier@linaro.org"},"content":"On 4/7/26 12:59 PM, Pierrick Bouvier wrote:\n> This series tackles (most of) the rest of target/arm, especially tcg folder.\n> \n> We extract tcg memory operation in a new header, with a new type representing\n> virtual addresses.\n> \n> Initially, I went down the way to have a dynamic definition of TCGv, which\n> required much more boilerplate and runtime checks. After discussing with\n> Richard, I realized it was not needed, and that could simply split 32 and 64 bit\n> properly in different files instead. This approach will not work with other\n> architectures, requiring something else, but it's enough for target/arm.\n> \n> Files left are:\n> - target/arm/tcg/mve_helper.c\n> - target/arm/tcg/m_helper.c\n> - target/arm/tcg/cpu32.c\n> \n> v10\n> ---\n> \n> - extract patch for endianness handling in arm_disas_set_info\n> - added some comments\n> \n> v9\n> --\n> \n> - introduce aarch64_translate_code *before* adding parameter to translator_loop\n> - use TCG_TYPE_VA as address type for translator_loop\n> - remove inline marker on functions merged from arm_ldst.h to translate.c\n> - refactor arm_ldl_code/arm_lduw_code\n> \n> v8\n> --\n> \n> - make translate.c compilation unit common.\n> \n> v7\n> --\n> \n> - add parameter to translator_loop to indicate address type for current tb.\n> - remove TCGv from target/arm/tcg/translate.c\n> \n> v6\n> --\n> \n> - meson.build: extract decode files in separate variables and explicitly include\n> them in user and system code. The duplication is now minimized: one instance\n> for all system binaries, and one per user binary.\n> \n> v5\n> --\n> \n> - reimplemented what v0 did with new approach defining new tcg-op-mem header\n> - reapply all straightforward patches from v0\n> - only translate.c is left, but first want to validate that changes here are ok\n> for maintainers before doing more.\n> \n> v0\n> --\n> \n> See original thread:\n> https://lore.kernel.org/qemu-devel/20260109053158.2800705-1-pierrick.bouvier@linaro.org/#t\n> \n> Note about v1 -> v4\n> -------------------\n> \n> - After v0 which was trying to do too many changes, v1 to v4 focused on smaller\n> things, and all patches have been merged already.\n> https://patchew.org/QEMU/20260219040150.2098396-1-pierrick.bouvier@linaro.org/\n> \n> Pierrick Bouvier (21):\n> include/tcg/tcg-op: extract memory operations to tcg-op-mem.h\n> target/arm/translate.h: remove tcg-op.h include\n> target/arm/tcg/translate.h: remove tcg-op-gvec.h include\n> target/arm/tcg/translate.h: remove TARGET_AARCH64\n> target/arm/tcg/translate-vfp.c: make compilation unit common\n> target/arm/tcg/translate-neon.c: make compilation unit common\n> target/arm/tcg/translate-mve.c: make compilation unit common\n> target/arm/tcg/translate-m-nocp.c: make compilation unit common\n> target/arm/tcg/op_helper.c: make compilation unit common\n> target/arm/tcg/gengvec.c: make compilation unit common\n> target/arm/tcg/translate.c: remove MO_TE usage\n> target/arm/tcg/translate.c: replace target_ulong with uint32_t\n> target/arm/tcg/translate.c: extract aarch64_translate_code()\n> tcg/translator: add parameter to translator_loop for current addr type\n> target/arm/tcg/translate.c: replace TCGv with TCGv_va\n> target/arm/tcg/translate-a64.c: use translator_ldl_end instead of\n> arm_ldl_code\n> target/arm/tcg/arm_ldst.h: merge in translate.c\n> target/arm/tcg/translate.c: replace translator_ldl_swap with\n> translator_ldl_end\n> target/arm/cpu.c: simplify endianness handling in arm_disas_set_info\n> target/arm/tcg/translate.c: remove target_ulong\n> target/arm/tcg/translate.c: make compilation unit common\n> \n> include/exec/translator.h | 4 +-\n> include/tcg/tcg-op-mem.h | 126 +++++++++++++++++++++++++++++++\n> include/tcg/tcg-op.h | 100 +-----------------------\n> target/arm/internals.h | 2 +\n> target/arm/tcg/arm_ldst.h | 47 ------------\n> target/arm/tcg/translate.h | 14 +---\n> accel/tcg/translate-all.c | 1 -\n> accel/tcg/translator.c | 4 +-\n> target/alpha/translate.c | 3 +-\n> target/arm/cpu.c | 6 +-\n> target/arm/tcg/op_helper.c | 1 -\n> target/arm/tcg/stubs32.c | 24 ++++++\n> target/arm/tcg/translate-a64.c | 17 ++++-\n> target/arm/tcg/translate-sme.c | 1 +\n> target/arm/tcg/translate-sve.c | 1 +\n> target/arm/tcg/translate.c | 73 +++++++++++-------\n> target/avr/translate.c | 3 +-\n> target/hexagon/translate.c | 3 +-\n> target/hppa/translate.c | 3 +-\n> target/i386/tcg/translate.c | 3 +-\n> target/loongarch/tcg/translate.c | 3 +-\n> target/m68k/translate.c | 3 +-\n> target/microblaze/translate.c | 3 +-\n> target/mips/tcg/translate.c | 3 +-\n> target/or1k/translate.c | 3 +-\n> target/ppc/translate.c | 3 +-\n> target/riscv/translate.c | 3 +-\n> target/rx/translate.c | 3 +-\n> target/s390x/tcg/translate.c | 3 +-\n> target/sh4/translate.c | 3 +-\n> target/sparc/translate.c | 3 +-\n> target/tricore/translate.c | 3 +-\n> target/xtensa/translate.c | 3 +-\n> target/arm/tcg/meson.build | 57 ++++++++++----\n> 34 files changed, 304 insertions(+), 228 deletions(-)\n> create mode 100644 include/tcg/tcg-op-mem.h\n> create mode 100644 target/arm/tcg/stubs32.c\n> \n\nv11 sent:\nhttps://lore.kernel.org/qemu-devel/20260407222208.271838-1-pierrick.bouvier@linaro.org/\n\nRegards,\nPierrick","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=ESSy5rs3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::102f;\n envelope-from=pierrick.bouvier@linaro.org; helo=mail-pj1-x102f.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3674949,"web_url":"http://patchwork.ozlabs.org/comment/3674949/","msgid":"","list_archive_url":null,"date":"2026-04-07T22:09:20","subject":"Re: [PATCH v10 19.5/21] linux-user/arm: Inline bswap_code()","submitter":{"id":85798,"url":"http://patchwork.ozlabs.org/api/people/85798/","name":"Pierrick Bouvier","email":"pierrick.bouvier@linaro.org"},"content":"On 4/7/26 2:23 PM, Philippe Mathieu-Daudé wrote:\n> bswap_code() is now used once in get_user_code_u32(),\n> inline it and simplify removing dead system code.\n> \n> Signed-off-by: Philippe Mathieu-Daudé \n> ---\n> target/arm/cpu.h | 16 ----------------\n> linux-user/arm/cpu_loop.c | 10 ++++++++++\n> 2 files changed, 10 insertions(+), 16 deletions(-)\n> \n> diff --git a/target/arm/cpu.h b/target/arm/cpu.h\n> index 657ff4ab20b..917e9919e8c 100644\n> --- a/target/arm/cpu.h\n> +++ b/target/arm/cpu.h\n> @@ -2568,22 +2568,6 @@ static inline int sme_vq(CPUARMState *env)\n> return EX_TBFLAG_A64(env->hflags, SVL) + 1;\n> }\n> \n> -static inline bool bswap_code(bool sctlr_b)\n> -{\n> -#ifdef CONFIG_USER_ONLY\n> - /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian.\n> - * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0\n> - * would also end up as a mixed-endian mode with BE code, LE data.\n> - */\n> - return TARGET_BIG_ENDIAN ^ sctlr_b;\n> -#else\n> - /* All code access in ARM is little endian, and there are no loaders\n> - * doing swaps that need to be reversed\n> - */\n> - return 0;\n> -#endif\n> -}\n> -\n> enum {\n> QEMU_PSCI_CONDUIT_DISABLED = 0,\n> QEMU_PSCI_CONDUIT_SMC = 1,\n> diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c\n> index 19874f4c727..24a66b52cee 100644\n> --- a/linux-user/arm/cpu_loop.c\n> +++ b/linux-user/arm/cpu_loop.c\n> @@ -29,6 +29,16 @@\n> #include \"user/page-protection.h\"\n> #include \"target/arm/syndrome.h\"\n> \n> +static inline bool bswap_code(bool sctlr_b)\n> +{\n> + /*\n> + * BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian.\n> + * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0\n> + * would also end up as a mixed-endian mode with BE code, LE data.\n> + */\n> + return TARGET_BIG_ENDIAN ^ sctlr_b;\n> +}\n> +\n> #define get_user_code_u32(x, gaddr, env) \\\n> ({ abi_long __r = get_user_u32((x), (gaddr)); \\\n> if (!__r && bswap_code(arm_sctlr_b(env))) { \\\n\nI don't think so, Richard wants to remove bswap_code completely and \nget_user_code_u32 is last usage of it. I'm waiting for his patch to \nintegrate it in series.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=e+sAl1tc;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frY8j3s2vz1xv0\n\tfor ; Thu, 09 Apr 2026 05:31:33 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wAYWR-0006nC-RZ; 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