[{"id":3673927,"web_url":"http://patchwork.ozlabs.org/comment/3673927/","msgid":"","list_archive_url":null,"date":"2026-04-07T02:29:10","subject":"Re: [PATCH v8 00/20] target/arm: single-binary","submitter":{"id":85798,"url":"http://patchwork.ozlabs.org/api/people/85798/","name":"Pierrick Bouvier","email":"pierrick.bouvier@linaro.org"},"content":"On 4/6/26 11:25 AM, Pierrick Bouvier wrote:\n> This series tackles (most of) the rest of target/arm, especially tcg folder.\n> \n> We extract tcg memory operation in a new header, with a new type representing\n> virtual addresses.\n> \n> Initially, I went down the way to have a dynamic definition of TCGv, which\n> required much more boilerplate and runtime checks. After discussing with\n> Richard, I realized it was not needed, and that could simply split 32 and 64 bit\n> properly in different files instead. This approach will not work with other\n> architectures, requiring something else, but it's enough for target/arm.\n> \n> Files left are:\n> - target/arm/tcg/mve_helper.c\n> - target/arm/tcg/m_helper.c\n> - target/arm/tcg/cpu32.c\n> \n> v8\n> --\n> \n> - make translate.c compilation unit common.\n> \n> v7\n> --\n> \n> - add parameter to translator_loop to indicate address type for current tb.\n> - remove TCGv from target/arm/tcg/translate.c\n> \n> v6\n> --\n> \n> - meson.build: extract decode files in separate variables and explicitly include\n> them in user and system code. The duplication is now minimized: one instance\n> for all system binaries, and one per user binary.\n> \n> v5\n> --\n> \n> - reimplemented what v0 did with new approach defining new tcg-op-mem header\n> - reapply all straightforward patches from v0\n> - only translate.c is left, but first want to validate that changes here are ok\n> for maintainers before doing more.\n> \n> v0\n> --\n> \n> See original thread:\n> https://lore.kernel.org/qemu-devel/20260109053158.2800705-1-pierrick.bouvier@linaro.org/#t\n> \n> Note about v1 -> v4\n> -------------------\n> \n> - After v0 which was trying to do too many changes, v1 to v4 focused on smaller\n> things, and all patches have been merged already.\n> https://patchew.org/QEMU/20260219040150.2098396-1-pierrick.bouvier@linaro.org/\n> \n> Pierrick Bouvier (20):\n> include/tcg/tcg-op: extract memory operations to tcg-op-mem.h\n> target/arm/translate.h: remove tcg-op.h include\n> target/arm/tcg/translate.h: remove tcg-op-gvec.h include\n> target/arm/tcg/translate.h: remove TARGET_AARCH64\n> target/arm/tcg/translate-vfp.c: make compilation unit common\n> target/arm/tcg/translate-neon.c: make compilation unit common\n> target/arm/tcg/translate-mve.c: make compilation unit common\n> target/arm/tcg/translate-m-nocp.c: make compilation unit common\n> target/arm/tcg/op_helper.c: make compilation unit common\n> target/arm/tcg/gengvec.c: make compilation unit common\n> target/arm/tcg/translate.c: remove MO_TE usage\n> target/arm/tcg/translate.c: replace target_ulong with uint32_t\n> tcg/translator: add parameter to translator_loop for current addr type\n> target/arm/tcg/translate.c: replace TCGv with TCGv_va\n> target/arm/tcg/translate-a64.c: use translator_ldl_end instead of\n> arm_ldl_code\n> target/arm/tcg/arm_ldst.h: merge in translate.c\n> target/arm/tcg/translate.c: replace translator_ldl_swap with\n> translator_ldl_end\n> target/arm/tcg/translate.c: remove target_ulong\n> target/arm/tcg/translate.c: remove TARGET_AARCH64\n> target/arm/tcg/translate.c: make compilation unit common\n> \n> include/exec/translator.h | 4 +-\n> include/tcg/tcg-op-mem.h | 126 +++++++++++++++++++++++++++++++\n> include/tcg/tcg-op.h | 100 +-----------------------\n> include/tcg/tcg.h | 5 ++\n> target/arm/internals.h | 2 +\n> target/arm/tcg/arm_ldst.h | 47 ------------\n> target/arm/tcg/translate.h | 14 +---\n> accel/tcg/translator.c | 4 +-\n> target/alpha/translate.c | 3 +-\n> target/arm/tcg/op_helper.c | 1 -\n> target/arm/tcg/stubs32.c | 24 ++++++\n> target/arm/tcg/translate-a64.c | 14 +++-\n> target/arm/tcg/translate-sme.c | 1 +\n> target/arm/tcg/translate-sve.c | 1 +\n> target/arm/tcg/translate.c | 80 +++++++++++++-------\n> target/avr/translate.c | 3 +-\n> target/hexagon/translate.c | 3 +-\n> target/hppa/translate.c | 3 +-\n> target/i386/tcg/translate.c | 3 +-\n> target/loongarch/tcg/translate.c | 3 +-\n> target/m68k/translate.c | 3 +-\n> target/microblaze/translate.c | 3 +-\n> target/mips/tcg/translate.c | 3 +-\n> target/or1k/translate.c | 3 +-\n> target/ppc/translate.c | 3 +-\n> target/riscv/translate.c | 3 +-\n> target/rx/translate.c | 3 +-\n> target/s390x/tcg/translate.c | 3 +-\n> target/sh4/translate.c | 3 +-\n> target/sparc/translate.c | 3 +-\n> target/tricore/translate.c | 3 +-\n> target/xtensa/translate.c | 3 +-\n> target/arm/tcg/meson.build | 57 ++++++++++----\n> 33 files changed, 312 insertions(+), 222 deletions(-)\n> create mode 100644 include/tcg/tcg-op-mem.h\n> create mode 100644 target/arm/tcg/stubs32.c\n> \n\nv9 sent:\nhttps://lore.kernel.org/qemu-devel/20260407022748.57629-1-pierrick.bouvier@linaro.org/T/#u\n\nRegards,\nPierrick","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=mVER0LU/;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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