[{"id":3673926,"web_url":"http://patchwork.ozlabs.org/comment/3673926/","msgid":"<20260406192312.0f7a2760@kernel.org>","list_archive_url":null,"date":"2026-04-07T02:23:12","subject":"Re: [Intel-wired-lan] [PATCH v5 net-next 0/8] dpll/ice: Add TXC\n DPLL type and full TX reference clock control for E825","submitter":{"id":77159,"url":"http://patchwork.ozlabs.org/api/people/77159/","name":"Jakub Kicinski","email":"kuba@kernel.org"},"content":"On Fri, 3 Apr 2026 01:06:18 +0200 Grzegorz Nitka wrote:\n> This series adds TX reference clock support for E825 devices and exposes\n> TX clock selection and synchronization status via the Linux DPLL\n> subsystem.\n> E825 hardware contains a dedicated Tx clock (TXC) domain that is\n> distinct\n> from PPS and EEC. TX reference clock selection is device‑wide, shared\n> across ports, and mediated by firmware as part of the link bring‑up\n> process. As a result, TX clock selection intent may differ from the\n> effective hardware configuration, and software must verify the outcome\n> after link‑up.\n> To support this, the series introduces TXC support incrementally across\n> the DPLL core and the ice driver:\n> \n> - add a new DPLL type (TXC) to represent transmit clock generators;\n\nI'm not grasping why this is needed, isn't it part of any EEC system\nthat the DPLL can drive the TXC? Is your system going to expose multiple\nDPLLs now for one NIC?\n\n> - relax DPLL pin registration rules for firmware‑described shared pins\n> and extend pin notifications with a source identifier;\n> - allow dynamic state control of SyncE reference pins where hardware\n> supports it;\n> - add CPI infrastructure for PHY‑side TX clock control on E825C;\n> - introduce a TXC DPLL device and TX reference clock pins (EXT_EREF0 and\n> SYNCE) in the ice driver;\n> - extend the Restart Auto‑Negotiation command to carry a TX reference\n> clock index;\n> - implement hardware‑backed TX reference clock switching, post‑link\n> - verification, and TX synchronization reporting.\n> \n> TXCLK pins report TX reference topology only. Actual synchronization\n> success is reported via the TXC DPLL lock status, which is updated after\n> hardware verification: external Tx references report LOCKED, while the\n> internal ENET/TXCO source reports UNLOCKED.\n> This provides reliable TX reference selection and observability on E825\n> devices using standard DPLL interfaces, without conflating user intent\n> with effective hardware behavior.","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=1OiwEHRy;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=140.211.166.136; helo=smtp3.osuosl.org;\n envelope-from=intel-wired-lan-bounces@osuosl.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fqVNr5k5Bz1yD3\n\tfor ; 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helo=sea.source.kernel.org;\n envelope-from=kuba@kernel.org; receiver=","DMARC-Filter":"OpenDMARC Filter v1.4.2 smtp2.osuosl.org B045D400D1","Date":"Mon, 6 Apr 2026 19:23:12 -0700","From":"Jakub Kicinski ","To":"Grzegorz Nitka ","Message-ID":"<20260406192312.0f7a2760@kernel.org>","In-Reply-To":"<20260402230626.3826719-1-grzegorz.nitka@intel.com>","References":"<20260402230626.3826719-1-grzegorz.nitka@intel.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"quoted-printable","X-Mailman-Original-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=kernel.org; s=k20201202; t=1775528594;\n bh=J3G58NtGbvUyzKFU/bUdQFTxP5xxRhZEkzXFIq5Rduc=;\n h=Date:From:To:Cc:Subject:In-Reply-To:References:From;\n b=dd8dQAQcF0Pgr/mecx4sBWjNfNCim71nTp5J6mUHfx4MMbJgGpzdZ06ftrKs0GcaR\n e5vkwdJYQTahgggjKrwUSpoiiUU7N0tA67vfupAkvOIFowI9gKSu1Kir4qaxQ2rc5s\n Hk4MzvSziczHaw5PdZgjIiF9CbdD7LCgeyKaymJpskj+eqVKr6j7c0evit3/pH6gGo\n rZ1OmuF1jyOaBbAyW7tB8BIup5AQ+p0k60zm0uuT0PXnyldxiaEoOc9gwnXRdjQ1/e\n FcZ/0sm2fz0gIx83zdOlxj2nlQr2HopHpYMonRay88uUzpt3qcj8uZNNwrcsj0WtM2\n 6Rk85JDS7vG0A==","X-Mailman-Original-Authentication-Results":["smtp2.osuosl.org;\n dmarc=pass (p=quarantine dis=none)\n header.from=kernel.org","smtp2.osuosl.org;\n dkim=pass (2048-bit key,\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=dd8dQAQc"],"Subject":"Re: [Intel-wired-lan] [PATCH v5 net-next 0/8] dpll/ice: Add TXC\n DPLL type and full TX reference clock control for E825","X-BeenThere":"intel-wired-lan@osuosl.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Intel Wired Ethernet Linux Kernel Driver Development\n ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Cc":"ivecera@redhat.com, vadim.fedorenko@linux.dev, jiri@resnulli.us,\n edumazet@google.com, netdev@vger.kernel.org, richardcochran@gmail.com,\n donald.hunter@gmail.com, linux-kernel@vger.kernel.org,\n arkadiusz.kubalewski@intel.com, Prathosh.Satish@microchip.com,\n andrew+netdev@lunn.ch, intel-wired-lan@lists.osuosl.org, horms@kernel.org,\n przemyslaw.kitszel@intel.com, anthony.l.nguyen@intel.com, pabeni@redhat.com,\n davem@davemloft.net","Errors-To":"intel-wired-lan-bounces@osuosl.org","Sender":"\"Intel-wired-lan\" "}}]