[{"id":3670845,"web_url":"http://patchwork.ozlabs.org/comment/3670845/","msgid":"","list_archive_url":null,"date":"2026-03-30T04:40:38","subject":"Re: [PATCH v2 0/2] Bug fixes and IPSR.PMIP support","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Wed, Mar 25, 2026 at 3:01 PM Jay Chang wrote:\n>\n> This series contains two fixes for the RISC-V IOMMU implementation:\n>\n> 1. Fix a bug in the HPM (Hardware Performance Monitor) timer setup where\n> irq_overflow_left was not properly reset, causing stale values from\n> previous timer setups to affect new timer behavior.\n>\n> 2. Add proper RW1C (Read/Write 1 to Clear) support for the IPSR.PMIP\n> (Performance Monitor Interrupt Pending) bit, which was missing from\n> the IPSR register implementation.\n\nThanks!\n\nApplied to riscv-to-apply.next\n\nAlistair\n\n>\n> ---\n> Change in V2\n> Add commit message\n>\n> Jay Chang (2):\n> hw/riscv/riscv-iommu-hpm: Fix irq_overflow_left residual value bug\n> hw/riscv/riscv-iommu: Add IPSR.PMIP RW1C support\n>\n> hw/riscv/riscv-iommu-bits.h | 1 +\n> hw/riscv/riscv-iommu-hpm.c | 1 +\n> hw/riscv/riscv-iommu.c | 4 ++++\n> 3 files changed, 6 insertions(+)\n>\n> --\n> 2.48.1\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=dje1j4OY;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Sun, 29 Mar 2026\n 21:41:04 -0700 (PDT)","MIME-Version":"1.0","References":"<20260325050011.66722-1-jay.chang@sifive.com>","In-Reply-To":"<20260325050011.66722-1-jay.chang@sifive.com>","From":"Alistair Francis ","Date":"Mon, 30 Mar 2026 14:40:38 +1000","X-Gm-Features":"AQROBzCXaxpn2Qj2nW6jpbBGlCJ-x-p56Y0XOCXvMzprxZPk05wLlJdn49uJZrA","Message-ID":"\n ","Subject":"Re: [PATCH v2 0/2] Bug fixes and IPSR.PMIP support","To":"Jay Chang ","Cc":"qemu-devel@nongnu.org, qemu-riscv@nongnu.org,\n Palmer Dabbelt ,\n Alistair Francis ,\n Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2a00:1450:4864:20::633;\n envelope-from=alistair23@gmail.com; helo=mail-ej1-x633.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}}]