[{"id":3673473,"web_url":"http://patchwork.ozlabs.org/comment/3673473/","msgid":"","list_archive_url":null,"date":"2026-04-04T16:53:32","subject":"Re: [PATCH v5 0/3] PCI Controller event and LTSSM tracepoint support","submitter":{"id":78905,"url":"http://patchwork.ozlabs.org/api/people/78905/","name":"Manivannan Sadhasivam","email":"mani@kernel.org"},"content":"On Wed, Mar 25, 2026 at 09:58:29AM +0800, Shawn Lin wrote:\n> \n> This patch-set adds new pci controller event and LTSSM tracepoint used by host drivers\n> which provide LTSSM trace functionality. The first user is pcie-dw-rockchip with a 256\n> Bytes FIFO for recording LTSSM transition.\n> \n\nSteve, could you please take a look at the tracing part?\n\n- Mani\n\n> Testing\n> =========\n> \n> This series was tested on RK3588/RK3588s EVB1 with NVMe SSD connected to PCIe3 and PCIe2\n> root ports.\n> \n> echo 1 > /sys/kernel/debug/tracing/events/pci_controller/pcie_ltssm_state_transition/enable\n> cat /sys/kernel/debug/tracing/trace_pipe\n> \n> # tracer: nop\n> #\n> # entries-in-buffer/entries-written: 64/64 #P:8\n> #\n> # _-----=> irqs-off/BH-disabled\n> # / _----=> need-resched\n> # | / _---=> hardirq/softirq\n> # || / _--=> preempt-depth\n> # ||| / _-=> migrate-disable\n> # |||| / delay\n> # TASK-PID CPU# ||||| TIMESTAMP FUNCTION\n> # | | | ||||| | |\n> kworker/0:0-9 [000] ..... 5.600194: pcie_ltssm_state_transition: dev: a40000000.pcie state: DETECT_ACT rate: Unknown\n> kworker/0:0-9 [000] ..... 5.600198: pcie_ltssm_state_transition: dev: a40000000.pcie state: DETECT_WAIT rate: Unknown\n> kworker/0:0-9 [000] ..... 5.600199: pcie_ltssm_state_transition: dev: a40000000.pcie state: DETECT_ACT rate: Unknown\n> kworker/0:0-9 [000] ..... 5.600201: pcie_ltssm_state_transition: dev: a40000000.pcie state: POLL_ACTIVE rate: Unknown\n> kworker/0:0-9 [000] ..... 5.600202: pcie_ltssm_state_transition: dev: a40000000.pcie state: POLL_CONFIG rate: Unknown\n> kworker/0:0-9 [000] ..... 5.600204: pcie_ltssm_state_transition: dev: a40000000.pcie state: CFG_LINKWD_START rate: Unknown\n> kworker/0:0-9 [000] ..... 5.600206: pcie_ltssm_state_transition: dev: a40000000.pcie state: CFG_LINKWD_ACEPT rate: Unknown\n> kworker/0:0-9 [000] ..... 5.600207: pcie_ltssm_state_transition: dev: a40000000.pcie state: CFG_LANENUM_WAI rate: Unknown\n> kworker/0:0-9 [000] ..... 5.600208: pcie_ltssm_state_transition: dev: a40000000.pcie state: CFG_LANENUM_ACEPT rate: Unknown\n> kworker/0:0-9 [000] ..... 5.600210: pcie_ltssm_state_transition: dev: a40000000.pcie state: CFG_COMPLETE rate: Unknown\n> kworker/0:0-9 [000] ..... 5.600212: pcie_ltssm_state_transition: dev: a40000000.pcie state: CFG_IDLE rate: Unknown\n> kworker/0:0-9 [000] ..... 5.600213: pcie_ltssm_state_transition: dev: a40000000.pcie state: L0 rate: 2.5 GT/s\n> kworker/0:0-9 [000] ..... 5.600214: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_LOCK rate: Unknown\n> kworker/0:0-9 [000] ..... 5.600216: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_RCVRCFG rate: Unknown\n> kworker/0:0-9 [000] ..... 5.600217: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_SPEED rate: Unknown\n> kworker/0:0-9 [000] ..... 5.600218: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_LOCK rate: Unknown\n> kworker/0:0-9 [000] ..... 5.600220: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_EQ1 rate: Unknown\n> kworker/0:0-9 [000] ..... 5.600221: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_EQ2 rate: 8.0 GT/s\n> kworker/0:0-9 [000] ..... 5.600222: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_EQ3 rate: 8.0 GT/s\n> kworker/0:0-9 [000] ..... 5.600224: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_LOCK rate: 8.0 GT/s\n> kworker/0:0-9 [000] ..... 5.600225: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_RCVRCFG rate: 8.0 GT/s\n> kworker/0:0-9 [000] ..... 5.600226: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_IDLE rate: 8.0 GT/s\n> kworker/0:0-9 [000] ..... 5.600227: pcie_ltssm_state_transition: dev: a40000000.pcie state: L0 rate: 8.0 GT/s\n> kworker/0:0-9 [000] ..... 5.600228: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_LOCK rate: 8.0 GT/s\n> kworker/0:0-9 [000] ..... 5.600229: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_RCVRCFG rate: 8.0 GT/s\n> kworker/0:0-9 [000] ..... 5.600231: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_IDLE rate: 8.0 GT/s\n> kworker/0:0-9 [000] ..... 5.600232: pcie_ltssm_state_transition: dev: a40000000.pcie state: L0 rate: 8.0 GT/s\n> kworker/0:0-9 [000] ..... 5.600233: pcie_ltssm_state_transition: dev: a40000000.pcie state: L123_SEND_EIDLE rate: 8.0 GT/s\n> kworker/0:0-9 [000] ..... 5.600234: pcie_ltssm_state_transition: dev: a40000000.pcie state: L1_IDLE rate: 8.0 GT/s\n> kworker/0:0-9 [000] ..... 5.600236: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_LOCK rate: 8.0 GT/s\n> kworker/0:0-9 [000] ..... 5.600237: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_RCVRCFG rate: 8.0 GT/s\n> kworker/0:0-9 [000] ..... 5.600238: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_IDLE rate: 8.0 GT/s\n> kworker/0:0-9 [000] ..... 5.600239: pcie_ltssm_state_transition: dev: a40000000.pcie state: L0 rate: 8.0 GT/s\n> \n> \n> Changes in v5:\n> - rebase\n> - use EM/EMe instead\n> - remove reg/unreg function and back to use TRACE_EVENT\n> - use trace_pcie_ltssm_state_transition_enabled()\n> \n> Changes in v4:\n> - use TRACE_EVENT_FN to notify when to start and stop the tracepoint,\n> and export pci_ltssm_tp_enabled() for host drivers to use\n> - skip trace if pci_ltssm_tp_enabled() is false.(Steven)\n> - wrap into 80 columns(Bjorn)\n> \n> Changes in v3:\n> - add TRACE_DEFINE_ENUM for all enums(Steven Rostedt)\n> - Add toctree entry in Documentation/trace/index.rst(Bagas Sanjaya)\n> - fix mismatch section underline length(Bagas Sanjaya)\n> - Make example snippets in code block(Bagas Sanjaya)\n> - warp context into 80 columns and fix the file name(Bjorn)\n> - reorder variables(Mani)\n> - rename loop to i; rename en to enable(Mani)\n> - use FIELD_GET(Mani)\n> - add comment about how the FIFO works(Mani)\n> \n> Changes in v2:\n> - use tracepoint\n> \n> Shawn Lin (3):\n> PCI: trace: Add PCI controller LTSSM transition tracepoint\n> Documentation: tracing: Add PCI controller event documentation\n> PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support\n> \n> Documentation/trace/events-pci-controller.rst | 42 ++++++++++\n> Documentation/trace/index.rst | 1 +\n> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 111 ++++++++++++++++++++++++++\n> drivers/pci/trace.c | 1 +\n> include/trace/events/pci_controller.h | 58 ++++++++++++++\n> 5 files changed, 213 insertions(+)\n> create mode 100644 Documentation/trace/events-pci-controller.rst\n> create mode 100644 include/trace/events/pci_controller.h\n> \n> -- \n> 2.7.4\n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=uoLLbiIx;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n 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+0530","From":"Manivannan Sadhasivam ","To":"Steven Rostedt ,\n\tShawn Lin ","Cc":"Bjorn Helgaas ,\n\tlinux-rockchip@lists.infradead.org, linux-pci@vger.kernel.org,\n linux-trace-kernel@vger.kernel.org,\n\tlinux-doc@vger.kernel.org","Subject":"Re: [PATCH v5 0/3] PCI Controller event and LTSSM tracepoint support","Message-ID":"","References":"<1774403912-210670-1-git-send-email-shawn.lin@rock-chips.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"<1774403912-210670-1-git-send-email-shawn.lin@rock-chips.com>"}},{"id":3673766,"web_url":"http://patchwork.ozlabs.org/comment/3673766/","msgid":"<20260406110829.12f3e445@gandalf.local.home>","list_archive_url":null,"date":"2026-04-06T15:08:29","subject":"Re: [PATCH v5 0/3] PCI Controller event and LTSSM tracepoint\n support","submitter":{"id":112,"url":"http://patchwork.ozlabs.org/api/people/112/","name":"Steven Rostedt","email":"rostedt@goodmis.org"},"content":"On Sat, 4 Apr 2026 22:23:32 +0530\nManivannan Sadhasivam wrote:\n\n> On Wed, Mar 25, 2026 at 09:58:29AM +0800, Shawn Lin wrote:\n> > \n> > This patch-set adds new pci controller event and LTSSM tracepoint used by host drivers\n> > which provide LTSSM trace functionality. The first user is pcie-dw-rockchip with a 256\n> > Bytes FIFO for recording LTSSM transition.\n> > \n> \n> Steve, could you please take a look at the tracing part?\n\nI already have but didn't say anything because I didn't find anything ;-)\n\nAnyway, for the tracing part:\n\nReviewed-by: Steven Rostedt (Google) \n\n-- Steve","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; helo=sto.lore.kernel.org;\n envelope-from=linux-pci+bounces-51955-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=216.40.44.11","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=goodmis.org","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=goodmis.org"],"Received":["from sto.lore.kernel.org (sto.lore.kernel.org\n [IPv6:2600:3c09:e001:a7::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fqCNx3Nzbz1yFt\n\tfor ; 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The first user is pcie-dw-rockchip with a 256\n> Bytes FIFO for recording LTSSM transition.\n> \n> Testing\n> =========\n> \n> [...]\n\nApplied, thanks!\n\n[1/3] PCI: trace: Add PCI controller LTSSM transition tracepoint\n commit: d1b7add89c004295cd48d7cd49946ed5cb5cbb55\n[2/3] Documentation: tracing: Add PCI controller event documentation\n commit: a3966a6f915ea7d1af0941ea26848d921e574c45\n[3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support\n commit: a276c0d802d8d2a22088b7919d9e82e936995cf4\n\nBest regards,","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=ntLJzeLG;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=OG+wUWl/;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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