[{"id":3632337,"web_url":"http://patchwork.ozlabs.org/comment/3632337/","msgid":"","date":"2026-01-07T18:36:44","subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","submitter":{"id":91751,"url":"http://patchwork.ozlabs.org/api/people/91751/","name":"Matthew Brost","email":"matthew.brost@intel.com"},"content":"On Wed, Jan 07, 2026 at 08:18:12PM +1100, Jordan Niethe wrote:\n> Today, when creating these device private struct pages, the first step\n> is to use request_free_mem_region() to get a range of physical address\n> space large enough to represent the devices memory. This allocated\n> physical address range is then remapped as device private memory using\n> memremap_pages.\n> \n> Needing allocation of physical address space has some problems:\n> \n> 1) There may be insufficient physical address space to represent the\n> device memory. KASLR reducing the physical address space and VM\n> configurations with limited physical address space increase the\n> likelihood of hitting this especially as device memory increases. This\n> has been observed to prevent device private from being initialized. \n> \n> 2) Attempting to add the device private pages to the linear map at\n> addresses beyond the actual physical memory causes issues on\n> architectures like aarch64 - meaning the feature does not work there [0].\n> \n> This series changes device private memory so that it does not require\n> allocation of physical address space and these problems are avoided.\n> Instead of using the physical address space, we introduce a \"device\n> private address space\" and allocate from there.\n> \n> A consequence of placing the device private pages outside of the\n> physical address space is that they no longer have a PFN. However, it is\n> still necessary to be able to look up a corresponding device private\n> page from a device private PTE entry, which means that we still require\n> some way to index into this device private address space. Instead of a\n> PFN, device private pages use an offset into this device private address\n> space to look up device private struct pages.\n> \n> The problem that then needs to be addressed is how to avoid confusing\n> these device private offsets with PFNs. It is the inherent limited usage\n> of the device private pages themselves which make this possible. A\n> device private page is only used for userspace mappings, we do not need\n> to be concerned with them being used within the mm more broadly. This\n> means that the only way that the core kernel looks up these pages is via\n> the page table, where their PTE already indicates if they refer to a\n> device private page via their swap type, e.g. SWP_DEVICE_WRITE. We can\n> use this information to determine if the PTE contains a PFN which should\n> be looked up in the page map, or a device private offset which should be\n> looked up elsewhere.\n> \n> This applies when we are creating PTE entries for device private pages -\n> because they have their own type there are already must be handled\n> separately, so it is a small step to convert them to a device private\n> PFN now too.\n> \n> The first part of the series updates callers where device private\n> offsets might now be encountered to track this extra state.\n> \n> The last patch contains the bulk of the work where we change how we\n> convert between device private pages to device private offsets and then\n> use a new interface for allocating device private pages without the need\n> for reserving physical address space.\n> \n> By removing the device private pages from the physical address space,\n> this series also opens up the possibility to moving away from tracking\n> device private memory using struct pages in the future. This is\n> desirable as on systems with large amounts of memory these device\n> private struct pages use a signifiant amount of memory and take a\n> significant amount of time to initialize.\n> \n> *** Changes in v2 ***\n> \n> The most significant change in v2 is addressing code paths that are\n> common between MEMORY_DEVICE_PRIVATE and MEMORY_DEVICE_COHERENT devices.\n> \n> This had been overlooked in previous revisions.\n> \n> To do this we introduce a migrate_pfn_from_page() helper which will call\n> device_private_offset_to_page() and set the MIGRATE_PFN_DEVICE_PRIVATE\n> flag if required.\n> \n> In places where we could have a device private offset\n> (MEMORY_DEVICE_PRIVATE) or a pfn (MEMORY_DEVICE_COHERENT) we update to\n> use an mpfn to disambiguate. This includes some users in the drivers\n> and migrate_device_{pfns,range}().\n> \n> Seeking opinions on using the mpfns like this or if a new type would be\n> preferred.\n> \n> - mm/migrate_device: Introduce migrate_pfn_from_page() helper\n> - New to series\n> \n> - drm/amdkfd: Use migrate pfns internally\n> - New to series\n> \n> - mm/migrate_device: Make migrate_device_{pfns,range}() take mpfns\n> - New to series\n> \n> - mm/migrate_device: Add migrate PFN flag to track device private pages\n> - Update for migrate_pfn_from_page()\n> - Rename to MIGRATE_PFN_DEVICE_PRIVATE\n> - drm/amd: Check adev->gmc.xgmi.connected_to_cpu\n> - lib/test_hmm.c: Check chunk->pagemap.type == MEMORY_DEVICE_PRIVATE\n> \n> - mm: Add helpers to create migration entries from struct pages\n> - Add a flags param\n> \n> - mm: Add a new swap type for migration entries of device private pages\n> - Add softleaf_is_migration_device_private_read()\n> \n> - mm: Add helpers to create device private entries from struct pages\n> - Add a flags param\n> \n> - mm: Remove device private pages from the physical address space\n> - Make sure last member of struct dev_pagemap remains DECLARE_FLEX_ARRAY(struct range, ranges);\n> \n> Testing:\n> - selftests/mm/hmm-tests on an amd64 VM\n> \n> * NOTE: I will need help in testing the driver changes *\n> \n\nThanks for the series. For some reason Intel's CI couldn't apply this\nseries to drm-tip to get results [1]. I'll manually apply this and run all\nour SVM tests and get back you on results + review the changes here. For\nfuture reference if you want to use our CI system, the series must apply\nto drm-tip, feel free to rebase this series and just send to intel-xe\nlist if you want CI results.\n\nI was also wondering if Nvidia could help review one our core MM patches\n[2] which is gating enabling 2M device pages too?\n\nMatt\n\n[1] https://patchwork.freedesktop.org/series/159738/\n[2] https://patchwork.freedesktop.org/patch/694775/?series=159119&rev=1 \n\n> Revisions:\n> - RFC: https://lore.kernel.org/all/20251128044146.80050-1-jniethe@nvidia.com/\n> - v1: https://lore.kernel.org/all/20251231043154.42931-1-jniethe@nvidia.com/\n> \n> [0] https://lore.kernel.org/lkml/CAMj1kXFZ=4hLL1w6iCV5O5uVoVLHAJbc0rr40j24ObenAjXe9w@mail.gmail.com/\n> \n> Jordan Niethe (11):\n> mm/migrate_device: Introduce migrate_pfn_from_page() helper\n> drm/amdkfd: Use migrate pfns internally\n> mm/migrate_device: Make migrate_device_{pfns,range}() take mpfns\n> mm/migrate_device: Add migrate PFN flag to track device private pages\n> mm/page_vma_mapped: Add flags to page_vma_mapped_walk::pfn to track\n> device private pages\n> mm: Add helpers to create migration entries from struct pages\n> mm: Add a new swap type for migration entries of device private pages\n> mm: Add helpers to create device private entries from struct pages\n> mm/util: Add flag to track device private pages in page snapshots\n> mm/hmm: Add flag to track device private pages\n> mm: Remove device private pages from the physical address space\n> \n> Documentation/mm/hmm.rst | 11 +-\n> arch/powerpc/kvm/book3s_hv_uvmem.c | 43 ++---\n> drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 45 +++---\n> drivers/gpu/drm/amd/amdkfd/kfd_migrate.h | 2 +-\n> drivers/gpu/drm/drm_pagemap.c | 11 +-\n> drivers/gpu/drm/nouveau/nouveau_dmem.c | 45 ++----\n> drivers/gpu/drm/xe/xe_svm.c | 37 ++---\n> fs/proc/page.c | 6 +-\n> include/drm/drm_pagemap.h | 8 +-\n> include/linux/hmm.h | 7 +-\n> include/linux/leafops.h | 116 ++++++++++++--\n> include/linux/memremap.h | 64 +++++++-\n> include/linux/migrate.h | 23 ++-\n> include/linux/mm.h | 9 +-\n> include/linux/rmap.h | 33 +++-\n> include/linux/swap.h | 8 +-\n> include/linux/swapops.h | 136 ++++++++++++++++\n> lib/test_hmm.c | 86 ++++++----\n> mm/debug.c | 9 +-\n> mm/hmm.c | 5 +-\n> mm/huge_memory.c | 43 ++---\n> mm/hugetlb.c | 15 +-\n> mm/memory.c | 5 +-\n> mm/memremap.c | 193 ++++++++++++++++++-----\n> mm/migrate.c | 6 +-\n> mm/migrate_device.c | 76 +++++----\n> mm/mm_init.c | 8 +-\n> mm/mprotect.c | 10 +-\n> mm/page_vma_mapped.c | 32 +++-\n> mm/rmap.c | 59 ++++---\n> mm/util.c | 8 +-\n> mm/vmscan.c | 2 +-\n> 32 files changed, 822 insertions(+), 339 deletions(-)\n> \n> \n> base-commit: f8f9c1f4d0c7a64600e2ca312dec824a0bc2f1da\n> -- \n> 2.34.1\n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) 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lists.ozlabs.org"}},{"id":3632346,"web_url":"http://patchwork.ozlabs.org/comment/3632346/","msgid":"<20260107120608.5ccd2cc7e4227d2e80028bd9@linux-foundation.org>","date":"2026-01-07T20:06:08","subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","submitter":{"id":107,"url":"http://patchwork.ozlabs.org/api/people/107/","name":"Andrew Morton","email":"akpm@linux-foundation.org"},"content":"On Wed, 7 Jan 2026 20:18:12 +1100 Jordan Niethe wrote:\n\n> Today, when creating these device private struct pages, the first step\n> is to use request_free_mem_region() to get a range of physical address\n> space large enough to represent the devices memory. This allocated\n> physical address range is then remapped as device private memory using\n> memremap_pages.\n\nWelcome to Linux MM. That's a heck of an opening salvo ;)\n\n> Needing allocation of physical address space has some problems:\n> \n> 1) There may be insufficient physical address space to represent the\n> device memory. KASLR reducing the physical address space and VM\n> configurations with limited physical address space increase the\n> likelihood of hitting this especially as device memory increases. This\n> has been observed to prevent device private from being initialized. \n> \n> 2) Attempting to add the device private pages to the linear map at\n> addresses beyond the actual physical memory causes issues on\n> architectures like aarch64 - meaning the feature does not work there [0].\n\nCan you better help us understand the seriousness of these problems? \nHow much are our users really hurting from this?\n\n> Seeking opinions on using the mpfns like this or if a new type would be\n> preferred.\n\nWhose opinions? IOW, can you suggest who you'd like to see review this\nwork?\n\n> \n> * NOTE: I will need help in testing the driver changes *\n> \n\nAgain, please name names ;) I'm not afraid to prod.\n\n\nI'm reluctant to add this to mm.git's development/testing branches at\nthis time. Your advice on when you think we're ready for that step\nwould be valuable, thanks.","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux-foundation.org header.i=@linux-foundation.org\n header.a=rsa-sha256 header.s=korg header.b=NLgidEHi;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:21b9:f100::1; helo=lists.ozlabs.org;\n envelope-from=linuxppc-dev+bounces-15391-incoming=patchwork.ozlabs.org@lists.ozlabs.org;\n receiver=patchwork.ozlabs.org)","lists.ozlabs.org;\n arc=none smtp.remote-ip=172.105.4.254","lists.ozlabs.org;\n dmarc=none (p=none dis=none) header.from=linux-foundation.org","lists.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux-foundation.org header.i=@linux-foundation.org\n header.a=rsa-sha256 header.s=korg header.b=NLgidEHi;\n\tdkim-atps=neutral","lists.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=linux-foundation.org\n (client-ip=172.105.4.254; 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lists.ozlabs.org;\n dmarc=none (p=none dis=none) header.from=linux-foundation.org;\n dkim=pass (1024-bit key;\n unprotected) header.d=linux-foundation.org header.i=@linux-foundation.org\n header.a=rsa-sha256 header.s=korg header.b=NLgidEHi; dkim-atps=neutral;\n spf=pass (client-ip=172.105.4.254; helo=tor.source.kernel.org;\n envelope-from=akpm@linux-foundation.org;\n receiver=lists.ozlabs.org) smtp.mailfrom=linux-foundation.org","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=linux-foundation.org;\n\ts=korg; t=1767816369;\n\tbh=9PIBpB6BT7c2Nly9VamIDqbclUvTqGBanLECbpOqsZU=;\n\th=Date:From:To:Cc:Subject:In-Reply-To:References:From;\n\tb=NLgidEHia+ljn45TqKKiaI1PqrlkMihQySUaXwHidlJUJPZNGsTIZWluKWXqqW0JD\n\t pyxhlCbST+uZv3N70zgjUhz9hGOVY0eKuj6ZXXiv5xVYcKWEmySRYVNQZVYzawb7RK\n\t 0/qFXzfy9W/GNVAvifH3407hbK+RS4rtYOs+DkSg=","Date":"Wed, 7 Jan 2026 12:06:08 -0800","From":"Andrew Morton ","To":"Jordan Niethe ","Cc":"linux-mm@kvack.org, balbirs@nvidia.com, matthew.brost@intel.com,\n linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,\n david@redhat.com, ziy@nvidia.com, apopple@nvidia.com,\n lorenzo.stoakes@oracle.com, lyude@redhat.com, dakr@kernel.org,\n airlied@gmail.com, simona@ffwll.ch, rcampbell@nvidia.com,\n mpenttil@redhat.com, jgg@nvidia.com, willy@infradead.org,\n linuxppc-dev@lists.ozlabs.org, intel-xe@lists.freedesktop.org,\n jgg@ziepe.ca, Felix.Kuehling@amd.com","Subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","Message-Id":"<20260107120608.5ccd2cc7e4227d2e80028bd9@linux-foundation.org>","In-Reply-To":"<20260107091823.68974-1-jniethe@nvidia.com>","References":"<20260107091823.68974-1-jniethe@nvidia.com>","X-Mailer":"Sylpheed 3.8.0beta1 (GTK+ 2.24.33; x86_64-pc-linux-gnu)","X-Mailing-List":"linuxppc-dev@lists.ozlabs.org","List-Id":"","List-Help":"","List-Owner":"","List-Post":"","List-Archive":",\n ","List-Subscribe":",\n ,\n ","List-Unsubscribe":"","Precedence":"list","Mime-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","X-Spam-Status":"No, score=-0.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID,\n\tDKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS\n\tautolearn=disabled version=4.0.1 OzLabs 8","X-Spam-Checker-Version":"SpamAssassin 4.0.1 (2024-03-25) on lists.ozlabs.org"}},{"id":3632352,"web_url":"http://patchwork.ozlabs.org/comment/3632352/","msgid":"<02D37B25-E2E4-4E1E-A714-1CF90AC7AA35@nvidia.com>","date":"2026-01-07T20:21:33","subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","submitter":{"id":76947,"url":"http://patchwork.ozlabs.org/api/people/76947/","name":"Zi Yan","email":"ziy@nvidia.com"},"content":"On 7 Jan 2026, at 13:36, Matthew Brost wrote:\n\n> On Wed, Jan 07, 2026 at 08:18:12PM +1100, Jordan Niethe wrote:\n>> Today, when creating these device private struct pages, the first step\n>> is to use request_free_mem_region() to get a range of physical address\n>> space large enough to represent the devices memory. This allocated\n>> physical address range is then remapped as device private memory using\n>> memremap_pages.\n>>\n>> Needing allocation of physical address space has some problems:\n>>\n>> 1) There may be insufficient physical address space to represent the\n>> device memory. KASLR reducing the physical address space and VM\n>> configurations with limited physical address space increase the\n>> likelihood of hitting this especially as device memory increases. This\n>> has been observed to prevent device private from being initialized.\n>>\n>> 2) Attempting to add the device private pages to the linear map at\n>> addresses beyond the actual physical memory causes issues on\n>> architectures like aarch64 - meaning the feature does not work there [0].\n>>\n>> This series changes device private memory so that it does not require\n>> allocation of physical address space and these problems are avoided.\n>> Instead of using the physical address space, we introduce a \"device\n>> private address space\" and allocate from there.\n>>\n>> A consequence of placing the device private pages outside of the\n>> physical address space is that they no longer have a PFN. However, it is\n>> still necessary to be able to look up a corresponding device private\n>> page from a device private PTE entry, which means that we still require\n>> some way to index into this device private address space. Instead of a\n>> PFN, device private pages use an offset into this device private address\n>> space to look up device private struct pages.\n>>\n>> The problem that then needs to be addressed is how to avoid confusing\n>> these device private offsets with PFNs. It is the inherent limited usage\n>> of the device private pages themselves which make this possible. A\n>> device private page is only used for userspace mappings, we do not need\n>> to be concerned with them being used within the mm more broadly. This\n>> means that the only way that the core kernel looks up these pages is via\n>> the page table, where their PTE already indicates if they refer to a\n>> device private page via their swap type, e.g. SWP_DEVICE_WRITE. We can\n>> use this information to determine if the PTE contains a PFN which should\n>> be looked up in the page map, or a device private offset which should be\n>> looked up elsewhere.\n>>\n>> This applies when we are creating PTE entries for device private pages -\n>> because they have their own type there are already must be handled\n>> separately, so it is a small step to convert them to a device private\n>> PFN now too.\n>>\n>> The first part of the series updates callers where device private\n>> offsets might now be encountered to track this extra state.\n>>\n>> The last patch contains the bulk of the work where we change how we\n>> convert between device private pages to device private offsets and then\n>> use a new interface for allocating device private pages without the need\n>> for reserving physical address space.\n>>\n>> By removing the device private pages from the physical address space,\n>> this series also opens up the possibility to moving away from tracking\n>> device private memory using struct pages in the future. This is\n>> desirable as on systems with large amounts of memory these device\n>> private struct pages use a signifiant amount of memory and take a\n>> significant amount of time to initialize.\n>>\n>> *** Changes in v2 ***\n>>\n>> The most significant change in v2 is addressing code paths that are\n>> common between MEMORY_DEVICE_PRIVATE and MEMORY_DEVICE_COHERENT devices.\n>>\n>> This had been overlooked in previous revisions.\n>>\n>> To do this we introduce a migrate_pfn_from_page() helper which will call\n>> device_private_offset_to_page() and set the MIGRATE_PFN_DEVICE_PRIVATE\n>> flag if required.\n>>\n>> In places where we could have a device private offset\n>> (MEMORY_DEVICE_PRIVATE) or a pfn (MEMORY_DEVICE_COHERENT) we update to\n>> use an mpfn to disambiguate. This includes some users in the drivers\n>> and migrate_device_{pfns,range}().\n>>\n>> Seeking opinions on using the mpfns like this or if a new type would be\n>> preferred.\n>>\n>> - mm/migrate_device: Introduce migrate_pfn_from_page() helper\n>> - New to series\n>>\n>> - drm/amdkfd: Use migrate pfns internally\n>> - New to series\n>>\n>> - mm/migrate_device: Make migrate_device_{pfns,range}() take mpfns\n>> - New to series\n>>\n>> - mm/migrate_device: Add migrate PFN flag to track device private pages\n>> - Update for migrate_pfn_from_page()\n>> - Rename to MIGRATE_PFN_DEVICE_PRIVATE\n>> - drm/amd: Check adev->gmc.xgmi.connected_to_cpu\n>> - lib/test_hmm.c: Check chunk->pagemap.type == MEMORY_DEVICE_PRIVATE\n>>\n>> - mm: Add helpers to create migration entries from struct pages\n>> - Add a flags param\n>>\n>> - mm: Add a new swap type for migration entries of device private pages\n>> - Add softleaf_is_migration_device_private_read()\n>>\n>> - mm: Add helpers to create device private entries from struct pages\n>> - Add a flags param\n>>\n>> - mm: Remove device private pages from the physical address space\n>> - Make sure last member of struct dev_pagemap remains DECLARE_FLEX_ARRAY(struct range, ranges);\n>>\n>> Testing:\n>> - selftests/mm/hmm-tests on an amd64 VM\n>>\n>> * NOTE: I will need help in testing the driver changes *\n>>\n>\n> Thanks for the series. For some reason Intel's CI couldn't apply this\n> series to drm-tip to get results [1]. I'll manually apply this and run all\n> our SVM tests and get back you on results + review the changes here. For\n> future reference if you want to use our CI system, the series must apply\n> to drm-tip, feel free to rebase this series and just send to intel-xe\n> list if you want CI results.\n>\n> I was also wondering if Nvidia could help review one our core MM patches\n> [2] which is gating enabling 2M device pages too?\n\nI will take a look. But next time, do you mind Ccing MM maintainers and\nreviewers based on MAINTAINERS file? Otherwise, it is hard for people to\ncheck every email from linux-mm.\n\nThanks.\n\n>\n> Matt\n>\n> [1] https://patchwork.freedesktop.org/series/159738/\n> [2] https://patchwork.freedesktop.org/patch/694775/?series=159119&rev=1\n>\n>> Revisions:\n>> - RFC: https://lore.kernel.org/all/20251128044146.80050-1-jniethe@nvidia.com/\n>> - v1: https://lore.kernel.org/all/20251231043154.42931-1-jniethe@nvidia.com/\n>>\n>> [0] https://lore.kernel.org/lkml/CAMj1kXFZ=4hLL1w6iCV5O5uVoVLHAJbc0rr40j24ObenAjXe9w@mail.gmail.com/\n>>\n>> Jordan Niethe (11):\n>> mm/migrate_device: Introduce migrate_pfn_from_page() helper\n>> drm/amdkfd: Use migrate pfns internally\n>> mm/migrate_device: Make migrate_device_{pfns,range}() take mpfns\n>> mm/migrate_device: Add migrate PFN flag to track device private pages\n>> mm/page_vma_mapped: Add flags to page_vma_mapped_walk::pfn to track\n>> device private pages\n>> mm: Add helpers to create migration entries from struct pages\n>> mm: Add a new swap type for migration entries of device private pages\n>> mm: Add helpers to create device private entries from struct pages\n>> mm/util: Add flag to track device private pages in page snapshots\n>> mm/hmm: Add flag to track device private pages\n>> mm: Remove device private pages from the physical address space\n>>\n>> Documentation/mm/hmm.rst | 11 +-\n>> arch/powerpc/kvm/book3s_hv_uvmem.c | 43 ++---\n>> drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 45 +++---\n>> drivers/gpu/drm/amd/amdkfd/kfd_migrate.h | 2 +-\n>> drivers/gpu/drm/drm_pagemap.c | 11 +-\n>> drivers/gpu/drm/nouveau/nouveau_dmem.c | 45 ++----\n>> drivers/gpu/drm/xe/xe_svm.c | 37 ++---\n>> fs/proc/page.c | 6 +-\n>> include/drm/drm_pagemap.h | 8 +-\n>> include/linux/hmm.h | 7 +-\n>> include/linux/leafops.h | 116 ++++++++++++--\n>> include/linux/memremap.h | 64 +++++++-\n>> include/linux/migrate.h | 23 ++-\n>> include/linux/mm.h | 9 +-\n>> include/linux/rmap.h | 33 +++-\n>> include/linux/swap.h | 8 +-\n>> include/linux/swapops.h | 136 ++++++++++++++++\n>> lib/test_hmm.c | 86 ++++++----\n>> mm/debug.c | 9 +-\n>> mm/hmm.c | 5 +-\n>> mm/huge_memory.c | 43 ++---\n>> mm/hugetlb.c | 15 +-\n>> mm/memory.c | 5 +-\n>> mm/memremap.c | 193 ++++++++++++++++++-----\n>> mm/migrate.c | 6 +-\n>> mm/migrate_device.c | 76 +++++----\n>> mm/mm_init.c | 8 +-\n>> mm/mprotect.c | 10 +-\n>> mm/page_vma_mapped.c | 32 +++-\n>> mm/rmap.c | 59 ++++---\n>> mm/util.c | 8 +-\n>> mm/vmscan.c | 2 +-\n>> 32 files changed, 822 insertions(+), 339 deletions(-)\n>>\n>>\n>> base-commit: f8f9c1f4d0c7a64600e2ca312dec824a0bc2f1da\n>> -- \n>> 2.34.1\n>>\n\n\nBest Regards,\nYan, Zi","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 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dri-devel@lists.freedesktop.org, david@redhat.com, apopple@nvidia.com,\n lorenzo.stoakes@oracle.com, lyude@redhat.com, dakr@kernel.org,\n airlied@gmail.com, simona@ffwll.ch, rcampbell@nvidia.com,\n mpenttil@redhat.com, jgg@nvidia.com, willy@infradead.org,\n linuxppc-dev@lists.ozlabs.org, intel-xe@lists.freedesktop.org, jgg@ziepe.ca,\n Felix.Kuehling@amd.com","Subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","Date":"Wed, 07 Jan 2026 15:21:33 -0500","X-Mailer":"MailMate (2.0r6290)","Message-ID":"<02D37B25-E2E4-4E1E-A714-1CF90AC7AA35@nvidia.com>","In-Reply-To":"","References":"<20260107091823.68974-1-jniethe@nvidia.com>\n ","Content-Type":"text/plain","Content-Transfer-Encoding":"quoted-printable","X-ClientProxiedBy":"BYAPR06CA0021.namprd06.prod.outlook.com\n (2603:10b6:a03:d4::34) To DS7PR12MB9473.namprd12.prod.outlook.com\n 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lists.ozlabs.org"}},{"id":3632365,"web_url":"http://patchwork.ozlabs.org/comment/3632365/","msgid":"<20260107205404.GI293394@nvidia.com>","date":"2026-01-07T20:54:04","subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","submitter":{"id":79424,"url":"http://patchwork.ozlabs.org/api/people/79424/","name":"Jason Gunthorpe","email":"jgg@nvidia.com"},"content":"On Wed, Jan 07, 2026 at 12:06:08PM -0800, Andrew Morton wrote:\n\n> > 2) Attempting to add the device private pages to the linear map at\n> > addresses beyond the actual physical memory causes issues on\n> > architectures like aarch64 - meaning the feature does not work there [0].\n> \n> Can you better help us understand the seriousness of these problems? \n> How much are our users really hurting from this?\n\nWe think it is pretty serious, in the future HW support sense, as it\nmeans real systems being built do not work :)\n\nAlso Willy and others were cheering this work on at LPC. I think the\npossible followup to move DEVICE_PRIVATE from struct page and reduce\nthe memory allocation would be well celebrated.\n\nThe Intel Xe and AMD GPU teams are the two drivers most important to\nbe testing this as they consume the feature.\n\nJason","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=uYn6Zpxp;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:21b9:f100::1; helo=lists.ozlabs.org;\n envelope-from=linuxppc-dev+bounces-15394-incoming=patchwork.ozlabs.org@lists.ozlabs.org;\n receiver=patchwork.ozlabs.org)","lists.ozlabs.org;\n arc=pass smtp.remote-ip=52.101.56.12 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c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=bg/+TeXfpGaelqWXlfi2WyIE54OghyTP7ekZYKuGuvY=;\n b=uYn6ZpxpoQKQAhE1YvSYwKljqRQjhtPvO+X7Vun1OiqPFQgGAJ+dNOajGq3Y1vj513hw86s88jk+Zdnn15g509fk0HWB12imZYhwKq0XSGtcHtLZC08I04O2wKtzwGwurCvSpQmCfW0UK7AvckAy3Fo/2ipBc2kCrtX6xc8zPPoUEv3nRF8RCQpljpihxSPuZ78/pCBb7ynfvnV6Ow4RfDIPCFYHE1+ri5uczquLjgp184cr2Ahwg0YODXmKDEySmJWI/IzpjbGxQ0rJKLmt+5HzDUI6gZnpqluQlEd66gfW1uk7kvWVmZy2iuFumZzyXoBQQTSMfV5h9WUJzf3Qkw==","Date":"Wed, 7 Jan 2026 16:54:04 -0400","From":"Jason Gunthorpe ","To":"Andrew Morton ","Cc":"Jordan Niethe , linux-mm@kvack.org,\n\tbalbirs@nvidia.com, matthew.brost@intel.com,\n\tlinux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,\n\tdavid@redhat.com, ziy@nvidia.com, apopple@nvidia.com,\n\tlorenzo.stoakes@oracle.com, lyude@redhat.com, dakr@kernel.org,\n\tairlied@gmail.com, simona@ffwll.ch, rcampbell@nvidia.com,\n\tmpenttil@redhat.com, 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lists.ozlabs.org"}},{"id":3632367,"web_url":"http://patchwork.ozlabs.org/comment/3632367/","msgid":"","date":"2026-01-07T21:02:25","subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","submitter":{"id":90215,"url":"http://patchwork.ozlabs.org/api/people/90215/","name":"Balbir Singh","email":"balbirs@nvidia.com"},"content":"On 1/8/26 06:54, Jason Gunthorpe wrote:\n> On Wed, Jan 07, 2026 at 12:06:08PM -0800, Andrew Morton wrote:\n> \n>>> 2) Attempting to add the device private pages to the linear map at\n>>> addresses beyond the actual physical memory causes issues on\n>>> architectures like aarch64 - meaning the feature does not work there [0].\n>>\n>> Can you better help us understand the seriousness of these problems? \n>> How much are our users really hurting from this?\n> \n> We think it is pretty serious, in the future HW support sense, as it\n> means real systems being built do not work :)\n> \n> Also Willy and others were cheering this work on at LPC. I think the\n> possible followup to move DEVICE_PRIVATE from struct page and reduce\n> the memory allocation would be well celebrated.\n> \n> The Intel Xe and AMD GPU teams are the two drivers most important to\n> be testing this as they consume the feature.\n> \n\nAnd the ultravisor usage in powerpc as well (book3s_hv_uvmem).\n\nBalbir","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=po79M7gv;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:21b9:f100::1; helo=lists.ozlabs.org;\n envelope-from=linuxppc-dev+bounces-15395-incoming=patchwork.ozlabs.org@lists.ozlabs.org;\n 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space","To":"Jason Gunthorpe ,\n Andrew Morton ","Cc":"Jordan Niethe , linux-mm@kvack.org,\n matthew.brost@intel.com, linux-kernel@vger.kernel.org,\n dri-devel@lists.freedesktop.org, david@redhat.com, ziy@nvidia.com,\n apopple@nvidia.com, lorenzo.stoakes@oracle.com, lyude@redhat.com,\n dakr@kernel.org, airlied@gmail.com, simona@ffwll.ch, rcampbell@nvidia.com,\n mpenttil@redhat.com, willy@infradead.org, linuxppc-dev@lists.ozlabs.org,\n intel-xe@lists.freedesktop.org, Felix.Kuehling@amd.com","References":"<20260107091823.68974-1-jniethe@nvidia.com>\n <20260107120608.5ccd2cc7e4227d2e80028bd9@linux-foundation.org>\n <20260107205404.GI293394@nvidia.com>","Content-Language":"en-US","From":"Balbir Singh ","In-Reply-To":"<20260107205404.GI293394@nvidia.com>","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"7bit","X-ClientProxiedBy":"BYAPR05CA0030.namprd05.prod.outlook.com\n (2603:10b6:a03:c0::43) To PH8PR12MB7277.namprd12.prod.outlook.com\n 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lists.ozlabs.org"}},{"id":3632446,"web_url":"http://patchwork.ozlabs.org/comment/3632446/","msgid":"<71fade9d-be8f-40d1-b580-4fac89a16cc7@nvidia.com>","date":"2026-01-08T01:08:43","subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","submitter":{"id":71484,"url":"http://patchwork.ozlabs.org/api/people/71484/","name":"John Hubbard","email":"jhubbard@nvidia.com"},"content":"On 1/7/26 12:06 PM, Andrew Morton wrote:\n> On Wed, 7 Jan 2026 20:18:12 +1100 Jordan Niethe wrote:\n...\n> Can you better help us understand the seriousness of these problems? \n> How much are our users really hurting from this?\n> \n\nA lot! We have been involved in escalations from various customers\nwho have attempted to enable, say, KASLR and HMM at the same time.\nAnd they ran out of phys address space, forcing them into an awkward\nugly choice of one or the other, often.\n\nThis is a huge pain point and a barrier to HMM adoption.\n\nthanks,","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=Ydec20e3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=112.213.38.117; helo=lists.ozlabs.org;\n envelope-from=linuxppc-dev+bounces-15397-incoming=patchwork.ozlabs.org@lists.ozlabs.org;\n receiver=patchwork.ozlabs.org)","lists.ozlabs.org;\n arc=pass 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lists.ozlabs.org"}},{"id":3632450,"web_url":"http://patchwork.ozlabs.org/comment/3632450/","msgid":"","date":"2026-01-08T01:29:21","subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","submitter":{"id":81117,"url":"http://patchwork.ozlabs.org/api/people/81117/","name":"Alistair Popple","email":"apopple@nvidia.com"},"content":"On 2026-01-08 at 08:02 +1100, Balbir Singh wrote...\n> On 1/8/26 06:54, Jason Gunthorpe wrote:\n> > On Wed, Jan 07, 2026 at 12:06:08PM -0800, Andrew Morton wrote:\n> > \n> >>> 2) Attempting to add the device private pages to the linear map at\n> >>> addresses beyond the actual physical memory causes issues on\n> >>> architectures like aarch64 - meaning the feature does not work there [0].\n> >>\n> >> Can you better help us understand the seriousness of these problems? \n> >> How much are our users really hurting from this?\n> > \n> > We think it is pretty serious, in the future HW support sense, as it\n> > means real systems being built do not work :)\n\nThere's actually existing HW that could benefit from this support - after all\nthere is nothing stopping someone plugging a Intel/AMD/NVIDIA GPU into an ARM\nmachine today :-)\n\nSo it would be nice if we could support this feature there as it results in\nreally sub-optimal performance compared with x86 when using the SVM (shared\nvirtual memory) feature because data has to be remote mapped (ie. accessed via\nPCIe link) rather than migrated to local GPU video memory.\n\nHaving the kernel steal physical address space has also caused problems on\nx86 - we have encountered virtualised environments which depending on specific\nfirmware/BIOS don't have enough free physical address space to support device\nprivate pages and hence migration of memory to the GPU device, again leading to\nsub-optmial performance.\n\n> > Also Willy and others were cheering this work on at LPC. I think the\n> > possible followup to move DEVICE_PRIVATE from struct page and reduce\n> > the memory allocation would be well celebrated.\n\nFor reference the recording of my LPC presentation covering both this series and\nthe above is here - https://www.youtube.com/watch?v=CFe_c8-tEuM\n\nThe hope is that in addition to enabling support for this more broadly across\nother platforms/architectures that it will also enable further clean-ups to\nreduce memory allocation overhead (I almost convinced myself we wouldn't need a\nstruct at all ... almost)\n\n> > The Intel Xe and AMD GPU teams are the two drivers most important to\n> > be testing this as they consume the feature.\n> > \n> \n> And the ultravisor usage in powerpc as well (book3s_hv_uvmem).\n\nAs does Nouveau (which I've tested). But I agree AMD GPU and Intel Xe are the\nmost important drivers here. I would be surprised if anyone was actually using\nthe powerpc ultravisor, and I don't have access to a setup for this, so unless\nsome PPC folk can offer to help I wouldn't like to see testing there hold up\nthe series.\n\nEspecially as I believe most of the driver side changes are relatively straight\nforward.\n\n - Alistair\n\n> Balbir","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=XFPiHdNn;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=112.213.38.117; helo=lists.ozlabs.org;\n envelope-from=linuxppc-dev+bounces-15398-incoming=patchwork.ozlabs.org@lists.ozlabs.org;\n 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,\n Jordan Niethe , linux-mm@kvack.org,\n\tmatthew.brost@intel.com, linux-kernel@vger.kernel.org,\n dri-devel@lists.freedesktop.org,\n\tdavid@redhat.com, ziy@nvidia.com, lorenzo.stoakes@oracle.com,\n lyude@redhat.com,\n\tdakr@kernel.org, airlied@gmail.com, simona@ffwll.ch, rcampbell@nvidia.com,\n\tmpenttil@redhat.com, willy@infradead.org, linuxppc-dev@lists.ozlabs.org,\n\tintel-xe@lists.freedesktop.org, Felix.Kuehling@amd.com","Subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","Message-ID":"","References":"<20260107091823.68974-1-jniethe@nvidia.com>\n <20260107120608.5ccd2cc7e4227d2e80028bd9@linux-foundation.org>\n <20260107205404.GI293394@nvidia.com>\n ","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","X-ClientProxiedBy":"SY5P282CA0125.AUSP282.PROD.OUTLOOK.COM\n (2603:10c6:10:209::14) To DS0PR12MB7726.namprd12.prod.outlook.com\n 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lists.ozlabs.org"}},{"id":3632455,"web_url":"http://patchwork.ozlabs.org/comment/3632455/","msgid":"<3qduomzahrrn2s35xxfjem5nud77qhshr4vmg4kwmizyn3twp4@rqoinq7e4yqr>","date":"2026-01-08T01:49:05","subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","submitter":{"id":81117,"url":"http://patchwork.ozlabs.org/api/people/81117/","name":"Alistair Popple","email":"apopple@nvidia.com"},"content":"On 2026-01-08 at 07:06 +1100, Andrew Morton wrote...\n> On Wed, 7 Jan 2026 20:18:12 +1100 Jordan Niethe wrote:\n> \n> > Today, when creating these device private struct pages, the first step\n> > is to use request_free_mem_region() to get a range of physical address\n> > space large enough to represent the devices memory. This allocated\n> > physical address range is then remapped as device private memory using\n> > memremap_pages.\n> \n> Welcome to Linux MM. That's a heck of an opening salvo ;)\n> \n> > Needing allocation of physical address space has some problems:\n> > \n> > 1) There may be insufficient physical address space to represent the\n> > device memory. KASLR reducing the physical address space and VM\n> > configurations with limited physical address space increase the\n> > likelihood of hitting this especially as device memory increases. This\n> > has been observed to prevent device private from being initialized. \n> > \n> > 2) Attempting to add the device private pages to the linear map at\n> > addresses beyond the actual physical memory causes issues on\n> > architectures like aarch64 - meaning the feature does not work there [0].\n> \n> Can you better help us understand the seriousness of these problems? \n> How much are our users really hurting from this?\n\nHopefully the rest of the thread helps address this.\n\n> > Seeking opinions on using the mpfns like this or if a new type would be\n> > preferred.\n> \n> Whose opinions? IOW, can you suggest who you'd like to see review this\n> work?\n\nI was going to see if I could find Lorenzo on IRC as I think it would be good to\nget his opinion on the softleaf changes. And probably Felix's (and my) opinion\nfor the mpfn changes (I don't think Intel currently uses DEVICE_COHERENT which\nthis bit has the biggest impact on).\n\n> > \n> > * NOTE: I will need help in testing the driver changes *\n> > \n> \n> Again, please name names ;) I'm not afraid to prod.\n\nAs noted in the other thread Intel Xe and AMD GPU are the biggest. Matthew has\nalready offered to help test Intel (thanks!) and Felix saw the v1 posting so\nhoping he can help with testing there.\n\n> I'm reluctant to add this to mm.git's development/testing branches at\n> this time. Your advice on when you think we're ready for that step\n> would be valuable, thanks.\n\nWill leave the readiness call to Jordan, but we were hoping to get\nthis in for the v6.20 merge window if at all possible. I realise\nwe're probably running late given we generally like to let stuff\nsettle in development/testing branches for a while prior to the\nmerge window, but it did have an early round of review last year\n(https://lore.kernel.org/linux-mm/20251128044146.80050-1-jniethe@nvidia.com/)\nand I reviewed it internally and it looked very reasonable.\n\nI will take a look at this latest version later today.\n\n - Alistair","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=VTZKPfns;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:21b9:f100::1; helo=lists.ozlabs.org;\n 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linux-mm@kvack.org,\n\tbalbirs@nvidia.com, matthew.brost@intel.com, linux-kernel@vger.kernel.org,\n\tdri-devel@lists.freedesktop.org, david@redhat.com, ziy@nvidia.com,\n lorenzo.stoakes@oracle.com,\n\tlyude@redhat.com, dakr@kernel.org, airlied@gmail.com, simona@ffwll.ch,\n\trcampbell@nvidia.com, mpenttil@redhat.com, jgg@nvidia.com,\n willy@infradead.org,\n\tlinuxppc-dev@lists.ozlabs.org, intel-xe@lists.freedesktop.org, jgg@ziepe.ca,\n\tFelix.Kuehling@amd.com","Subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","Message-ID":"<3qduomzahrrn2s35xxfjem5nud77qhshr4vmg4kwmizyn3twp4@rqoinq7e4yqr>","References":"<20260107091823.68974-1-jniethe@nvidia.com>\n <20260107120608.5ccd2cc7e4227d2e80028bd9@linux-foundation.org>","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20260107120608.5ccd2cc7e4227d2e80028bd9@linux-foundation.org>","X-ClientProxiedBy":"SY5P282CA0006.AUSP282.PROD.OUTLOOK.COM\n (2603:10c6:10:208::11) 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lists.ozlabs.org"}},{"id":3632461,"web_url":"http://patchwork.ozlabs.org/comment/3632461/","msgid":"<3586d8f1-a25f-4087-a987-162ccd97c25f@nvidia.com>","date":"2026-01-08T02:25:48","subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","submitter":{"id":92354,"url":"http://patchwork.ozlabs.org/api/people/92354/","name":"Jordan Niethe","email":"jniethe@nvidia.com"},"content":"Hi,\n\nOn 8/1/26 05:36, Matthew Brost wrote:\n> \n> Thanks for the series. For some reason Intel's CI couldn't apply this\n> series to drm-tip to get results [1]. I'll manually apply this and run all\n> our SVM tests and get back you on results + review the changes here. For\n> future reference if you want to use our CI system, the series must apply\n> to drm-tip, feel free to rebase this series and just send to intel-xe\n> list if you want CI \n\nThanks, I'll rebase on drm-tip and send to the intel-xe list.\n\nJordan.\n\n> \n> I was also wondering if Nvidia could help review one our core MM patches\n> [2] which is gating enabling 2M device pages too?\n> \n> Matt\n> \n> [1] https://patchwork.freedesktop.org/series/159738/\n> [2] https://patchwork.freedesktop.org/patch/694775/?series=159119&rev=1","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=mNOiaADv;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) 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device private pages from physical\n address space","To":"Matthew Brost ","Cc":"linux-mm@kvack.org, balbirs@nvidia.com, akpm@linux-foundation.org,\n linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,\n david@redhat.com, ziy@nvidia.com, apopple@nvidia.com,\n lorenzo.stoakes@oracle.com, lyude@redhat.com, dakr@kernel.org,\n airlied@gmail.com, simona@ffwll.ch, rcampbell@nvidia.com,\n mpenttil@redhat.com, jgg@nvidia.com, willy@infradead.org,\n linuxppc-dev@lists.ozlabs.org, intel-xe@lists.freedesktop.org, jgg@ziepe.ca,\n Felix.Kuehling@amd.com","References":"<20260107091823.68974-1-jniethe@nvidia.com>\n ","Content-Language":"en-US","From":"Jordan Niethe ","In-Reply-To":"","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","X-ClientProxiedBy":"BYAPR11CA0055.namprd11.prod.outlook.com\n (2603:10b6:a03:80::32) To DM4PR12MB9072.namprd12.prod.outlook.com\n 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lists.ozlabs.org"}},{"id":3632465,"web_url":"http://patchwork.ozlabs.org/comment/3632465/","msgid":"","date":"2026-01-08T02:55:39","subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","submitter":{"id":92354,"url":"http://patchwork.ozlabs.org/api/people/92354/","name":"Jordan Niethe","email":"jniethe@nvidia.com"},"content":"Hi,\n\nOn 8/1/26 12:49, Alistair Popple wrote:\n> On 2026-01-08 at 07:06 +1100, Andrew Morton wrote...\n>> On Wed, 7 Jan 2026 20:18:12 +1100 Jordan Niethe wrote:\n>>\n>>> Today, when creating these device private struct pages, the first step\n>>> is to use request_free_mem_region() to get a range of physical address\n>>> space large enough to represent the devices memory. This allocated\n>>> physical address range is then remapped as device private memory using\n>>> memremap_pages.\n>>\n>> Welcome to Linux MM. That's a heck of an opening salvo ;)\n>>\n>>> Needing allocation of physical address space has some problems:\n>>>\n>>> 1) There may be insufficient physical address space to represent the\n>>> device memory. KASLR reducing the physical address space and VM\n>>> configurations with limited physical address space increase the\n>>> likelihood of hitting this especially as device memory increases. This\n>>> has been observed to prevent device private from being initialized.\n>>>\n>>> 2) Attempting to add the device private pages to the linear map at\n>>> addresses beyond the actual physical memory causes issues on\n>>> architectures like aarch64 - meaning the feature does not work there [0].\n>>\n>> Can you better help us understand the seriousness of these problems?\n>> How much are our users really hurting from this?\n> \n> Hopefully the rest of the thread helps address this.\n> \n>>> Seeking opinions on using the mpfns like this or if a new type would be\n>>> preferred.\n>>\n>> Whose opinions? IOW, can you suggest who you'd like to see review this\n>> work?\n> \n> I was going to see if I could find Lorenzo on IRC as I think it would be good to\n> get his opinion on the softleaf changes. And probably Felix's (and my) opinion\n> for the mpfn changes (I don't think Intel currently uses DEVICE_COHERENT which\n> this bit has the biggest impact on).\n\nIt also effects intel's driver because the mpfn changes also touch\nmigrate_device_pfns() which gets used there.\n\nSo also looking for Matthew's thoughts here as well as Felix's.\n\n> \n>>>\n>>> * NOTE: I will need help in testing the driver changes *\n>>>\n>>\n>> Again, please name names ;) I'm not afraid to prod.\n> \n> As noted in the other thread Intel Xe and AMD GPU are the biggest. Matthew has\n> already offered to help test Intel (thanks!) and Felix saw the v1 posting so\n> hoping he can help with testing there.\n\nYes, I should also be able to get run this through the intel-xe CI.\nThe other area that needs testing is the powerpc ultravisor.\n(+cc) Madhavan Srinivasan - are you able to help here?\n\n> \n>> I'm reluctant to add this to mm.git's development/testing branches at\n>> this time. Your advice on when you think we're ready for that step\n>> would be valuable, thanks.\n> \n> Will leave the readiness call to Jordan, but we were hoping to get\n> this in for the v6.20 merge window if at all possible. I realise\n> we're probably running late given we generally like to let stuff\n> settle in development/testing branches for a while prior to the\n> merge window, but it did have an early round of review last year\n> (https://lore.kernel.org/linux-mm/20251128044146.80050-1-jniethe@nvidia.com/)\n> and I reviewed it internally and it looked very reasonable.\n\nMatt has kindly said that he is reviewing the patches so will wait for \nhis feedback.\nI'd also like to get the results from the intel-xe CI first.\n\nAndrew, I'll advise on including in mm.git after these steps - but I don't\nexpect any major issues at this stage. The changes have been solid with the\nhmm selftests and with updating our out of tree driver to use the new\ninterface.\n\n\nThanks,\nJordan.\n\n> \n> I will take a look at this latest version later today.\n> \n> - Alistair","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=jP1ozXG3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=112.213.38.117; helo=lists.ozlabs.org;\n envelope-from=linuxppc-dev+bounces-15401-incoming=patchwork.ozlabs.org@lists.ozlabs.org;\n receiver=patchwork.ozlabs.org)","lists.ozlabs.org;\n arc=pass smtp.remote-ip=52.101.193.53 arc.chain=microsoft.com","lists.ozlabs.org;\n dmarc=pass (p=reject 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airlied@gmail.com, simona@ffwll.ch,\n rcampbell@nvidia.com, mpenttil@redhat.com, jgg@nvidia.com,\n willy@infradead.org, linuxppc-dev@lists.ozlabs.org,\n intel-xe@lists.freedesktop.org, jgg@ziepe.ca, Felix.Kuehling@amd.com,\n maddy@linux.ibm.com","References":"<20260107091823.68974-1-jniethe@nvidia.com>\n <20260107120608.5ccd2cc7e4227d2e80028bd9@linux-foundation.org>\n <3qduomzahrrn2s35xxfjem5nud77qhshr4vmg4kwmizyn3twp4@rqoinq7e4yqr>","Content-Language":"en-US","From":"Jordan Niethe ","In-Reply-To":"<3qduomzahrrn2s35xxfjem5nud77qhshr4vmg4kwmizyn3twp4@rqoinq7e4yqr>","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","X-ClientProxiedBy":"SJ0PR03CA0363.namprd03.prod.outlook.com\n (2603:10b6:a03:3a1::8) To DM4PR12MB9072.namprd12.prod.outlook.com\n (2603:10b6:8:be::6)","X-Mailing-List":"linuxppc-dev@lists.ozlabs.org","List-Id":"","List-Help":"","List-Owner":"","List-Post":"","List-Archive":",\n ","List-Subscribe":",\n ,\n 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lists.ozlabs.org"}},{"id":3632499,"web_url":"http://patchwork.ozlabs.org/comment/3632499/","msgid":"<6a911224-05e5-45ee-8008-e36ef35cbc7b@nvidia.com>","date":"2026-01-08T05:42:34","subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","submitter":{"id":92354,"url":"http://patchwork.ozlabs.org/api/people/92354/","name":"Jordan Niethe","email":"jniethe@nvidia.com"},"content":"Hi,\n\nOn 8/1/26 13:25, Jordan Niethe wrote:\n> Hi,\n> \n> On 8/1/26 05:36, Matthew Brost wrote:\n>>\n>> Thanks for the series. For some reason Intel's CI couldn't apply this\n>> series to drm-tip to get results [1]. I'll manually apply this and run \n>> all\n>> our SVM tests and get back you on results + review the changes here. For\n>> future reference if you want to use our CI system, the series must apply\n>> to drm-tip, feel free to rebase this series and just send to intel-xe\n>> list if you want CI \n> \n> Thanks, I'll rebase on drm-tip and send to the intel-xe list.\n\nFor reference the rebase on drm-tip on the intel-xe list:\n\nhttps://patchwork.freedesktop.org/series/159738/\n\nWill watch the CI results.\n\nThanks,\nJordan.\n\n> \n> Jordan.\n> \n>>\n>> I was also wondering if Nvidia could help review one our core MM patches\n>> [2] which is gating enabling 2M device pages too?\n>>\n>> Matt\n>>\n>> [1] https://patchwork.freedesktop.org/series/159738/\n>> [2] https://patchwork.freedesktop.org/patch/694775/?series=159119&rev=1\n> \n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) 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lists.ozlabs.org"}},{"id":3633227,"web_url":"http://patchwork.ozlabs.org/comment/3633227/","msgid":"","date":"2026-01-09T00:01:13","subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","submitter":{"id":92354,"url":"http://patchwork.ozlabs.org/api/people/92354/","name":"Jordan Niethe","email":"jniethe@nvidia.com"},"content":"Hi,\n\nOn 8/1/26 16:42, Jordan Niethe wrote:\n> Hi,\n> \n> On 8/1/26 13:25, Jordan Niethe wrote:\n>> Hi,\n>>\n>> On 8/1/26 05:36, Matthew Brost wrote:\n>>>\n>>> Thanks for the series. For some reason Intel's CI couldn't apply this\n>>> series to drm-tip to get results [1]. I'll manually apply this and \n>>> run all\n>>> our SVM tests and get back you on results + review the changes here. For\n>>> future reference if you want to use our CI system, the series must apply\n>>> to drm-tip, feel free to rebase this series and just send to intel-xe\n>>> list if you want CI \n>>\n>> Thanks, I'll rebase on drm-tip and send to the intel-xe list.\n> \n> For reference the rebase on drm-tip on the intel-xe list:\n> \n> https://patchwork.freedesktop.org/series/159738/\n> \n> Will watch the CI results.\n\nThe series causes some failures in the intel-xe tests:\nhttps://patchwork.freedesktop.org/series/159738/#rev4\n\nWorking through the failures now.\n\nThanks,\nJordan.\n\n> \n> Thanks,\n> Jordan.\n> \n>>\n>> Jordan.\n>>\n>>>\n>>> I was also wondering if Nvidia could help review one our core MM patches\n>>> [2] which is gating enabling 2M device pages too?\n>>>\n>>> Matt\n>>>\n>>> [1] https://patchwork.freedesktop.org/series/159738/\n>>> [2] https://patchwork.freedesktop.org/patch/694775/?series=159119&rev=1\n>>\n>>\n>","headers":{"Return-Path":"\n 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lists.ozlabs.org"}},{"id":3633234,"web_url":"http://patchwork.ozlabs.org/comment/3633234/","msgid":"","date":"2026-01-09T00:31:40","subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","submitter":{"id":91751,"url":"http://patchwork.ozlabs.org/api/people/91751/","name":"Matthew Brost","email":"matthew.brost@intel.com"},"content":"On Fri, Jan 09, 2026 at 11:01:13AM +1100, Jordan Niethe wrote:\n> Hi,\n> \n> On 8/1/26 16:42, Jordan Niethe wrote:\n> > Hi,\n> > \n> > On 8/1/26 13:25, Jordan Niethe wrote:\n> > > Hi,\n> > > \n> > > On 8/1/26 05:36, Matthew Brost wrote:\n> > > > \n> > > > Thanks for the series. For some reason Intel's CI couldn't apply this\n> > > > series to drm-tip to get results [1]. I'll manually apply this\n> > > > and run all\n> > > > our SVM tests and get back you on results + review the changes here. For\n> > > > future reference if you want to use our CI system, the series must apply\n> > > > to drm-tip, feel free to rebase this series and just send to intel-xe\n> > > > list if you want CI\n> > > \n> > > Thanks, I'll rebase on drm-tip and send to the intel-xe list.\n> > \n> > For reference the rebase on drm-tip on the intel-xe list:\n> > \n> > https://patchwork.freedesktop.org/series/159738/\n> > \n> > Will watch the CI results.\n> \n> The series causes some failures in the intel-xe tests:\n> https://patchwork.freedesktop.org/series/159738/#rev4\n> \n> Working through the failures now.\n> \n\nYea, I saw the failures. I haven't had time look at the patches on my\nend quite yet. Scrabling to get a few things in 6.20/7.0 PR, so I may\nnot have bandwidth to look in depth until mid next week but digging is\non my TODO list.\n\nMatt \n\n> Thanks,\n> Jordan.\n> \n> > \n> > Thanks,\n> > Jordan.\n> > \n> > > \n> > > Jordan.\n> > > \n> > > > \n> > > > I was also wondering if Nvidia could help review one our core MM patches\n> > > > [2] which is gating enabling 2M device pages too?\n> > > > \n> > > > Matt\n> > > > \n> > > > [1] https://patchwork.freedesktop.org/series/159738/\n> > > > [2] https://patchwork.freedesktop.org/patch/694775/?series=159119&rev=1\n> > > \n> > > \n> > \n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel 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lists.ozlabs.org"}},{"id":3633246,"web_url":"http://patchwork.ozlabs.org/comment/3633246/","msgid":"","date":"2026-01-09T01:27:50","subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","submitter":{"id":92354,"url":"http://patchwork.ozlabs.org/api/people/92354/","name":"Jordan Niethe","email":"jniethe@nvidia.com"},"content":"Hi\nOn 9/1/26 11:31, Matthew Brost wrote:\n> On Fri, Jan 09, 2026 at 11:01:13AM +1100, Jordan Niethe wrote:\n>> Hi,\n>>\n>> On 8/1/26 16:42, Jordan Niethe wrote:\n>>> Hi,\n>>>\n>>> On 8/1/26 13:25, Jordan Niethe wrote:\n>>>> Hi,\n>>>>\n>>>> On 8/1/26 05:36, Matthew Brost wrote:\n>>>>>\n>>>>> Thanks for the series. For some reason Intel's CI couldn't apply this\n>>>>> series to drm-tip to get results [1]. I'll manually apply this\n>>>>> and run all\n>>>>> our SVM tests and get back you on results + review the changes here. For\n>>>>> future reference if you want to use our CI system, the series must apply\n>>>>> to drm-tip, feel free to rebase this series and just send to intel-xe\n>>>>> list if you want CI\n>>>>\n>>>> Thanks, I'll rebase on drm-tip and send to the intel-xe list.\n>>>\n>>> For reference the rebase on drm-tip on the intel-xe list:\n>>>\n>>> https://patchwork.freedesktop.org/series/159738/\n>>>\n>>> Will watch the CI results.\n>>\n>> The series causes some failures in the intel-xe tests:\n>> https://patchwork.freedesktop.org/series/159738/#rev4\n>>\n>> Working through the failures now.\n>>\n> \n> Yea, I saw the failures. I haven't had time look at the patches on my\n> end quite yet. Scrabling to get a few things in 6.20/7.0 PR, so I may\n> not have bandwidth to look in depth until mid next week but digging is\n> on my TODO list.\n\nSure, that's completely fine. The failures seem pretty directly related \nto the\nseries so I think I'll be able to make good progress.\n\nFor example \nhttps://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159738v4/bat-bmg-2/igt@xe_evict@evict-beng-small.html\n\nIt looks like I missed that xe_pagemap_destroy_work() needs to be updated to\nremove the call to devm_release_mem_region() now we are no longer \nreserving a mem\nregion. \n \n \n\n\nThanks,\nJordan.\n\n> \n> Matt\n> \n>> Thanks,\n>> Jordan.\n>>\n>>>\n>>> Thanks,\n>>> Jordan.\n>>>\n>>>>\n>>>> Jordan.\n>>>>\n>>>>>\n>>>>> I was also wondering if Nvidia could help review one our core MM patches\n>>>>> [2] which is gating enabling 2M device pages too?\n>>>>>\n>>>>> Matt\n>>>>>\n>>>>> [1] https://patchwork.freedesktop.org/series/159738/\n>>>>> [2] https://patchwork.freedesktop.org/patch/694775/?series=159119&rev=1\n>>>>\n>>>>\n>>>\n>>","headers":{"Return-Path":"\n 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dakr@kernel.org,\n airlied@gmail.com, simona@ffwll.ch, rcampbell@nvidia.com,\n mpenttil@redhat.com, jgg@nvidia.com, willy@infradead.org,\n linuxppc-dev@lists.ozlabs.org, intel-xe@lists.freedesktop.org, jgg@ziepe.ca,\n Felix.Kuehling@amd.com","References":"<20260107091823.68974-1-jniethe@nvidia.com>\n \n <3586d8f1-a25f-4087-a987-162ccd97c25f@nvidia.com>\n <6a911224-05e5-45ee-8008-e36ef35cbc7b@nvidia.com>\n \n ","Content-Language":"en-US","From":"Jordan Niethe ","In-Reply-To":"","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","X-ClientProxiedBy":"BYAPR21CA0019.namprd21.prod.outlook.com\n (2603:10b6:a03:114::29) To DM4PR12MB9072.namprd12.prod.outlook.com\n (2603:10b6:8:be::6)","X-Mailing-List":"linuxppc-dev@lists.ozlabs.org","List-Id":"","List-Help":"","List-Owner":"","List-Post":"","List-Archive":",\n ","List-Subscribe":",\n ,\n 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lists.ozlabs.org"}},{"id":3633961,"web_url":"http://patchwork.ozlabs.org/comment/3633961/","msgid":"","date":"2026-01-09T06:22:37","subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","submitter":{"id":91751,"url":"http://patchwork.ozlabs.org/api/people/91751/","name":"Matthew Brost","email":"matthew.brost@intel.com"},"content":"On Fri, Jan 09, 2026 at 12:27:50PM +1100, Jordan Niethe wrote:\n> Hi\n> On 9/1/26 11:31, Matthew Brost wrote:\n> > On Fri, Jan 09, 2026 at 11:01:13AM +1100, Jordan Niethe wrote:\n> > > Hi,\n> > > \n> > > On 8/1/26 16:42, Jordan Niethe wrote:\n> > > > Hi,\n> > > > \n> > > > On 8/1/26 13:25, Jordan Niethe wrote:\n> > > > > Hi,\n> > > > > \n> > > > > On 8/1/26 05:36, Matthew Brost wrote:\n> > > > > > \n> > > > > > Thanks for the series. For some reason Intel's CI couldn't apply this\n> > > > > > series to drm-tip to get results [1]. I'll manually apply this\n> > > > > > and run all\n> > > > > > our SVM tests and get back you on results + review the changes here. For\n> > > > > > future reference if you want to use our CI system, the series must apply\n> > > > > > to drm-tip, feel free to rebase this series and just send to intel-xe\n> > > > > > list if you want CI\n> > > > > \n> > > > > Thanks, I'll rebase on drm-tip and send to the intel-xe list.\n> > > > \n> > > > For reference the rebase on drm-tip on the intel-xe list:\n> > > > \n> > > > https://patchwork.freedesktop.org/series/159738/\n> > > > \n> > > > Will watch the CI results.\n> > > \n> > > The series causes some failures in the intel-xe tests:\n> > > https://patchwork.freedesktop.org/series/159738/#rev4\n> > > \n> > > Working through the failures now.\n> > > \n> > \n> > Yea, I saw the failures. I haven't had time look at the patches on my\n> > end quite yet. Scrabling to get a few things in 6.20/7.0 PR, so I may\n> > not have bandwidth to look in depth until mid next week but digging is\n> > on my TODO list.\n> \n> Sure, that's completely fine. The failures seem pretty directly related to\n> the\n> series so I think I'll be able to make good progress.\n> \n> For example https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159738v4/bat-bmg-2/igt@xe_evict@evict-beng-small.html\n> \n> It looks like I missed that xe_pagemap_destroy_work() needs to be updated to\n> remove the call to devm_release_mem_region() now we are no longer reserving\n> a mem\n> region.\n\n+1\n\nSo this is the one I’d be most concerned about [1].\nxe_exec_system_allocator is our SVM test, which does almost all the\nridiculous things possible in user space to stress SVM. It’s blowing up\nin the core MM—but the source of the bug could be anywhere (e.g., Xe\nSVM, GPU SVM, migrate device layer, or core MM). I’ll try to help when I\nhave bandwidth.\n\nMatt\n\n[1] https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159738v4/shard-bmg-9/igt@xe_exec_system_allocator@threads-many-large-execqueues-free-nomemset.html\n\n> \n> \n> Thanks,\n> Jordan.\n> \n> > \n> > Matt\n> > \n> > > Thanks,\n> > > Jordan.\n> > > \n> > > > \n> > > > Thanks,\n> > > > Jordan.\n> > > > \n> > > > > \n> > > > > Jordan.\n> > > > > \n> > > > > > \n> > > > > > I was also wondering if Nvidia could help review one our core MM patches\n> > > > > > [2] which is gating enabling 2M device pages too?\n> > > > > > \n> > > > > > Matt\n> > > > > > \n> > > > > > [1] https://patchwork.freedesktop.org/series/159738/\n> > > > > > [2] https://patchwork.freedesktop.org/patch/694775/?series=159119&rev=1\n> > > > > \n> > > > > \n> > > > \n> > > \n>","headers":{"Return-Path":"\n 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lists.ozlabs.org"}},{"id":3635705,"web_url":"http://patchwork.ozlabs.org/comment/3635705/","msgid":"","date":"2026-01-14T05:41:46","subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","submitter":{"id":92354,"url":"http://patchwork.ozlabs.org/api/people/92354/","name":"Jordan Niethe","email":"jniethe@nvidia.com"},"content":"Hi,\n\nOn 9/1/26 17:22, Matthew Brost wrote:\n> On Fri, Jan 09, 2026 at 12:27:50PM +1100, Jordan Niethe wrote:\n>> Hi\n>> On 9/1/26 11:31, Matthew Brost wrote:\n>>> On Fri, Jan 09, 2026 at 11:01:13AM +1100, Jordan Niethe wrote:\n>>>> Hi,\n>>>>\n>>>> On 8/1/26 16:42, Jordan Niethe wrote:\n>>>>> Hi,\n>>>>>\n>>>>> On 8/1/26 13:25, Jordan Niethe wrote:\n>>>>>> Hi,\n>>>>>>\n>>>>>> On 8/1/26 05:36, Matthew Brost wrote:\n>>>>>>>\n>>>>>>> Thanks for the series. For some reason Intel's CI couldn't apply this\n>>>>>>> series to drm-tip to get results [1]. I'll manually apply this\n>>>>>>> and run all\n>>>>>>> our SVM tests and get back you on results + review the changes here. For\n>>>>>>> future reference if you want to use our CI system, the series must apply\n>>>>>>> to drm-tip, feel free to rebase this series and just send to intel-xe\n>>>>>>> list if you want CI\n>>>>>>\n>>>>>> Thanks, I'll rebase on drm-tip and send to the intel-xe list.\n>>>>>\n>>>>> For reference the rebase on drm-tip on the intel-xe list:\n>>>>>\n>>>>> https://patchwork.freedesktop.org/series/159738/\n>>>>>\n>>>>> Will watch the CI results.\n>>>>\n>>>> The series causes some failures in the intel-xe tests:\n>>>> https://patchwork.freedesktop.org/series/159738/#rev4\n>>>>\n>>>> Working through the failures now.\n>>>>\n>>>\n>>> Yea, I saw the failures. I haven't had time look at the patches on my\n>>> end quite yet. Scrabling to get a few things in 6.20/7.0 PR, so I may\n>>> not have bandwidth to look in depth until mid next week but digging is\n>>> on my TODO list.\n>>\n>> Sure, that's completely fine. The failures seem pretty directly related to\n>> the\n>> series so I think I'll be able to make good progress.\n>>\n>> For example https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159738v4/bat-bmg-2/igt@xe_evict@evict-beng-small.html\n>>\n>> It looks like I missed that xe_pagemap_destroy_work() needs to be updated to\n>> remove the call to devm_release_mem_region() now we are no longer reserving\n>> a mem\n>> region.\n> \n> +1\n> \n> So this is the one I’d be most concerned about [1].\n> xe_exec_system_allocator is our SVM test, which does almost all the\n> ridiculous things possible in user space to stress SVM. It’s blowing up\n> in the core MM—but the source of the bug could be anywhere (e.g., Xe\n> SVM, GPU SVM, migrate device layer, or core MM). I’ll try to help when I\n> have bandwidth.\n> \n> Matt\n> \n> [1] https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159738v4/shard-bmg-9/igt@xe_exec_system_allocator@threads-many-large-execqueues-free-nomemset.html\n\nA similar fault in lruvec_stat_mod_folio can be repro'd if\nmemremap_device_private_pagemap() is called with NUMA_NO_NODE instead of \n(say)\nnuma_node_id() for the nid parameter.\n\nThe xe_svm driver uses devm_memremap_device_private_pagemap() which uses\ndev_to_node() for the nid parameter. Suspect this is causing something \nsimilar\nto happen.\n\nWhen memremap_pages() calls pagemap_range() we have the following logic:\n\n if (nid < 0)\n nid = numa_mem_id();\n\nI think we might need to add this to memremap_device_private_pagemap() \nto handle\nthe NUMA_NO_NODE case. Still confirming.\n\nThanks,\nJordan.\n\n> \n>>\n>>\n>> Thanks,\n>> Jordan.\n>>\n>>>\n>>> Matt\n>>>\n>>>> Thanks,\n>>>> Jordan.\n>>>>\n>>>>>\n>>>>> Thanks,\n>>>>> Jordan.\n>>>>>\n>>>>>>\n>>>>>> Jordan.\n>>>>>>\n>>>>>>>\n>>>>>>> I was also wondering if Nvidia could help review one our core MM patches\n>>>>>>> [2] which is gating enabling 2M device pages too?\n>>>>>>>\n>>>>>>> Matt\n>>>>>>>\n>>>>>>> [1] https://patchwork.freedesktop.org/series/159738/\n>>>>>>> [2] https://patchwork.freedesktop.org/patch/694775/?series=159119&rev=1\n>>>>>>\n>>>>>>\n>>>>>\n>>>>\n>>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=ce0DkyTl;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF 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space","To":"Matthew Brost ","Cc":"linux-mm@kvack.org, balbirs@nvidia.com, akpm@linux-foundation.org,\n linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,\n david@redhat.com, ziy@nvidia.com, apopple@nvidia.com,\n lorenzo.stoakes@oracle.com, lyude@redhat.com, dakr@kernel.org,\n airlied@gmail.com, simona@ffwll.ch, rcampbell@nvidia.com,\n mpenttil@redhat.com, jgg@nvidia.com, willy@infradead.org,\n linuxppc-dev@lists.ozlabs.org, intel-xe@lists.freedesktop.org, jgg@ziepe.ca,\n Felix.Kuehling@amd.com","References":"<20260107091823.68974-1-jniethe@nvidia.com>\n \n <3586d8f1-a25f-4087-a987-162ccd97c25f@nvidia.com>\n <6a911224-05e5-45ee-8008-e36ef35cbc7b@nvidia.com>\n \n \n \n ","Content-Language":"en-US","From":"Jordan Niethe ","In-Reply-To":"","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit","X-ClientProxiedBy":"BYAPR02CA0071.namprd02.prod.outlook.com\n (2603:10b6:a03:54::48) To DM4PR12MB9072.namprd12.prod.outlook.com\n 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lists.ozlabs.org"}},{"id":3640742,"web_url":"http://patchwork.ozlabs.org/comment/3640742/","msgid":"","date":"2026-01-23T06:25:08","subject":"Re: [PATCH v2 00/11] Remove device private pages from physical\n address space","submitter":{"id":92354,"url":"http://patchwork.ozlabs.org/api/people/92354/","name":"Jordan Niethe","email":"jniethe@nvidia.com"},"content":"Hi,\n\nOn 14/1/26 16:41, Jordan Niethe wrote:\n> Hi,\n> \n> On 9/1/26 17:22, Matthew Brost wrote:\n>> On Fri, Jan 09, 2026 at 12:27:50PM +1100, Jordan Niethe wrote:\n>>> Hi\n>>> On 9/1/26 11:31, Matthew Brost wrote:\n>>>> On Fri, Jan 09, 2026 at 11:01:13AM +1100, Jordan Niethe wrote:\n>>>>> Hi,\n>>>>>\n>>>>> On 8/1/26 16:42, Jordan Niethe wrote:\n>>>>>> Hi,\n>>>>>>\n>>>>>> On 8/1/26 13:25, Jordan Niethe wrote:\n>>>>>>> Hi,\n>>>>>>>\n>>>>>>> On 8/1/26 05:36, Matthew Brost wrote:\n>>>>>>>>\n>>>>>>>> Thanks for the series. For some reason Intel's CI couldn't apply this\n>>>>>>>> series to drm-tip to get results [1]. I'll manually apply this\n>>>>>>>> and run all\n>>>>>>>> our SVM tests and get back you on results + review the changes here. For\n>>>>>>>> future reference if you want to use our CI system, the series must apply\n>>>>>>>> to drm-tip, feel free to rebase this series and just send to intel-xe\n>>>>>>>> list if you want CI\n>>>>>>>\n>>>>>>> Thanks, I'll rebase on drm-tip and send to the intel-xe list.\n>>>>>>\n>>>>>> For reference the rebase on drm-tip on the intel-xe list:\n>>>>>>\n>>>>>> https://patchwork.freedesktop.org/series/159738/\n>>>>>>\n>>>>>> Will watch the CI results.\n>>>>>\n>>>>> The series causes some failures in the intel-xe tests:\n>>>>> https://patchwork.freedesktop.org/series/159738/#rev4\n>>>>>\n>>>>> Working through the failures now.\n>>>>>\n>>>>\n>>>> Yea, I saw the failures. I haven't had time look at the patches on my\n>>>> end quite yet. Scrabling to get a few things in 6.20/7.0 PR, so I may\n>>>> not have bandwidth to look in depth until mid next week but digging is\n>>>> on my TODO list.\n>>>\n>>> Sure, that's completely fine. The failures seem pretty directly related to\n>>> the\n>>> series so I think I'll be able to make good progress.\n>>>\n>>> For example https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159738v4/bat-bmg-2/igt@xe_evict@evict-beng-small.html\n>>>\n>>> It looks like I missed that xe_pagemap_destroy_work() needs to be updated to\n>>> remove the call to devm_release_mem_region() now we are no longer reserving\n>>> a mem\n>>> region.\n>>\n>> +1\n>>\n>> So this is the one I’d be most concerned about [1].\n>> xe_exec_system_allocator is our SVM test, which does almost all the\n>> ridiculous things possible in user space to stress SVM. It’s blowing up\n>> in the core MM—but the source of the bug could be anywhere (e.g., Xe\n>> SVM, GPU SVM, migrate device layer, or core MM). I’ll try to help when I\n>> have bandwidth.\n>>\n>> Matt\n>>\n>> [1] https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159738v4/shard-bmg-9/igt@xe_exec_system_allocator@threads-many-large-execqueues-free-nomemset.html\n> \n> A similar fault in lruvec_stat_mod_folio can be repro'd if\n> memremap_device_private_pagemap() is called with NUMA_NO_NODE instead of (say)\n> numa_node_id() for the nid parameter.\n> \n> The xe_svm driver uses devm_memremap_device_private_pagemap() which uses\n> dev_to_node() for the nid parameter. Suspect this is causing something similar\n> to happen.\n> \n> When memremap_pages() calls pagemap_range() we have the following logic:\n> \n>         if (nid < 0)\n>                 nid = numa_mem_id();\n> \n> I think we might need to add this to memremap_device_private_pagemap() to handle\n> the NUMA_NO_NODE case. Still confirming.\n\nThis was the problem, fixed in v3.\n\n> \n> Thanks,\n> Jordan.\n> \n>>\n>>>\n>>>\n>>> Thanks,\n>>> Jordan.\n>>>\n>>>>\n>>>> Matt\n>>>>\n>>>>> Thanks,\n>>>>> Jordan.\n>>>>>\n>>>>>>\n>>>>>> Thanks,\n>>>>>> Jordan.\n>>>>>>\n>>>>>>>\n>>>>>>> Jordan.\n>>>>>>>\n>>>>>>>>\n>>>>>>>> I was also wondering if Nvidia could help review one our core MM patches\n>>>>>>>> [2] which is gating enabling 2M device pages too?\n>>>>>>>>\n>>>>>>>> Matt\n>>>>>>>>\n>>>>>>>> [1] https://patchwork.freedesktop.org/series/159738/\n>>>>>>>> [2] https://patchwork.freedesktop.org/patch/694775/?series=159119&rev=1\n>>>>>>>\n>>>>>>>\n>>>>>>\n>>>>>\n>>>\n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 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